Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10541 |
1 |
|
T2 |
9 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
442 |
1 |
|
T2 |
8 |
|
T22 |
1 |
|
T27 |
9 |
| others[2] |
486 |
1 |
|
T2 |
11 |
|
T5 |
1 |
|
T9 |
1 |
| others[3] |
822 |
1 |
|
T2 |
20 |
|
T19 |
2 |
|
T7 |
1 |
| false |
244 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T27 |
5 |
| true |
2212 |
1 |
|
T2 |
49 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10283 |
1 |
|
T2 |
11 |
|
T13 |
2 |
|
T7 |
1 |
| others[1] |
263 |
1 |
|
T2 |
9 |
|
T30 |
1 |
|
T27 |
11 |
| others[2] |
266 |
1 |
|
T2 |
8 |
|
T47 |
1 |
|
T27 |
7 |
| others[3] |
426 |
1 |
|
T2 |
12 |
|
T27 |
15 |
|
T23 |
8 |
| false |
131 |
1 |
|
T2 |
5 |
|
T27 |
3 |
|
T23 |
10 |
| true |
3378 |
1 |
|
T1 |
1 |
|
T2 |
56 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10298 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T13 |
2 |
| others[1] |
256 |
1 |
|
T2 |
12 |
|
T27 |
16 |
|
T23 |
11 |
| others[2] |
248 |
1 |
|
T2 |
8 |
|
T27 |
14 |
|
T23 |
9 |
| others[3] |
415 |
1 |
|
T2 |
16 |
|
T27 |
18 |
|
T45 |
1 |
| false |
135 |
1 |
|
T2 |
4 |
|
T22 |
1 |
|
T27 |
6 |
| true |
3395 |
1 |
|
T1 |
1 |
|
T2 |
54 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10834 |
1 |
|
T2 |
28 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
818 |
1 |
|
T2 |
18 |
|
T9 |
1 |
|
T27 |
28 |
| others[2] |
835 |
1 |
|
T2 |
21 |
|
T4 |
1 |
|
T6 |
1 |
| others[3] |
1333 |
1 |
|
T2 |
27 |
|
T5 |
1 |
|
T9 |
1 |
| false |
429 |
1 |
|
T2 |
7 |
|
T27 |
13 |
|
T23 |
10 |
| true |
498 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10833 |
1 |
|
T2 |
15 |
|
T4 |
1 |
|
T13 |
2 |
| others[1] |
795 |
1 |
|
T2 |
21 |
|
T9 |
1 |
|
T27 |
19 |
| others[2] |
824 |
1 |
|
T2 |
25 |
|
T5 |
1 |
|
T6 |
1 |
| others[3] |
1404 |
1 |
|
T2 |
25 |
|
T47 |
1 |
|
T27 |
42 |
| false |
382 |
1 |
|
T2 |
15 |
|
T27 |
6 |
|
T140 |
1 |
| true |
509 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2473 |
1 |
|
T2 |
10 |
|
T48 |
26 |
|
T33 |
34 |
| others[1] |
2576 |
1 |
|
T2 |
14 |
|
T13 |
1 |
|
T48 |
26 |
| others[2] |
2572 |
1 |
|
T2 |
10 |
|
T5 |
1 |
|
T48 |
26 |
| others[3] |
4184 |
1 |
|
T2 |
14 |
|
T3 |
1 |
|
T4 |
1 |
| false |
1393 |
1 |
|
T2 |
6 |
|
T48 |
13 |
|
T33 |
22 |
| true |
1549 |
1 |
|
T1 |
1 |
|
T2 |
47 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10309 |
1 |
|
T2 |
12 |
|
T13 |
2 |
|
T47 |
1 |
| others[1] |
259 |
1 |
|
T2 |
12 |
|
T3 |
1 |
|
T9 |
2 |
| others[2] |
285 |
1 |
|
T2 |
4 |
|
T9 |
1 |
|
T8 |
1 |
| others[3] |
444 |
1 |
|
T1 |
1 |
|
T2 |
18 |
|
T9 |
1 |
| false |
126 |
1 |
|
T2 |
7 |
|
T27 |
4 |
|
T23 |
3 |
| true |
3324 |
1 |
|
T2 |
48 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10506 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T13 |
2 |
| others[1] |
475 |
1 |
|
T2 |
11 |
|
T9 |
2 |
|
T19 |
1 |
| others[2] |
472 |
1 |
|
T2 |
8 |
|
T9 |
1 |
|
T27 |
10 |
| others[3] |
784 |
1 |
|
T1 |
1 |
|
T2 |
22 |
|
T9 |
1 |
| false |
245 |
1 |
|
T2 |
6 |
|
T27 |
3 |
|
T23 |
6 |
| true |
2265 |
1 |
|
T2 |
48 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10340 |
1 |
|
T2 |
10 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
264 |
1 |
|
T2 |
12 |
|
T27 |
10 |
|
T23 |
7 |
| others[2] |
255 |
1 |
|
T2 |
12 |
|
T6 |
1 |
|
T27 |
10 |
| others[3] |
443 |
1 |
|
T2 |
12 |
|
T47 |
1 |
|
T30 |
1 |
| false |
136 |
1 |
|
T2 |
4 |
|
T27 |
6 |
|
T23 |
4 |
| true |
3309 |
1 |
|
T1 |
1 |
|
T2 |
51 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10315 |
1 |
|
T2 |
10 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
264 |
1 |
|
T2 |
11 |
|
T9 |
2 |
|
T8 |
1 |
| others[2] |
269 |
1 |
|
T2 |
10 |
|
T27 |
9 |
|
T23 |
14 |
| others[3] |
422 |
1 |
|
T2 |
19 |
|
T4 |
1 |
|
T5 |
1 |
| false |
121 |
1 |
|
T2 |
4 |
|
T27 |
6 |
|
T23 |
6 |
| true |
3356 |
1 |
|
T1 |
1 |
|
T2 |
47 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10886 |
1 |
|
T2 |
19 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
824 |
1 |
|
T2 |
21 |
|
T27 |
17 |
|
T140 |
2 |
| others[2] |
793 |
1 |
|
T2 |
19 |
|
T5 |
1 |
|
T19 |
1 |
| others[3] |
1346 |
1 |
|
T2 |
30 |
|
T9 |
2 |
|
T41 |
1 |
| false |
403 |
1 |
|
T2 |
12 |
|
T4 |
1 |
|
T27 |
10 |
| true |
495 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10850 |
1 |
|
T2 |
22 |
|
T4 |
1 |
|
T13 |
2 |
| others[1] |
861 |
1 |
|
T2 |
19 |
|
T6 |
1 |
|
T27 |
13 |
| others[2] |
787 |
1 |
|
T2 |
21 |
|
T5 |
1 |
|
T47 |
1 |
| others[3] |
1338 |
1 |
|
T2 |
33 |
|
T27 |
37 |
|
T140 |
1 |
| false |
393 |
1 |
|
T2 |
6 |
|
T9 |
1 |
|
T27 |
14 |
| true |
518 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2596 |
1 |
|
T2 |
7 |
|
T5 |
1 |
|
T48 |
23 |
| others[1] |
2505 |
1 |
|
T2 |
6 |
|
T13 |
1 |
|
T48 |
29 |
| others[2] |
2490 |
1 |
|
T2 |
10 |
|
T3 |
1 |
|
T48 |
19 |
| others[3] |
4298 |
1 |
|
T2 |
21 |
|
T4 |
1 |
|
T13 |
1 |
| false |
1318 |
1 |
|
T2 |
8 |
|
T48 |
16 |
|
T6 |
1 |
| true |
1540 |
1 |
|
T1 |
1 |
|
T2 |
49 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10315 |
1 |
|
T2 |
5 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
281 |
1 |
|
T2 |
9 |
|
T27 |
14 |
|
T45 |
1 |
| others[2] |
297 |
1 |
|
T2 |
10 |
|
T27 |
14 |
|
T40 |
1 |
| others[3] |
492 |
1 |
|
T2 |
19 |
|
T9 |
1 |
|
T7 |
1 |
| false |
131 |
1 |
|
T2 |
6 |
|
T47 |
1 |
|
T27 |
2 |
| true |
3231 |
1 |
|
T1 |
1 |
|
T2 |
52 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10505 |
1 |
|
T2 |
12 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
470 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T19 |
1 |
| others[2] |
462 |
1 |
|
T2 |
11 |
|
T27 |
8 |
|
T23 |
8 |
| others[3] |
848 |
1 |
|
T2 |
18 |
|
T9 |
1 |
|
T14 |
1 |
| false |
238 |
1 |
|
T2 |
2 |
|
T19 |
1 |
|
T27 |
4 |
| true |
2224 |
1 |
|
T2 |
49 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10299 |
1 |
|
T2 |
7 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
264 |
1 |
|
T2 |
5 |
|
T27 |
10 |
|
T45 |
1 |
| others[2] |
252 |
1 |
|
T2 |
14 |
|
T5 |
1 |
|
T6 |
1 |
| others[3] |
449 |
1 |
|
T2 |
16 |
|
T3 |
1 |
|
T8 |
1 |
| false |
166 |
1 |
|
T2 |
5 |
|
T27 |
4 |
|
T23 |
8 |
| true |
3317 |
1 |
|
T1 |
1 |
|
T2 |
54 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10304 |
1 |
|
T2 |
17 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
242 |
1 |
|
T2 |
8 |
|
T27 |
7 |
|
T23 |
13 |
| others[2] |
263 |
1 |
|
T2 |
8 |
|
T5 |
1 |
|
T9 |
1 |
| others[3] |
452 |
1 |
|
T2 |
15 |
|
T9 |
1 |
|
T8 |
1 |
| false |
133 |
1 |
|
T2 |
9 |
|
T3 |
1 |
|
T9 |
1 |
| true |
3353 |
1 |
|
T1 |
1 |
|
T2 |
44 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10878 |
1 |
|
T2 |
19 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
798 |
1 |
|
T2 |
18 |
|
T27 |
21 |
|
T140 |
2 |
| others[2] |
801 |
1 |
|
T2 |
21 |
|
T4 |
1 |
|
T27 |
16 |
| others[3] |
1372 |
1 |
|
T2 |
35 |
|
T5 |
1 |
|
T19 |
1 |
| false |
394 |
1 |
|
T2 |
8 |
|
T27 |
5 |
|
T140 |
3 |
| true |
504 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10813 |
1 |
|
T2 |
25 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
791 |
1 |
|
T2 |
18 |
|
T4 |
1 |
|
T9 |
1 |
| others[2] |
821 |
1 |
|
T2 |
20 |
|
T5 |
1 |
|
T9 |
1 |
| others[3] |
1394 |
1 |
|
T2 |
31 |
|
T27 |
27 |
|
T140 |
5 |
| false |
404 |
1 |
|
T2 |
7 |
|
T27 |
9 |
|
T23 |
9 |
| true |
524 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2528 |
1 |
|
T2 |
8 |
|
T13 |
1 |
|
T48 |
30 |
| others[1] |
2554 |
1 |
|
T2 |
6 |
|
T48 |
21 |
|
T33 |
33 |
| others[2] |
2515 |
1 |
|
T2 |
12 |
|
T3 |
1 |
|
T48 |
27 |
| others[3] |
4308 |
1 |
|
T2 |
21 |
|
T4 |
1 |
|
T13 |
1 |
| false |
1278 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T48 |
9 |
| true |
1564 |
1 |
|
T1 |
1 |
|
T2 |
52 |
|
T9 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10278 |
1 |
|
T2 |
9 |
|
T13 |
2 |
|
T48 |
133 |
| others[1] |
274 |
1 |
|
T2 |
10 |
|
T9 |
2 |
|
T6 |
1 |
| others[2] |
277 |
1 |
|
T2 |
7 |
|
T27 |
10 |
|
T23 |
11 |
| others[3] |
442 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T3 |
1 |
| false |
159 |
1 |
|
T2 |
3 |
|
T30 |
1 |
|
T27 |
4 |
| true |
3317 |
1 |
|
T2 |
59 |
|
T4 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10490 |
1 |
|
T2 |
8 |
|
T13 |
2 |
|
T9 |
2 |
| others[1] |
462 |
1 |
|
T2 |
13 |
|
T9 |
1 |
|
T27 |
7 |
| others[2] |
491 |
1 |
|
T2 |
16 |
|
T9 |
1 |
|
T30 |
1 |
| others[3] |
848 |
1 |
|
T2 |
17 |
|
T5 |
1 |
|
T9 |
1 |
| false |
250 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| true |
2206 |
1 |
|
T1 |
1 |
|
T2 |
46 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10291 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T13 |
2 |
| others[1] |
261 |
1 |
|
T2 |
7 |
|
T27 |
9 |
|
T23 |
11 |
| others[2] |
274 |
1 |
|
T2 |
10 |
|
T27 |
8 |
|
T23 |
12 |
| others[3] |
431 |
1 |
|
T2 |
21 |
|
T27 |
12 |
|
T45 |
1 |
| false |
157 |
1 |
|
T2 |
7 |
|
T27 |
9 |
|
T23 |
6 |
| true |
3333 |
1 |
|
T1 |
1 |
|
T2 |
48 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10281 |
1 |
|
T2 |
14 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
222 |
1 |
|
T2 |
10 |
|
T3 |
1 |
|
T27 |
8 |
| others[2] |
286 |
1 |
|
T2 |
10 |
|
T27 |
14 |
|
T23 |
14 |
| others[3] |
407 |
1 |
|
T2 |
16 |
|
T9 |
2 |
|
T27 |
20 |
| false |
119 |
1 |
|
T2 |
4 |
|
T27 |
3 |
|
T46 |
1 |
| true |
3432 |
1 |
|
T1 |
1 |
|
T2 |
47 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10888 |
1 |
|
T2 |
21 |
|
T13 |
2 |
|
T9 |
1 |
| others[1] |
810 |
1 |
|
T2 |
18 |
|
T5 |
1 |
|
T9 |
1 |
| others[2] |
832 |
1 |
|
T2 |
29 |
|
T4 |
1 |
|
T19 |
1 |
| others[3] |
1359 |
1 |
|
T2 |
23 |
|
T9 |
1 |
|
T47 |
1 |
| false |
372 |
1 |
|
T2 |
10 |
|
T27 |
6 |
|
T23 |
9 |
| true |
486 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
3 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |