Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	233514	1		T1	10		T2	100		T3	20
auto[FlashEraseBank]	200142	1		T1	5		T2	1042		T4	505

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	243726	1		T1	14		T2	453		T3	20
auto[FlashOpProgram]	169420	1		T1	1		T2	647		T4	1240
auto[FlashOpErase]	16510	1		T2	42		T47	29		T48	205
auto[FlashOpInvalid]	4000	1		T145	200		T193	200		T201	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	243726	1		T1	14		T2	453		T3	20
op[FlashOpProgram]	169420	1		T1	1		T2	647		T4	1240
op[FlashOpErase]	16510	1		T2	42		T47	29		T48	205
read_erase_read	740	1		T2	5		T47	22		T27	12
read_prog_read	1196	1		T1	1		T2	2		T22	6

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	292881	1		T1	1		T2	99		T3	20
auto[FlashPartInfo]	137429	1		T1	13		T2	1042		T4	213
auto[FlashPartInfo1]	790	1		T5	3		T7	17		T8	2
auto[FlashPartInfo2]	2556	1		T1	1		T2	1		T4	8

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	179410	1		T1	1		T2	36		T3	20
auto[FlashPartData]	auto[FlashOpProgram]	105801	1		T2	39		T4	1019		T9	3
auto[FlashPartData]	auto[FlashOpErase]	3742	1		T2	24		T47	8		T27	26
auto[FlashPartData]	auto[FlashOpInvalid]	3928	1		T145	198		T193	200		T201	194
auto[FlashPartInfo]	auto[FlashOpRead]	61934	1		T1	12		T2	416		T19	88
auto[FlashPartInfo]	auto[FlashOpProgram]	62685	1		T1	1		T2	608		T4	213
auto[FlashPartInfo]	auto[FlashOpErase]	12750	1		T2	18		T47	21		T48	205
auto[FlashPartInfo]	auto[FlashOpInvalid]	60	1		T145	2		T201	6		T357	2
auto[FlashPartInfo1]	auto[FlashOpRead]	711	1		T5	3		T7	17		T8	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	68	1		T71	32		T149	1		T358	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T62	2		T149	1		T358	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T149	2		T358	2		T359	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1671	1		T1	1		T2	1		T5	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	866	1		T4	8		T6	13		T22	10
auto[FlashPartInfo2]	auto[FlashOpErase]	13	1		T298	7		T156	1		T360	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T156	2		T360	2		T361	2