Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31933	1		T2	12		T47	2		T48	392
auto[1]	8	1		T294	2		T295	2		T296	1
auto[2]	193	1		T75	1		T51	4		T52	4
auto[3]	270	1		T1	1		T47	35		T49	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8129	1		T2	3		T47	10		T48	98
evic_idx[1]	8104	1		T2	3		T47	9		T48	98
evic_idx[2]	8088	1		T1	1		T2	3		T47	11
evic_idx[3]	8083	1		T2	3		T47	7		T48	98

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31289	1		T47	37		T48	392		T33	484
evic_op[2]	507	1		T1	1		T49	2		T40	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7755	1		T48	98		T33	121		T28	1
evic_idx[0]	evic_op[1]	auto[2]	13	1		T297	13		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	77	1		T47	10		T254	33		T298	17
evic_idx[0]	evic_op[2]	auto[0]	78	1		T24	1		T210	1		T144	1
evic_idx[0]	evic_op[2]	auto[1]	3	1		T294	1		T295	1		T299	1
evic_idx[0]	evic_op[2]	auto[2]	39	1		T75	1		T300	8		T301	6
evic_idx[0]	evic_op[2]	auto[3]	12	1		T187	1		T188	1		T302	1
evic_idx[1]	evic_op[1]	auto[0]	7755	1		T48	98		T33	121		T28	1
evic_idx[1]	evic_op[1]	auto[2]	11	1		T297	11		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	61	1		T47	9		T254	13		T298	18
evic_idx[1]	evic_op[2]	auto[0]	80	1		T24	1		T39	1		T210	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T294	1		T295	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	30	1		T300	8		T301	9		T189	3
evic_idx[1]	evic_op[2]	auto[3]	13	1		T190	1		T303	1		T251	1
evic_idx[2]	evic_op[1]	auto[0]	7757	1		T47	2		T48	98		T33	121
evic_idx[2]	evic_op[1]	auto[2]	11	1		T297	11		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	48	1		T47	9		T254	9		T298	13
evic_idx[2]	evic_op[2]	auto[0]	79	1		T24	1		T210	1		T144	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T296	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	30	1		T300	7		T301	7		T189	7
evic_idx[2]	evic_op[2]	auto[3]	10	1		T1	1		T49	1		T40	1
evic_idx[3]	evic_op[1]	auto[0]	7755	1		T48	98		T33	121		T28	1
evic_idx[3]	evic_op[1]	auto[2]	12	1		T297	12		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	34	1		T47	7		T254	9		T298	8
evic_idx[3]	evic_op[2]	auto[0]	82	1		T24	1		T210	1		T144	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T304	1		T299	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	31	1		T300	6		T301	3		T189	5
evic_idx[3]	evic_op[2]	auto[3]	15	1		T49	1		T76	1		T143	1