Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
instr_type_cp 3 0 3 100.00 100 1 1 0
key_cp 2 0 2 100.00 100 1 1 2


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_instr_cross 6 0 6 100.00 100 1 1 0


Summary for Variable instr_type_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for instr_type_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others 6488 1 T42 165 T43 102 T44 81
instr_types[0] 7649 1 T42 315 T43 164 T44 215
instr_types[1] 4232158 1 T1 7 T5 15909 T19 354



Summary for Variable key_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4244245 1 T1 7 T5 15909 T19 354
auto[1] 2050 1 T42 137 T43 173 T44 161



Summary for Cross key_instr_cross

Samples crossed: key_cp instr_type_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for key_instr_cross

Bins
key_cpinstr_type_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] others 6075 1 T42 109 T43 50 T44 68
auto[0] instr_types[0] 6854 1 T42 249 T43 150 T44 153
auto[0] instr_types[1] 4231316 1 T1 7 T5 15909 T19 354
auto[1] others 413 1 T42 56 T43 52 T44 13
auto[1] instr_types[0] 795 1 T42 66 T43 14 T44 62
auto[1] instr_types[1] 842 1 T42 15 T43 107 T44 86

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%