Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	41737	1		T120	5159		T60	2985		T121	4843
prog_lvl[2]	1556	1		T60	1		T362	657		T363	156
prog_lvl[3]	2	1		T362	1		T364	1		-	-

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	2427	1		T30	6		T20	594		T154	77
rd_lvl[2]	30292	1		T7	3		T30	13		T20	659
rd_lvl[3]	22099	1		T7	52		T30	21		T154	596
rd_lvl[4]	12091	1		T30	16		T178	1088		T61	2290
rd_lvl[5]	11366	1		T30	6		T178	461		T61	866
rd_lvl[6]	12493	1		T30	2		T154	43		T182	27
rd_lvl[7]	12065	1		T30	891		T178	1		T365	325
rd_lvl[8]	8980	1		T178	8		T365	606		T366	1115
rd_lvl[9]	5292	1		T30	674		T59	515		T367	434
rd_lvl[10]	6394	1		T30	471		T59	242		T244	480
rd_lvl[11]	2822	1		T244	551		T368	417		T365	5
rd_lvl[12]	4661	1		T30	1		T192	196		T365	66
rd_lvl[13]	6330	1		T7	535		T30	12		T59	1
rd_lvl[14]	5412	1		T7	427		T248	612		T186	561
rd_lvl[15]	3559	1		T248	491		T186	550		T369	421