Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	326258	1		T1	1		T2	2		T3	2
all_pins[1]	326258	1		T1	1		T2	2		T3	2
all_pins[2]	326258	1		T1	1		T2	2		T3	2
all_pins[3]	326258	1		T1	1		T2	2		T3	2
all_pins[4]	326258	1		T1	1		T2	2		T3	2
all_pins[5]	326258	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1581228	1		T1	6		T2	12		T3	12
values[0x1]	376320	1		T7	2462		T30	3284		T20	2275
transitions[0x0=>0x1]	353127	1		T7	2386		T30	2394		T20	2275
transitions[0x1=>0x0]	353138	1		T7	2386		T30	2394		T20	2275

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	257248	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	69010	1		T120	2990		T60	2080		T168	4208
all_pins[0]	transitions[0x0=>0x1]	68995	1		T120	2990		T60	2080		T168	4208
all_pins[0]	transitions[0x1=>0x0]	48988	1		T120	5159		T60	3981		T121	4843
all_pins[1]	values[0x0]	277255	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	49003	1		T120	5159		T60	3981		T121	4843
all_pins[1]	transitions[0x0=>0x1]	48993	1		T120	5159		T60	3981		T121	4843
all_pins[1]	transitions[0x1=>0x0]	10133	1		T7	408		T30	13		T59	1
all_pins[2]	values[0x0]	316115	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	10143	1		T7	408		T30	13		T59	1
all_pins[2]	transitions[0x0=>0x1]	8335	1		T7	408		T30	13		T59	1
all_pins[2]	transitions[0x1=>0x0]	149892	1		T7	1042		T30	2113		T20	1253
all_pins[3]	values[0x0]	174558	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	151700	1		T7	1042		T30	2113		T20	1253
all_pins[3]	transitions[0x0=>0x1]	130381	1		T7	966		T30	1223		T20	1253
all_pins[3]	transitions[0x1=>0x0]	75066	1		T7	936		T30	268		T20	1022
all_pins[4]	values[0x0]	229873	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	96385	1		T7	1012		T30	1158		T20	1022
all_pins[4]	transitions[0x0=>0x1]	96369	1		T7	1012		T30	1158		T20	1022
all_pins[4]	transitions[0x1=>0x0]	63	1		T235	2		T236	1		T308	2
all_pins[5]	values[0x0]	326179	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	79	1		T235	2		T236	1		T308	3
all_pins[5]	transitions[0x0=>0x1]	54	1		T235	2		T308	1		T309	4
all_pins[5]	transitions[0x1=>0x0]	68996	1		T120	2990		T60	2080		T168	4208