Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T235	4		T236	4		T237	7
all_values[1]	278	1		T235	4		T236	4		T237	7
all_values[2]	278	1		T235	4		T236	4		T237	7
all_values[3]	278	1		T235	4		T236	4		T237	7
all_values[4]	278	1		T235	4		T236	4		T237	7
all_values[5]	278	1		T235	4		T236	4		T237	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	897	1		T235	11		T236	18		T237	21
auto[1]	771	1		T235	13		T236	6		T237	21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	639	1		T235	14		T236	11		T237	16
auto[1]	1029	1		T235	10		T236	13		T237	26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	978	1		T235	19		T236	16		T237	23
auto[1]	690	1		T235	5		T236	8		T237	19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	54	1		T235	1		T236	1		T237	4
all_values[0]	auto[0]	auto[0]	auto[1]	20	1		T236	1		T237	1		T310	1
all_values[0]	auto[0]	auto[1]	auto[0]	60	1		T235	3		T308	1		T309	3
all_values[0]	auto[0]	auto[1]	auto[1]	28	1		T308	2		T311	2		T312	1
all_values[0]	auto[1]	auto[0]	auto[1]	58	1		T236	2		T237	2		T313	1
all_values[0]	auto[1]	auto[1]	auto[1]	58	1		T308	3		T309	1		T311	1
all_values[1]	auto[0]	auto[0]	auto[0]	65	1		T235	1		T237	1		T308	2
all_values[1]	auto[0]	auto[0]	auto[1]	29	1		T237	1		T308	2		T309	2
all_values[1]	auto[0]	auto[1]	auto[0]	56	1		T236	3		T309	1		T313	1
all_values[1]	auto[0]	auto[1]	auto[1]	25	1		T235	2		T237	1		T308	2
all_values[1]	auto[1]	auto[0]	auto[1]	60	1		T235	1		T236	1		T237	1
all_values[1]	auto[1]	auto[1]	auto[1]	43	1		T237	3		T308	1		T309	1
all_values[2]	auto[0]	auto[0]	auto[0]	66	1		T235	1		T236	3		T313	1
all_values[2]	auto[0]	auto[0]	auto[1]	24	1		T235	1		T309	1		T314	1
all_values[2]	auto[0]	auto[1]	auto[0]	55	1		T236	1		T237	4		T308	4
all_values[2]	auto[0]	auto[1]	auto[1]	21	1		T237	2		T309	1		T313	1
all_values[2]	auto[1]	auto[0]	auto[1]	61	1		T235	2		T308	2		T309	3
all_values[2]	auto[1]	auto[1]	auto[1]	51	1		T237	1		T308	1		T313	1
all_values[3]	auto[0]	auto[0]	auto[0]	48	1		T236	2		T237	1		T308	2
all_values[3]	auto[0]	auto[0]	auto[1]	40	1		T235	1		T236	1		T237	1
all_values[3]	auto[0]	auto[1]	auto[0]	37	1		T235	2		T237	2		T309	2
all_values[3]	auto[0]	auto[1]	auto[1]	34	1		T309	1		T313	1		T310	1
all_values[3]	auto[1]	auto[0]	auto[1]	63	1		T235	1		T236	1		T237	1
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T237	2		T308	3		T309	2
all_values[4]	auto[0]	auto[0]	auto[0]	66	1		T236	1		T308	4		T313	3
all_values[4]	auto[0]	auto[0]	auto[1]	33	1		T309	3		T315	3		T316	1
all_values[4]	auto[0]	auto[1]	auto[0]	40	1		T235	4		T237	2		T308	2
all_values[4]	auto[0]	auto[1]	auto[1]	21	1		T236	1		T317	4		T318	1
all_values[4]	auto[1]	auto[0]	auto[1]	67	1		T236	1		T237	3		T309	1
all_values[4]	auto[1]	auto[1]	auto[1]	51	1		T236	1		T237	2		T308	1
all_values[5]	auto[0]	auto[0]	auto[0]	52	1		T235	2		T309	1		T313	3
all_values[5]	auto[0]	auto[0]	auto[1]	30	1		T236	2		T237	1		T308	1
all_values[5]	auto[0]	auto[1]	auto[0]	40	1		T237	2		T309	1		T313	1
all_values[5]	auto[0]	auto[1]	auto[1]	34	1		T235	1		T308	1		T309	2
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T236	2		T237	4		T308	3
all_values[5]	auto[1]	auto[1]	auto[1]	61	1		T235	1		T308	2		T309	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal