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LINE 11939
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 11939
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T7,T47 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T22,T30 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T22,T30 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T22,T30 |
1 | 1 | Covered | T6,T22,T30 |
LINE 11939
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T6,T22,T30 |
LINE 11939
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[28] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[29] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[30] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[31] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[32] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[33] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[34] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[35] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[36] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T6,T22,T30 |
LINE 11939
SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[43] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[44] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T22,T30 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[57] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[61] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[64] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[66] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[69] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[71] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T6,T22,T30 |
LINE 11939
SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T6,T22,T30 |
LINE 11939
SUB-EXPRESSION (addr_hit[73] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[74] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[75] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[76] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[77] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[78] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[79] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[80] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[81] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[82] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[83] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[84] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[85] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[86] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[87] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[88] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[89] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[90] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T6,T22,T30 |
LINE 11939
SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T13,T6 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 11939
SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[94] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T6 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[96] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T9,T14 |
LINE 11939
SUB-EXPRESSION (addr_hit[97] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[98] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[99] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[100] & ((|(4'b0111 & (~reg_be)))))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T22,T30 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[101] & ((|(4'b0111 & (~reg_be)))))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[102] & ((|(4'b1 & (~reg_be)))))
------1------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[103] & ((|(4'b1 & (~reg_be)))))
------1------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[104] & ((|(4'b1111 & (~reg_be)))))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[105] & ((|(4'b0011 & (~reg_be)))))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
------1------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T22 |
1 | 1 | Covered | T1,T6,T22 |
LINE 11939
SUB-EXPRESSION (addr_hit[107] & ((|(4'b0011 & (~reg_be)))))
------1------ -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T22,T30 |
1 | 1 | Covered | T1,T7,T6 |
LINE 12051
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T211,T213,T215 |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 12064
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T7,T47 |
1 | 1 | 0 | Covered | T195,T212,T213 |
1 | 1 | 1 | Covered | T1,T7,T47 |
LINE 12077
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T195,T211,T212 |
1 | 1 | 1 | Covered | T235,T236,T237 |
LINE 12090
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T171,T211,T213 |
1 | 1 | 1 | Covered | T152,T166,T167 |
LINE 12101
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T171,T211,T238 |
1 | 1 | 1 | Not Covered | |
LINE 12104
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T169,T195,T212 |
1 | 1 | 1 | Covered | T42,T43,T44 |
LINE 12107
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T169,T195,T212 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 12110
EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T239 |
1 | 1 | 1 | Covered | T171,T213,T214 |
LINE 12111
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T212,T213,T215 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 12126
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T169,T211,T212 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 12129
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T195,T211,T238 |
1 | 1 | 1 | Covered | T140,T161,T94 |
LINE 12134
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T169,T171,T211 |
1 | 1 | 1 | Covered | T50,T51,T52 |
LINE 12137
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T169,T211,T212 |
1 | 1 | 1 | Covered | T54,T55,T56 |
LINE 12140
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T211,T212,T213 |
1 | 1 | 1 | Covered | T54,T55,T56 |
LINE 12143
EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T169,T171,T195 |
1 | 1 | 1 | Covered | T54,T55,T56 |
LINE 12146
EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T169,T211,T212 |
1 | 1 | 1 | Covered | T54,T55,T56 |
LINE 12149
EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T169,T211,T213 |
1 | 1 | 1 | Covered | T54,T55,T56 |
LINE 12152
EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T211,T212,T213 |
1 | 1 | 1 | Covered | T54,T55,T56 |
LINE 12155
EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T6,T22,T30 |
1 | 1 | 0 | Covered | T211,T212,T213 |
1 | 1 | 1 | Covered | T54,T55,T56 |
LINE 12158
EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T6,T22 |
1 | 1 | 0 | Covered | T211,T212,T215 |
1 | 1 | 1 | Covered | T54,T55,T56 |
LINE 12161
EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T211,T212,T213 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 12176
EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T171,T211,T212 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 12191
EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T169,T171,T212 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 12206
EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T169,T211,T212 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 12221
EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T169,T195,T211 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 12236
EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T169,T212,T213 |
1 | 1 | 1 | Covered | T1,T2,T3 |