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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.33 94.10 98.95 90.48 97.16 98.30 98.40


Total test records in report: 1204
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T233 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1448698899 Feb 18 01:38:10 PM PST 24 Feb 18 01:39:11 PM PST 24 187506100 ps
T1068 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3751982202 Feb 18 01:38:58 PM PST 24 Feb 18 01:39:51 PM PST 24 33509300 ps
T171 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.586283184 Feb 18 01:39:13 PM PST 24 Feb 18 01:40:08 PM PST 24 92415000 ps
T1069 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1976849587 Feb 18 01:39:02 PM PST 24 Feb 18 01:39:55 PM PST 24 30018400 ps
T195 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.402533816 Feb 18 01:38:54 PM PST 24 Feb 18 01:39:56 PM PST 24 139124800 ps
T234 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.885658255 Feb 18 01:38:33 PM PST 24 Feb 18 01:39:49 PM PST 24 336120900 ps
T237 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1486691606 Feb 18 01:39:19 PM PST 24 Feb 18 01:40:12 PM PST 24 14677600 ps
T172 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2621604369 Feb 18 01:38:52 PM PST 24 Feb 18 01:52:11 PM PST 24 2852061700 ps
T211 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4019117617 Feb 18 01:38:35 PM PST 24 Feb 18 01:39:36 PM PST 24 63227400 ps
T261 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3485609717 Feb 18 01:38:56 PM PST 24 Feb 18 01:39:56 PM PST 24 51107400 ps
T1070 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3916886340 Feb 18 01:38:49 PM PST 24 Feb 18 01:39:42 PM PST 24 17391100 ps
T308 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1893015758 Feb 18 01:39:18 PM PST 24 Feb 18 01:40:12 PM PST 24 50268700 ps
T279 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1898752110 Feb 18 01:38:06 PM PST 24 Feb 18 01:39:55 PM PST 24 1271670000 ps
T1071 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.533350173 Feb 18 01:38:36 PM PST 24 Feb 18 01:39:30 PM PST 24 14985100 ps
T212 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2002640053 Feb 18 01:38:49 PM PST 24 Feb 18 01:39:48 PM PST 24 52924800 ps
T213 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4083468332 Feb 18 01:38:54 PM PST 24 Feb 18 01:39:51 PM PST 24 344410100 ps
T262 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3875019307 Feb 18 01:38:36 PM PST 24 Feb 18 01:39:54 PM PST 24 412041500 ps
T196 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1398509193 Feb 18 01:38:11 PM PST 24 Feb 18 01:39:12 PM PST 24 38941800 ps
T280 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2976151840 Feb 18 01:38:41 PM PST 24 Feb 18 01:39:37 PM PST 24 31873100 ps
T214 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.804214017 Feb 18 01:38:27 PM PST 24 Feb 18 01:39:33 PM PST 24 136119200 ps
T215 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1166469334 Feb 18 01:38:35 PM PST 24 Feb 18 01:39:41 PM PST 24 234599800 ps
T263 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1695255238 Feb 18 01:39:37 PM PST 24 Feb 18 01:40:48 PM PST 24 221515400 ps
T216 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2191494028 Feb 18 01:39:09 PM PST 24 Feb 18 01:52:18 PM PST 24 3248330900 ps
T1072 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4122462490 Feb 18 01:38:04 PM PST 24 Feb 18 01:39:19 PM PST 24 218062400 ps
T309 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3154450058 Feb 18 01:39:15 PM PST 24 Feb 18 01:40:18 PM PST 24 30609500 ps
T264 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2660673252 Feb 18 01:38:35 PM PST 24 Feb 18 01:39:34 PM PST 24 66254300 ps
T313 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.51091304 Feb 18 01:39:21 PM PST 24 Feb 18 01:40:15 PM PST 24 28504800 ps
T1073 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4140525653 Feb 18 01:38:52 PM PST 24 Feb 18 01:40:00 PM PST 24 173619100 ps
T265 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4227993262 Feb 18 01:38:52 PM PST 24 Feb 18 01:40:14 PM PST 24 735483800 ps
T1074 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.872346758 Feb 18 01:38:58 PM PST 24 Feb 18 01:39:56 PM PST 24 20764100 ps
T311 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2511443459 Feb 18 01:38:24 PM PST 24 Feb 18 01:39:18 PM PST 24 86015300 ps
T310 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.640987745 Feb 18 01:39:25 PM PST 24 Feb 18 01:40:26 PM PST 24 119172100 ps
T315 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.616358633 Feb 18 01:37:57 PM PST 24 Feb 18 01:38:56 PM PST 24 18560500 ps
T314 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2438205103 Feb 18 01:39:15 PM PST 24 Feb 18 01:40:18 PM PST 24 29832500 ps
T238 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2551748707 Feb 18 01:39:00 PM PST 24 Feb 18 01:39:56 PM PST 24 83734500 ps
T312 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1959357208 Feb 18 01:39:12 PM PST 24 Feb 18 01:40:12 PM PST 24 42242500 ps
T316 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1516607782 Feb 18 01:38:42 PM PST 24 Feb 18 01:39:35 PM PST 24 56830300 ps
T1075 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.429608938 Feb 18 01:38:06 PM PST 24 Feb 18 01:39:02 PM PST 24 15202400 ps
T266 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2979686680 Feb 18 01:38:14 PM PST 24 Feb 18 01:39:19 PM PST 24 354857000 ps
T1076 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2974482074 Feb 18 01:38:33 PM PST 24 Feb 18 01:39:29 PM PST 24 39701900 ps
T321 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3929075669 Feb 18 01:39:12 PM PST 24 Feb 18 01:47:40 PM PST 24 700281300 ps
T1077 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3567221942 Feb 18 01:38:57 PM PST 24 Feb 18 01:39:47 PM PST 24 23672600 ps
T1078 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3920599427 Feb 18 01:38:04 PM PST 24 Feb 18 01:39:03 PM PST 24 19092600 ps
T1079 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1187645227 Feb 18 01:38:29 PM PST 24 Feb 18 01:39:23 PM PST 24 14113000 ps
T1080 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1578193457 Feb 18 01:38:46 PM PST 24 Feb 18 01:39:42 PM PST 24 38380200 ps
T1081 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2295340435 Feb 18 01:38:17 PM PST 24 Feb 18 01:39:14 PM PST 24 11627300 ps
T240 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1619464789 Feb 18 01:38:50 PM PST 24 Feb 18 01:39:54 PM PST 24 143295000 ps
T1082 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1061768926 Feb 18 01:38:07 PM PST 24 Feb 18 01:40:03 PM PST 24 4774153700 ps
T1083 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2779098047 Feb 18 01:38:53 PM PST 24 Feb 18 01:39:48 PM PST 24 29310100 ps
T267 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1896453115 Feb 18 01:38:11 PM PST 24 Feb 18 01:51:30 PM PST 24 812891600 ps
T1084 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1047480726 Feb 18 01:39:03 PM PST 24 Feb 18 01:39:58 PM PST 24 13778200 ps
T1085 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1824892800 Feb 18 01:38:40 PM PST 24 Feb 18 01:39:48 PM PST 24 1147507800 ps
T268 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3295297423 Feb 18 01:38:46 PM PST 24 Feb 18 01:39:42 PM PST 24 39729000 ps
T1086 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3272283059 Feb 18 01:37:47 PM PST 24 Feb 18 01:38:46 PM PST 24 32952700 ps
T269 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1035001689 Feb 18 01:38:29 PM PST 24 Feb 18 01:39:28 PM PST 24 99756500 ps
T218 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2348194236 Feb 18 01:37:56 PM PST 24 Feb 18 01:38:55 PM PST 24 19435500 ps
T1087 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.419478042 Feb 18 01:38:41 PM PST 24 Feb 18 01:39:55 PM PST 24 618762600 ps
T1088 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2680616637 Feb 18 01:38:03 PM PST 24 Feb 18 01:39:02 PM PST 24 31161300 ps
T1089 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3179061422 Feb 18 01:38:34 PM PST 24 Feb 18 01:39:33 PM PST 24 15044700 ps
T1090 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2641091022 Feb 18 01:39:09 PM PST 24 Feb 18 01:39:59 PM PST 24 14342400 ps
T1091 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1581438114 Feb 18 01:38:04 PM PST 24 Feb 18 01:39:18 PM PST 24 20674600 ps
T1092 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.90849045 Feb 18 01:38:46 PM PST 24 Feb 18 01:39:42 PM PST 24 14407800 ps
T322 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2714590778 Feb 18 01:37:50 PM PST 24 Feb 18 01:46:07 PM PST 24 178316000 ps
T270 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3866603031 Feb 18 01:38:34 PM PST 24 Feb 18 01:54:17 PM PST 24 1475489100 ps
T1093 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3354192739 Feb 18 01:38:48 PM PST 24 Feb 18 01:39:44 PM PST 24 44128500 ps
T1094 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3366318975 Feb 18 01:39:27 PM PST 24 Feb 18 01:40:27 PM PST 24 346082800 ps
T1095 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4165017242 Feb 18 01:38:10 PM PST 24 Feb 18 01:39:08 PM PST 24 85380900 ps
T1096 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2326000332 Feb 18 01:38:29 PM PST 24 Feb 18 01:39:25 PM PST 24 55477400 ps
T1097 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1251920199 Feb 18 01:38:11 PM PST 24 Feb 18 01:39:08 PM PST 24 25093700 ps
T317 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2183686892 Feb 18 01:39:11 PM PST 24 Feb 18 01:40:01 PM PST 24 56462800 ps
T324 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2158496160 Feb 18 01:38:06 PM PST 24 Feb 18 01:53:45 PM PST 24 342322300 ps
T1098 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1732383461 Feb 18 01:39:01 PM PST 24 Feb 18 01:39:57 PM PST 24 136872100 ps
T1099 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2672010725 Feb 18 01:38:12 PM PST 24 Feb 18 01:39:09 PM PST 24 59553100 ps
T1100 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3114276372 Feb 18 01:38:18 PM PST 24 Feb 18 01:39:13 PM PST 24 41521600 ps
T1101 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1518453123 Feb 18 01:37:52 PM PST 24 Feb 18 01:39:45 PM PST 24 4965711500 ps
T1102 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2972993866 Feb 18 01:38:33 PM PST 24 Feb 18 01:39:32 PM PST 24 12528400 ps
T1103 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2482335666 Feb 18 01:39:16 PM PST 24 Feb 18 01:40:06 PM PST 24 38037200 ps
T241 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3821820398 Feb 18 01:39:07 PM PST 24 Feb 18 01:40:12 PM PST 24 53552500 ps
T271 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3330091202 Feb 18 01:38:10 PM PST 24 Feb 18 01:54:05 PM PST 24 7825717000 ps
T1104 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2660320317 Feb 18 01:38:54 PM PST 24 Feb 18 01:39:50 PM PST 24 70143800 ps
T1105 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3922437861 Feb 18 01:39:21 PM PST 24 Feb 18 01:40:29 PM PST 24 17612400 ps
T1106 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3194245274 Feb 18 01:39:24 PM PST 24 Feb 18 01:40:15 PM PST 24 44249200 ps
T1107 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.4167139060 Feb 18 01:39:11 PM PST 24 Feb 18 01:40:02 PM PST 24 71025300 ps
T1108 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4120463632 Feb 18 01:38:37 PM PST 24 Feb 18 01:39:35 PM PST 24 37734700 ps
T1109 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.576067404 Feb 18 01:39:10 PM PST 24 Feb 18 01:40:06 PM PST 24 78175000 ps
T1110 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.681709601 Feb 18 01:38:33 PM PST 24 Feb 18 01:39:31 PM PST 24 21000300 ps
T1111 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4027838105 Feb 18 01:38:58 PM PST 24 Feb 18 01:40:02 PM PST 24 217820400 ps
T1112 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3928973079 Feb 18 01:38:24 PM PST 24 Feb 18 01:39:19 PM PST 24 15646900 ps
T1113 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1790716552 Feb 18 01:39:17 PM PST 24 Feb 18 01:40:08 PM PST 24 42435100 ps
T278 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2114362058 Feb 18 01:38:15 PM PST 24 Feb 18 01:39:14 PM PST 24 76604900 ps
T319 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1636178268 Feb 18 01:38:27 PM PST 24 Feb 18 01:39:30 PM PST 24 437181300 ps
T318 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.324072891 Feb 18 01:38:56 PM PST 24 Feb 18 01:39:52 PM PST 24 18942700 ps
T1114 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1238478657 Feb 18 01:39:26 PM PST 24 Feb 18 01:40:20 PM PST 24 40040200 ps
T1115 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.261935372 Feb 18 01:38:27 PM PST 24 Feb 18 01:39:27 PM PST 24 95517300 ps
T1116 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2524503927 Feb 18 01:38:10 PM PST 24 Feb 18 01:39:08 PM PST 24 30111300 ps
T1117 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2126553269 Feb 18 01:39:17 PM PST 24 Feb 18 01:40:15 PM PST 24 38448900 ps
T1118 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3294167134 Feb 18 01:39:10 PM PST 24 Feb 18 01:40:01 PM PST 24 12232000 ps
T1119 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3799905648 Feb 18 01:38:04 PM PST 24 Feb 18 01:39:18 PM PST 24 81841100 ps
T272 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1102543568 Feb 18 01:37:58 PM PST 24 Feb 18 01:39:13 PM PST 24 114071000 ps
T1120 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2937388149 Feb 18 01:38:57 PM PST 24 Feb 18 01:39:52 PM PST 24 147741100 ps
T1121 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1126375365 Feb 18 01:37:52 PM PST 24 Feb 18 01:38:55 PM PST 24 55191600 ps
T1122 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4000424308 Feb 18 01:39:16 PM PST 24 Feb 18 01:40:06 PM PST 24 52227900 ps
T239 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1151487089 Feb 18 01:38:41 PM PST 24 Feb 18 01:45:53 PM PST 24 185500800 ps
T1123 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1059579132 Feb 18 01:39:00 PM PST 24 Feb 18 01:39:56 PM PST 24 106023300 ps
T1124 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2926874876 Feb 18 01:39:23 PM PST 24 Feb 18 01:40:20 PM PST 24 274344300 ps
T273 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2568080246 Feb 18 01:37:53 PM PST 24 Feb 18 01:39:15 PM PST 24 1163593900 ps
T1125 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.742082613 Feb 18 01:38:06 PM PST 24 Feb 18 01:39:06 PM PST 24 94781100 ps
T323 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4261574848 Feb 18 01:38:49 PM PST 24 Feb 18 01:46:01 PM PST 24 706770000 ps
T1126 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1159212587 Feb 18 01:38:01 PM PST 24 Feb 18 01:39:36 PM PST 24 4976850900 ps
T1127 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3329745671 Feb 18 01:38:56 PM PST 24 Feb 18 01:39:52 PM PST 24 95606900 ps
T274 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1680296123 Feb 18 01:38:11 PM PST 24 Feb 18 01:39:37 PM PST 24 1818636200 ps
T1128 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4275902058 Feb 18 01:38:58 PM PST 24 Feb 18 01:39:53 PM PST 24 235928900 ps
T1129 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4050000043 Feb 18 01:37:55 PM PST 24 Feb 18 01:38:54 PM PST 24 27851700 ps
T1130 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2423463759 Feb 18 01:39:23 PM PST 24 Feb 18 01:40:35 PM PST 24 30814500 ps
T1131 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1892447239 Feb 18 01:38:04 PM PST 24 Feb 18 01:39:08 PM PST 24 134411700 ps
T1132 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3432418158 Feb 18 01:37:48 PM PST 24 Feb 18 01:38:47 PM PST 24 11336000 ps
T1133 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3952570635 Feb 18 01:38:36 PM PST 24 Feb 18 01:39:36 PM PST 24 151232800 ps
T1134 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1880698069 Feb 18 01:39:24 PM PST 24 Feb 18 01:40:16 PM PST 24 52886000 ps
T1135 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.482963085 Feb 18 01:38:35 PM PST 24 Feb 18 01:39:36 PM PST 24 86864600 ps
T1136 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2644282426 Feb 18 01:38:36 PM PST 24 Feb 18 01:39:31 PM PST 24 81498800 ps
T327 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.4101343642 Feb 18 01:38:49 PM PST 24 Feb 18 01:47:17 PM PST 24 338749600 ps
T1137 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4074407860 Feb 18 01:39:18 PM PST 24 Feb 18 01:40:12 PM PST 24 42195000 ps
T1138 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1358481689 Feb 18 01:39:18 PM PST 24 Feb 18 01:40:12 PM PST 24 36622000 ps
T1139 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.455496600 Feb 18 01:38:56 PM PST 24 Feb 18 01:39:52 PM PST 24 31905000 ps
T329 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3888262535 Feb 18 01:37:57 PM PST 24 Feb 18 01:46:41 PM PST 24 5212957300 ps
T1140 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.389263819 Feb 18 01:39:12 PM PST 24 Feb 18 01:40:09 PM PST 24 67607100 ps
T1141 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4117775433 Feb 18 01:39:17 PM PST 24 Feb 18 01:40:08 PM PST 24 58864300 ps
T1142 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2836132802 Feb 18 01:38:46 PM PST 24 Feb 18 01:39:48 PM PST 24 69856300 ps
T1143 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2826666451 Feb 18 01:38:35 PM PST 24 Feb 18 01:39:32 PM PST 24 112662100 ps
T1144 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2001418043 Feb 18 01:38:46 PM PST 24 Feb 18 01:39:49 PM PST 24 124192200 ps
T1145 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3732329017 Feb 18 01:37:48 PM PST 24 Feb 18 01:38:47 PM PST 24 12925100 ps
T219 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.495371004 Feb 18 01:38:10 PM PST 24 Feb 18 01:39:06 PM PST 24 43633700 ps
T1146 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3087985596 Feb 18 01:38:34 PM PST 24 Feb 18 01:39:35 PM PST 24 18393000 ps
T1147 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1154357597 Feb 18 01:38:09 PM PST 24 Feb 18 01:39:20 PM PST 24 141858500 ps
T1148 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1581916347 Feb 18 01:39:17 PM PST 24 Feb 18 01:40:08 PM PST 24 28390900 ps
T1149 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2803807322 Feb 18 01:38:36 PM PST 24 Feb 18 01:39:41 PM PST 24 21620300 ps
T275 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.612800317 Feb 18 01:39:10 PM PST 24 Feb 18 01:40:09 PM PST 24 199640600 ps
T331 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2932286883 Feb 18 01:37:51 PM PST 24 Feb 18 01:46:18 PM PST 24 168799200 ps
T325 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2728797854 Feb 18 01:38:43 PM PST 24 Feb 18 01:54:27 PM PST 24 3278405800 ps
T1150 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2078620029 Feb 18 01:37:57 PM PST 24 Feb 18 01:38:58 PM PST 24 22460900 ps
T1151 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1287916300 Feb 18 01:38:42 PM PST 24 Feb 18 01:39:38 PM PST 24 17843300 ps
T1152 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3388811794 Feb 18 01:38:00 PM PST 24 Feb 18 01:38:58 PM PST 24 63281200 ps
T1153 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3471107279 Feb 18 01:37:56 PM PST 24 Feb 18 01:38:57 PM PST 24 458598200 ps
T1154 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2631769336 Feb 18 01:38:49 PM PST 24 Feb 18 01:39:44 PM PST 24 402421100 ps
T1155 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3155817846 Feb 18 01:38:58 PM PST 24 Feb 18 01:39:51 PM PST 24 120125800 ps
T220 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2521535496 Feb 18 01:38:05 PM PST 24 Feb 18 01:39:01 PM PST 24 19955200 ps
T1156 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.844682217 Feb 18 01:38:35 PM PST 24 Feb 18 01:39:29 PM PST 24 17438800 ps
T221 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2567805302 Feb 18 01:37:58 PM PST 24 Feb 18 01:39:04 PM PST 24 58870100 ps
T328 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.4186403538 Feb 18 01:38:33 PM PST 24 Feb 18 01:54:27 PM PST 24 1374690900 ps
T1157 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1718880452 Feb 18 01:39:26 PM PST 24 Feb 18 01:40:23 PM PST 24 27768600 ps
T1158 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2825744175 Feb 18 01:39:09 PM PST 24 Feb 18 01:40:03 PM PST 24 13814800 ps
T1159 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1185392770 Feb 18 01:37:51 PM PST 24 Feb 18 01:39:15 PM PST 24 23840000 ps
T1160 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.661010903 Feb 18 01:38:33 PM PST 24 Feb 18 01:39:33 PM PST 24 61174800 ps
T276 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2191285128 Feb 18 01:38:33 PM PST 24 Feb 18 01:39:48 PM PST 24 394373300 ps
T1161 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2893023303 Feb 18 01:39:18 PM PST 24 Feb 18 01:40:13 PM PST 24 56629100 ps
T320 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3204488531 Feb 18 01:38:56 PM PST 24 Feb 18 01:52:16 PM PST 24 2886743900 ps
T1162 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1076082555 Feb 18 01:37:53 PM PST 24 Feb 18 01:38:57 PM PST 24 58292700 ps
T1163 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1308558394 Feb 18 01:38:12 PM PST 24 Feb 18 01:39:30 PM PST 24 827614600 ps
T1164 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4003080004 Feb 18 01:38:33 PM PST 24 Feb 18 01:39:34 PM PST 24 61123500 ps
T1165 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3499102644 Feb 18 01:39:19 PM PST 24 Feb 18 01:40:12 PM PST 24 15106500 ps
T1166 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3933014740 Feb 18 01:38:05 PM PST 24 Feb 18 01:39:02 PM PST 24 72857300 ps
T1167 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3869265821 Feb 18 01:38:04 PM PST 24 Feb 18 01:39:01 PM PST 24 16413300 ps
T1168 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.4073197425 Feb 18 01:38:57 PM PST 24 Feb 18 01:39:55 PM PST 24 43227300 ps
T1169 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.635518373 Feb 18 01:38:54 PM PST 24 Feb 18 01:39:47 PM PST 24 34265900 ps
T1170 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2712365753 Feb 18 01:37:56 PM PST 24 Feb 18 01:38:57 PM PST 24 20754200 ps
T1171 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.58507918 Feb 18 01:38:35 PM PST 24 Feb 18 01:39:30 PM PST 24 15113700 ps
T1172 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4114907672 Feb 18 01:38:13 PM PST 24 Feb 18 01:39:54 PM PST 24 130889400 ps
T326 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2123198311 Feb 18 01:38:37 PM PST 24 Feb 18 01:54:21 PM PST 24 815441400 ps
T1173 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2260134622 Feb 18 01:37:56 PM PST 24 Feb 18 01:38:57 PM PST 24 11737900 ps
T1174 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1287130491 Feb 18 01:37:52 PM PST 24 Feb 18 01:38:51 PM PST 24 15743800 ps
T1175 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2663197511 Feb 18 01:38:05 PM PST 24 Feb 18 01:39:01 PM PST 24 17918300 ps
T1176 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3567921137 Feb 18 01:38:10 PM PST 24 Feb 18 01:39:10 PM PST 24 160450100 ps
T1177 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.81084117 Feb 18 01:38:36 PM PST 24 Feb 18 01:39:36 PM PST 24 157436800 ps
T1178 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2756870251 Feb 18 01:37:50 PM PST 24 Feb 18 01:38:51 PM PST 24 14913200 ps
T1179 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3056677127 Feb 18 01:38:43 PM PST 24 Feb 18 01:39:37 PM PST 24 14538200 ps
T1180 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1691880530 Feb 18 01:39:01 PM PST 24 Feb 18 01:39:53 PM PST 24 15014600 ps
T1181 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2201334117 Feb 18 01:39:04 PM PST 24 Feb 18 01:40:04 PM PST 24 236211900 ps
T222 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1299750038 Feb 18 01:37:53 PM PST 24 Feb 18 01:38:52 PM PST 24 50988600 ps
T1182 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.953069858 Feb 18 01:37:58 PM PST 24 Feb 18 01:38:59 PM PST 24 27725500 ps
T332 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1057579656 Feb 18 01:38:58 PM PST 24 Feb 18 01:52:16 PM PST 24 888023500 ps
T1183 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.525519696 Feb 18 01:38:04 PM PST 24 Feb 18 01:39:24 PM PST 24 817933200 ps
T1184 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.872455840 Feb 18 01:38:32 PM PST 24 Feb 18 01:39:31 PM PST 24 47567000 ps
T1185 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.35480300 Feb 18 01:38:46 PM PST 24 Feb 18 01:39:48 PM PST 24 13350200 ps
T1186 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3574469394 Feb 18 01:38:25 PM PST 24 Feb 18 01:39:34 PM PST 24 28294300 ps
T1187 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4257286015 Feb 18 01:38:37 PM PST 24 Feb 18 01:39:34 PM PST 24 38717100 ps
T1188 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4060399676 Feb 18 01:39:17 PM PST 24 Feb 18 01:40:13 PM PST 24 17053700 ps
T277 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2303788351 Feb 18 01:38:59 PM PST 24 Feb 18 01:39:59 PM PST 24 106034700 ps
T330 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.361107692 Feb 18 01:38:55 PM PST 24 Feb 18 01:47:08 PM PST 24 184389100 ps
T1189 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.933141837 Feb 18 01:39:14 PM PST 24 Feb 18 01:40:04 PM PST 24 56030300 ps
T1190 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1409506178 Feb 18 01:39:04 PM PST 24 Feb 18 01:40:06 PM PST 24 162313900 ps
T1191 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2963159739 Feb 18 01:38:33 PM PST 24 Feb 18 01:39:38 PM PST 24 290040800 ps
T1192 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.260865113 Feb 18 01:38:56 PM PST 24 Feb 18 01:39:54 PM PST 24 58432600 ps
T1193 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2562108845 Feb 18 01:39:22 PM PST 24 Feb 18 01:40:33 PM PST 24 30580700 ps
T1194 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3792173005 Feb 18 01:39:02 PM PST 24 Feb 18 01:39:53 PM PST 24 32768200 ps
T1195 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2342342412 Feb 18 01:38:11 PM PST 24 Feb 18 01:39:59 PM PST 24 3260959000 ps
T1196 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1086367915 Feb 18 01:37:57 PM PST 24 Feb 18 01:39:00 PM PST 24 45168000 ps
T1197 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3351894434 Feb 18 01:38:54 PM PST 24 Feb 18 01:39:57 PM PST 24 140499600 ps
T1198 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1844945063 Feb 18 01:37:51 PM PST 24 Feb 18 01:39:39 PM PST 24 1265013300 ps
T1199 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1339669407 Feb 18 01:39:04 PM PST 24 Feb 18 01:39:58 PM PST 24 14017700 ps
T1200 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2092770985 Feb 18 01:38:36 PM PST 24 Feb 18 01:39:34 PM PST 24 983590400 ps
T1201 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4071915940 Feb 18 01:38:47 PM PST 24 Feb 18 01:39:44 PM PST 24 120022600 ps
T1202 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.209619238 Feb 18 01:38:25 PM PST 24 Feb 18 01:39:19 PM PST 24 11698100 ps
T1203 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3140370619 Feb 18 01:39:13 PM PST 24 Feb 18 01:40:04 PM PST 24 80305100 ps
T1204 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3827895738 Feb 18 01:38:59 PM PST 24 Feb 18 01:39:49 PM PST 24 43808500 ps

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.795025046
Short name T2
Test name
Test status
Simulation time 21449771900 ps
CPU time 332.19 seconds
Started Feb 18 02:45:40 PM PST 24
Finished Feb 18 02:51:14 PM PST 24
Peak memory 272716 kb
Host smart-5c30d5ea-a8e3-4f7a-8ed0-e643d1ca6313
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795025046 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_mp_regions.795025046
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.4178726937
Short name T22
Test name
Test status
Simulation time 3391275300 ps
CPU time 529.22 seconds
Started Feb 18 02:43:11 PM PST 24
Finished Feb 18 02:52:03 PM PST 24
Peak memory 327760 kb
Host smart-aa902351-af31-4eda-8570-db27ce690b81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178726937 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.4178726937
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.3878839513
Short name T13
Test name
Test status
Simulation time 40126882100 ps
CPU time 766.96 seconds
Started Feb 18 02:51:09 PM PST 24
Finished Feb 18 03:04:00 PM PST 24
Peak memory 258300 kb
Host smart-1025a89e-0738-4a37-9281-1087067d8978
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878839513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.3878839513
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2621604369
Short name T172
Test name
Test status
Simulation time 2852061700 ps
CPU time 762.59 seconds
Started Feb 18 01:38:52 PM PST 24
Finished Feb 18 01:52:11 PM PST 24
Peak memory 263508 kb
Host smart-8899bcd2-d945-4193-8971-5875f04d50cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621604369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.2621604369
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.4260145844
Short name T15
Test name
Test status
Simulation time 5121746600 ps
CPU time 4789.27 seconds
Started Feb 18 02:43:14 PM PST 24
Finished Feb 18 04:03:06 PM PST 24
Peak memory 286688 kb
Host smart-280fd4ba-cca3-4953-a60c-9134fb0beede
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260145844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.4260145844
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1166469334
Short name T215
Test name
Test status
Simulation time 234599800 ps
CPU time 24.71 seconds
Started Feb 18 01:38:35 PM PST 24
Finished Feb 18 01:39:41 PM PST 24
Peak memory 271548 kb
Host smart-b9c90e88-fd03-4f56-9c6d-82499d3ca495
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166469334 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1166469334
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.294775799
Short name T33
Test name
Test status
Simulation time 3502562500 ps
CPU time 98.79 seconds
Started Feb 18 02:53:11 PM PST 24
Finished Feb 18 02:54:53 PM PST 24
Peak memory 261404 kb
Host smart-4b0287e4-9dc3-413f-a75c-a85c348444dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294775799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_h
w_sec_otp.294775799
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.1674535471
Short name T51
Test name
Test status
Simulation time 53941913100 ps
CPU time 508.02 seconds
Started Feb 18 02:46:34 PM PST 24
Finished Feb 18 02:55:04 PM PST 24
Peak memory 261972 kb
Host smart-b4f4d689-1112-4d15-b0ed-a3b764955de6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674535471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1674535471
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.3210654758
Short name T50
Test name
Test status
Simulation time 1744733700 ps
CPU time 76.41 seconds
Started Feb 18 02:44:08 PM PST 24
Finished Feb 18 02:45:27 PM PST 24
Peak memory 259744 kb
Host smart-86c08019-cd35-402c-8e0d-ec5c492070dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210654758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3210654758
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.398887525
Short name T7
Test name
Test status
Simulation time 3822269500 ps
CPU time 170.37 seconds
Started Feb 18 02:54:19 PM PST 24
Finished Feb 18 02:57:12 PM PST 24
Peak memory 291504 kb
Host smart-2aa841cd-d09f-4f90-a095-72b451f96bd6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398887525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flas
h_ctrl_intr_rd.398887525
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.3884344916
Short name T88
Test name
Test status
Simulation time 162240200 ps
CPU time 130.27 seconds
Started Feb 18 02:53:49 PM PST 24
Finished Feb 18 02:56:02 PM PST 24
Peak memory 258948 kb
Host smart-7f2bbcb5-1b48-403a-86d8-d522482c1e6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884344916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.3884344916
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3542105178
Short name T97
Test name
Test status
Simulation time 10036183800 ps
CPU time 49.24 seconds
Started Feb 18 02:51:52 PM PST 24
Finished Feb 18 02:52:42 PM PST 24
Peak memory 269432 kb
Host smart-4d698eb7-c93a-4037-9f0d-23cb3531f4c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542105178 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3542105178
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1971706848
Short name T54
Test name
Test status
Simulation time 667997500 ps
CPU time 38.71 seconds
Started Feb 18 01:38:14 PM PST 24
Finished Feb 18 01:39:35 PM PST 24
Peak memory 261700 kb
Host smart-6e64e410-2f0d-40b0-bad9-fcebca27ec70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971706848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.1971706848
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.728740823
Short name T84
Test name
Test status
Simulation time 239361863600 ps
CPU time 2357.66 seconds
Started Feb 18 02:43:54 PM PST 24
Finished Feb 18 03:23:13 PM PST 24
Peak memory 264324 kb
Host smart-2a96ca72-6e3e-4352-a0fa-9d78d3cb719f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728740823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_host_ctrl_arb.728740823
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.4092018963
Short name T14
Test name
Test status
Simulation time 15505600 ps
CPU time 13.51 seconds
Started Feb 18 02:49:43 PM PST 24
Finished Feb 18 02:49:57 PM PST 24
Peak memory 264340 kb
Host smart-90806e17-4a37-4d3c-8435-d494e8b5baa5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092018963 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.4092018963
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.3407316773
Short name T64
Test name
Test status
Simulation time 38728700 ps
CPU time 113.12 seconds
Started Feb 18 02:52:44 PM PST 24
Finished Feb 18 02:54:42 PM PST 24
Peak memory 258456 kb
Host smart-5f3a9be9-0ded-45ff-9844-92851183bee4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407316773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.3407316773
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1893015758
Short name T308
Test name
Test status
Simulation time 50268700 ps
CPU time 13.38 seconds
Started Feb 18 01:39:18 PM PST 24
Finished Feb 18 01:40:12 PM PST 24
Peak memory 261704 kb
Host smart-805de7f4-1bc9-4626-aeaa-01fa5ec07ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893015758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
1893015758
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.1099702209
Short name T24
Test name
Test status
Simulation time 19532900200 ps
CPU time 420.35 seconds
Started Feb 18 02:48:50 PM PST 24
Finished Feb 18 02:55:51 PM PST 24
Peak memory 272568 kb
Host smart-0d94d8b8-c50e-4f0b-9a2d-09e2a908c9ea
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099702209 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.1099702209
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.4114353042
Short name T9
Test name
Test status
Simulation time 47236300 ps
CPU time 14.99 seconds
Started Feb 18 02:44:35 PM PST 24
Finished Feb 18 02:44:50 PM PST 24
Peak memory 264368 kb
Host smart-0b9b5ee8-23ce-4c82-923a-ade093b93085
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114353042 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.4114353042
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.1002936041
Short name T68
Test name
Test status
Simulation time 878110200 ps
CPU time 19.49 seconds
Started Feb 18 02:45:25 PM PST 24
Finished Feb 18 02:45:49 PM PST 24
Peak memory 264492 kb
Host smart-4ed83789-c145-423a-aee2-74ef77928554
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002936041 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.1002936041
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.3137337517
Short name T42
Test name
Test status
Simulation time 1410572500 ps
CPU time 27.22 seconds
Started Feb 18 02:47:52 PM PST 24
Finished Feb 18 02:48:21 PM PST 24
Peak memory 264360 kb
Host smart-33cbc7c9-af74-43bb-97b0-082c938b3de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137337517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.3137337517
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.772996569
Short name T93
Test name
Test status
Simulation time 101396445600 ps
CPU time 937.02 seconds
Started Feb 18 02:45:34 PM PST 24
Finished Feb 18 03:01:12 PM PST 24
Peak memory 312748 kb
Host smart-2037f2f2-42fa-420f-9a00-bb6ffd640a69
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772996569 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.772996569
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1896453115
Short name T267
Test name
Test status
Simulation time 812891600 ps
CPU time 754.53 seconds
Started Feb 18 01:38:11 PM PST 24
Finished Feb 18 01:51:30 PM PST 24
Peak memory 263488 kb
Host smart-65937864-c52a-410f-8f5c-f0e9cefa1ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896453115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.1896453115
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.4055454950
Short name T72
Test name
Test status
Simulation time 25529100 ps
CPU time 13.59 seconds
Started Feb 18 02:52:37 PM PST 24
Finished Feb 18 02:52:51 PM PST 24
Peak memory 263456 kb
Host smart-9b4b0cc5-99c4-49ac-82ba-28ec8e6c9b3c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055454950 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.4055454950
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.619668269
Short name T210
Test name
Test status
Simulation time 15463752900 ps
CPU time 98.43 seconds
Started Feb 18 02:54:19 PM PST 24
Finished Feb 18 02:55:59 PM PST 24
Peak memory 263824 kb
Host smart-a441b25b-ce5d-4cb5-8137-76f681f457a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619668269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.619668269
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.49029764
Short name T53
Test name
Test status
Simulation time 2675887300 ps
CPU time 72.58 seconds
Started Feb 18 02:42:55 PM PST 24
Finished Feb 18 02:44:08 PM PST 24
Peak memory 258808 kb
Host smart-0068ff3a-8054-4916-9b54-55c9e193ba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49029764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.49029764
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.4106450762
Short name T166
Test name
Test status
Simulation time 158229200 ps
CPU time 14.48 seconds
Started Feb 18 02:49:48 PM PST 24
Finished Feb 18 02:50:03 PM PST 24
Peak memory 263336 kb
Host smart-03591b08-ea50-422e-9a8d-9ad02868e5c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106450762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
4106450762
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3866942851
Short name T60
Test name
Test status
Simulation time 259990938700 ps
CPU time 624.57 seconds
Started Feb 18 02:48:49 PM PST 24
Finished Feb 18 02:59:15 PM PST 24
Peak memory 264384 kb
Host smart-0263d1c5-a164-4649-9307-fe06dd64771e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386
6942851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3866942851
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.3420663776
Short name T46
Test name
Test status
Simulation time 5569778100 ps
CPU time 461.17 seconds
Started Feb 18 02:47:27 PM PST 24
Finished Feb 18 02:55:09 PM PST 24
Peak memory 312644 kb
Host smart-caec1fa5-96c1-4962-99eb-c6e531c102b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420663776 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_rw_derr.3420663776
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.3455919755
Short name T30
Test name
Test status
Simulation time 5172899600 ps
CPU time 161.39 seconds
Started Feb 18 02:53:45 PM PST 24
Finished Feb 18 02:56:30 PM PST 24
Peak memory 292144 kb
Host smart-3710f6a8-90d6-4802-b65e-5544c5ae16a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455919755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.3455919755
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1299750038
Short name T222
Test name
Test status
Simulation time 50988600 ps
CPU time 13.59 seconds
Started Feb 18 01:37:53 PM PST 24
Finished Feb 18 01:38:52 PM PST 24
Peak memory 260208 kb
Host smart-f5a8401b-e176-4fff-8b8d-7e0b863b776b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299750038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.1299750038
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3154450058
Short name T309
Test name
Test status
Simulation time 30609500 ps
CPU time 13.49 seconds
Started Feb 18 01:39:15 PM PST 24
Finished Feb 18 01:40:18 PM PST 24
Peak memory 261752 kb
Host smart-8a47fcd6-4f6c-42e7-b1d5-ade1248e1a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154450058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
3154450058
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4019117617
Short name T211
Test name
Test status
Simulation time 63227400 ps
CPU time 19.81 seconds
Started Feb 18 01:38:35 PM PST 24
Finished Feb 18 01:39:36 PM PST 24
Peak memory 263404 kb
Host smart-522bb144-88e8-48c7-8fed-36ca3f584a50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019117617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.4
019117617
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1780805407
Short name T149
Test name
Test status
Simulation time 8763835800 ps
CPU time 74.76 seconds
Started Feb 18 02:42:55 PM PST 24
Finished Feb 18 02:44:12 PM PST 24
Peak memory 258776 kb
Host smart-744dc9f2-9fb5-483c-b235-5a3badbe0def
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780805407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1780805407
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.4104560481
Short name T112
Test name
Test status
Simulation time 21213100 ps
CPU time 22.33 seconds
Started Feb 18 02:54:53 PM PST 24
Finished Feb 18 02:55:18 PM PST 24
Peak memory 279792 kb
Host smart-5580f9b5-3f8f-4548-8266-caee495e2f28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104560481 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.4104560481
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.2999663000
Short name T31
Test name
Test status
Simulation time 2623457300 ps
CPU time 206.12 seconds
Started Feb 18 02:46:43 PM PST 24
Finished Feb 18 02:50:12 PM PST 24
Peak memory 280920 kb
Host smart-3051885a-1a85-4e57-a073-ee3818299665
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999663000 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.2999663000
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.1559627306
Short name T425
Test name
Test status
Simulation time 47379900 ps
CPU time 13.68 seconds
Started Feb 18 02:51:54 PM PST 24
Finished Feb 18 02:52:09 PM PST 24
Peak memory 264248 kb
Host smart-947ab9c2-0783-4bd1-934f-f4664a495a0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559627306 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.1559627306
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.778225894
Short name T158
Test name
Test status
Simulation time 15457700 ps
CPU time 14.22 seconds
Started Feb 18 02:45:33 PM PST 24
Finished Feb 18 02:45:49 PM PST 24
Peak memory 277032 kb
Host smart-a26b17fd-74ce-4aad-ad83-2efbc5ad6839
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=778225894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.778225894
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.4114138105
Short name T38
Test name
Test status
Simulation time 13891100 ps
CPU time 13.71 seconds
Started Feb 18 02:44:29 PM PST 24
Finished Feb 18 02:44:44 PM PST 24
Peak memory 264428 kb
Host smart-dc175884-0dbf-461f-b32f-c5a2ac54cd4f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114138105 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.4114138105
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.612800317
Short name T275
Test name
Test status
Simulation time 199640600 ps
CPU time 21.4 seconds
Started Feb 18 01:39:10 PM PST 24
Finished Feb 18 01:40:09 PM PST 24
Peak memory 271588 kb
Host smart-9d25dfb1-13a6-4cc6-8e83-5df4238395db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612800317 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.612800317
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.1129868901
Short name T298
Test name
Test status
Simulation time 528448400 ps
CPU time 41.7 seconds
Started Feb 18 02:51:59 PM PST 24
Finished Feb 18 02:52:42 PM PST 24
Peak memory 272744 kb
Host smart-c038289c-97f4-4e50-81a2-f5c061edc4bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129868901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.1129868901
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.1454703719
Short name T189
Test name
Test status
Simulation time 415442600 ps
CPU time 34.83 seconds
Started Feb 18 02:54:22 PM PST 24
Finished Feb 18 02:55:00 PM PST 24
Peak memory 265544 kb
Host smart-8834a108-1fd4-43a5-a74d-0eda8bee99e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454703719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.1454703719
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.3007164337
Short name T17
Test name
Test status
Simulation time 3221811300 ps
CPU time 4894.02 seconds
Started Feb 18 02:44:30 PM PST 24
Finished Feb 18 04:06:06 PM PST 24
Peak memory 287728 kb
Host smart-947b796f-aca1-4449-8f22-049afd89022c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007164337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3007164337
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.773005734
Short name T183
Test name
Test status
Simulation time 46216000 ps
CPU time 14.16 seconds
Started Feb 18 02:45:35 PM PST 24
Finished Feb 18 02:45:50 PM PST 24
Peak memory 263804 kb
Host smart-a556dd1d-6e00-42e5-868b-b2e3f2ee4a18
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773005734 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.773005734
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3403945908
Short name T295
Test name
Test status
Simulation time 30255000 ps
CPU time 30.95 seconds
Started Feb 18 02:53:41 PM PST 24
Finished Feb 18 02:54:16 PM PST 24
Peak memory 273732 kb
Host smart-ce3108db-6ac1-4205-88ec-01434543b9d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403945908 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3403945908
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.915949738
Short name T124
Test name
Test status
Simulation time 15382627400 ps
CPU time 630.25 seconds
Started Feb 18 02:43:10 PM PST 24
Finished Feb 18 02:53:42 PM PST 24
Peak memory 324400 kb
Host smart-5f7ddb5f-5b96-4ad3-a03e-1667e3aa1fb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915949738 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.flash_ctrl_integrity.915949738
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2191494028
Short name T216
Test name
Test status
Simulation time 3248330900 ps
CPU time 751.29 seconds
Started Feb 18 01:39:09 PM PST 24
Finished Feb 18 01:52:18 PM PST 24
Peak memory 263528 kb
Host smart-5f93a493-2f3a-4f89-9dec-4deffaec6f80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191494028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.2191494028
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4069300126
Short name T236
Test name
Test status
Simulation time 54968500 ps
CPU time 13.57 seconds
Started Feb 18 01:39:19 PM PST 24
Finished Feb 18 01:40:10 PM PST 24
Peak memory 261880 kb
Host smart-b547954f-cfad-4cf7-9d4c-247a0f748da2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069300126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
4069300126
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.1778096283
Short name T297
Test name
Test status
Simulation time 133441200 ps
CPU time 36.8 seconds
Started Feb 18 02:50:56 PM PST 24
Finished Feb 18 02:51:35 PM PST 24
Peak memory 265500 kb
Host smart-2c38cf3c-505c-4e85-b1c6-8d4a30cbbd34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778096283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.1778096283
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.4095451949
Short name T367
Test name
Test status
Simulation time 107191397300 ps
CPU time 265.09 seconds
Started Feb 18 02:54:18 PM PST 24
Finished Feb 18 02:58:44 PM PST 24
Peak memory 290012 kb
Host smart-588372d6-bc03-4a22-86c6-e98ab8c217d3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095451949 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.4095451949
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.1218247500
Short name T259
Test name
Test status
Simulation time 10033001500 ps
CPU time 101.69 seconds
Started Feb 18 02:50:10 PM PST 24
Finished Feb 18 02:52:00 PM PST 24
Peak memory 270864 kb
Host smart-12b5e0db-adcc-417b-8bdc-2b30a7a4dfe3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218247500 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.1218247500
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1400820236
Short name T256
Test name
Test status
Simulation time 15992300 ps
CPU time 13.32 seconds
Started Feb 18 02:52:23 PM PST 24
Finished Feb 18 02:52:38 PM PST 24
Peak memory 263552 kb
Host smart-e14f341e-625f-415c-b209-04332ae7e1cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400820236 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1400820236
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.3496644227
Short name T49
Test name
Test status
Simulation time 52800800 ps
CPU time 30.97 seconds
Started Feb 18 02:48:02 PM PST 24
Finished Feb 18 02:48:34 PM PST 24
Peak memory 273752 kb
Host smart-3749b47e-ec74-4365-919d-f6e2192d716c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496644227 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3496644227
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1246376471
Short name T588
Test name
Test status
Simulation time 10011785300 ps
CPU time 129.48 seconds
Started Feb 18 02:43:30 PM PST 24
Finished Feb 18 02:45:41 PM PST 24
Peak memory 318440 kb
Host smart-f4b7f0c9-207a-46ae-af3b-cbc71169ea39
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246376471 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1246376471
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.2260198929
Short name T305
Test name
Test status
Simulation time 47129700 ps
CPU time 13.74 seconds
Started Feb 18 02:49:49 PM PST 24
Finished Feb 18 02:50:05 PM PST 24
Peak memory 264188 kb
Host smart-0830667c-673e-4689-84d4-6779cf8b4f57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260198929 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.2260198929
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.4024055379
Short name T18
Test name
Test status
Simulation time 26431700 ps
CPU time 16.28 seconds
Started Feb 18 02:55:30 PM PST 24
Finished Feb 18 02:55:48 PM PST 24
Peak memory 273680 kb
Host smart-05e46897-69e5-42cc-9804-30a34938ca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024055379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.4024055379
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.2426215548
Short name T165
Test name
Test status
Simulation time 530539600 ps
CPU time 1729.89 seconds
Started Feb 18 02:42:56 PM PST 24
Finished Feb 18 03:11:48 PM PST 24
Peak memory 260576 kb
Host smart-27969f91-9d97-47c3-bde3-5b8e247b2c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426215548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.2426215548
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.2150455929
Short name T366
Test name
Test status
Simulation time 1553515800 ps
CPU time 178.63 seconds
Started Feb 18 02:46:46 PM PST 24
Finished Feb 18 02:49:47 PM PST 24
Peak memory 293164 kb
Host smart-a5049665-0d98-400a-a5b6-3fb3c0b9ff58
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150455929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.2150455929
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2551748707
Short name T238
Test name
Test status
Simulation time 83734500 ps
CPU time 19.26 seconds
Started Feb 18 01:39:00 PM PST 24
Finished Feb 18 01:39:56 PM PST 24
Peak memory 263424 kb
Host smart-d3c1ea28-d621-4787-b6b9-fb5ab082bd05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551748707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
2551748707
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2714590778
Short name T322
Test name
Test status
Simulation time 178316000 ps
CPU time 451.71 seconds
Started Feb 18 01:37:50 PM PST 24
Finished Feb 18 01:46:07 PM PST 24
Peak memory 263320 kb
Host smart-6c46d2ab-a3a6-4875-a863-4c4938725721
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714590778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.2714590778
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.1083223662
Short name T342
Test name
Test status
Simulation time 499404200 ps
CPU time 63.82 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 02:52:18 PM PST 24
Peak memory 262324 kb
Host smart-ffa8aa57-e81f-450a-95a6-dbe8ac571b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083223662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1083223662
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.1814851137
Short name T351
Test name
Test status
Simulation time 2470899000 ps
CPU time 68.24 seconds
Started Feb 18 02:52:00 PM PST 24
Finished Feb 18 02:53:09 PM PST 24
Peak memory 258676 kb
Host smart-9d39389b-94d6-4051-b1a6-9c29e1c42519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814851137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1814851137
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.3278283583
Short name T346
Test name
Test status
Simulation time 10398871200 ps
CPU time 73.32 seconds
Started Feb 18 02:52:37 PM PST 24
Finished Feb 18 02:53:51 PM PST 24
Peak memory 262320 kb
Host smart-74d3371b-1000-4b50-943e-103b2031c753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278283583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3278283583
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.1921012813
Short name T339
Test name
Test status
Simulation time 2138330400 ps
CPU time 56.95 seconds
Started Feb 18 02:47:04 PM PST 24
Finished Feb 18 02:48:06 PM PST 24
Peak memory 262324 kb
Host smart-aa2f6e85-7469-4d31-8db3-c8a5054fd17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921012813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1921012813
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1368730617
Short name T119
Test name
Test status
Simulation time 143255644300 ps
CPU time 1983.36 seconds
Started Feb 18 02:43:49 PM PST 24
Finished Feb 18 03:16:53 PM PST 24
Peak memory 258064 kb
Host smart-7a60a36e-55db-4ffe-a991-c019a66dd509
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368730617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1368730617
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.4219123664
Short name T746
Test name
Test status
Simulation time 240993000 ps
CPU time 92.72 seconds
Started Feb 18 02:44:49 PM PST 24
Finished Feb 18 02:46:27 PM PST 24
Peak memory 264300 kb
Host smart-8f12d895-f8cb-423d-ad94-4924e3e28a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219123664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.4219123664
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.1595833641
Short name T674
Test name
Test status
Simulation time 33150800 ps
CPU time 13.95 seconds
Started Feb 18 02:43:38 PM PST 24
Finished Feb 18 02:43:53 PM PST 24
Peak memory 264304 kb
Host smart-41430f80-da01-4fe1-9cc1-5420d2b43b8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595833641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.1595833641
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.2086766111
Short name T421
Test name
Test status
Simulation time 7109527500 ps
CPU time 607.29 seconds
Started Feb 18 02:46:45 PM PST 24
Finished Feb 18 02:56:55 PM PST 24
Peak memory 311276 kb
Host smart-d046528b-f647-4f56-afb7-66d56a788064
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086766111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.2086766111
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.2805203563
Short name T303
Test name
Test status
Simulation time 29609100 ps
CPU time 30.81 seconds
Started Feb 18 02:53:32 PM PST 24
Finished Feb 18 02:54:07 PM PST 24
Peak memory 271452 kb
Host smart-27c67c81-a25d-4797-b284-d5ed085fc3bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805203563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.2805203563
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.2564530031
Short name T340
Test name
Test status
Simulation time 1811635200 ps
CPU time 68.89 seconds
Started Feb 18 02:54:28 PM PST 24
Finished Feb 18 02:55:40 PM PST 24
Peak memory 258700 kb
Host smart-ebfb4eab-2e4f-4ec3-aecb-59fa3aa473e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564530031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2564530031
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.2801038540
Short name T179
Test name
Test status
Simulation time 12623991400 ps
CPU time 585.57 seconds
Started Feb 18 02:44:17 PM PST 24
Finished Feb 18 02:54:04 PM PST 24
Peak memory 326516 kb
Host smart-e9cfe4ac-a077-4210-a9c3-d391b8f7aefb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801038540 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_rw_derr.2801038540
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2932286883
Short name T331
Test name
Test status
Simulation time 168799200 ps
CPU time 460.9 seconds
Started Feb 18 01:37:51 PM PST 24
Finished Feb 18 01:46:18 PM PST 24
Peak memory 263400 kb
Host smart-2f33f533-366b-438e-90fe-2ddab217c18a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932286883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.2932286883
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2728797854
Short name T325
Test name
Test status
Simulation time 3278405800 ps
CPU time 903.77 seconds
Started Feb 18 01:38:43 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 262724 kb
Host smart-bd74c608-110d-4ccb-afca-fda4c1882d43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728797854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.2728797854
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4261574848
Short name T323
Test name
Test status
Simulation time 706770000 ps
CPU time 392.36 seconds
Started Feb 18 01:38:49 PM PST 24
Finished Feb 18 01:46:01 PM PST 24
Peak memory 263400 kb
Host smart-f5704002-b21f-4cb8-aad0-1e2a8fc52992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261574848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.4261574848
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.3680440310
Short name T362
Test name
Test status
Simulation time 6545031900 ps
CPU time 100.05 seconds
Started Feb 18 02:43:12 PM PST 24
Finished Feb 18 02:44:55 PM PST 24
Peak memory 264324 kb
Host smart-078bff4d-3bf9-429f-900d-3f1835b9ee73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680440310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.3680440310
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.4077557062
Short name T110
Test name
Test status
Simulation time 13841400 ps
CPU time 22.27 seconds
Started Feb 18 02:44:22 PM PST 24
Finished Feb 18 02:44:46 PM PST 24
Peak memory 279756 kb
Host smart-cce60124-f0e8-4ecb-9f5d-ff96aef625ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077557062 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.4077557062
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.2051037220
Short name T360
Test name
Test status
Simulation time 3831569200 ps
CPU time 97.09 seconds
Started Feb 18 02:44:02 PM PST 24
Finished Feb 18 02:45:40 PM PST 24
Peak memory 258916 kb
Host smart-d26494f8-e914-4653-8267-13f3d86d1941
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051037220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2051037220
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.1219863084
Short name T304
Test name
Test status
Simulation time 149884900 ps
CPU time 29.03 seconds
Started Feb 18 02:44:24 PM PST 24
Finished Feb 18 02:44:55 PM PST 24
Peak memory 273740 kb
Host smart-d6778c06-ee17-4487-9695-e53ec079db59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219863084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.1219863084
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.1086181992
Short name T516
Test name
Test status
Simulation time 40661800 ps
CPU time 31.88 seconds
Started Feb 18 02:49:49 PM PST 24
Finished Feb 18 02:50:23 PM PST 24
Peak memory 271580 kb
Host smart-841931a0-0113-4ff5-9ffb-592fa0b80a3c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086181992 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.1086181992
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.663656063
Short name T705
Test name
Test status
Simulation time 11517000 ps
CPU time 21.87 seconds
Started Feb 18 02:51:09 PM PST 24
Finished Feb 18 02:51:35 PM PST 24
Peak memory 272748 kb
Host smart-64973d0b-1ffa-4362-af25-6a3ca610d511
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663656063 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.663656063
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.3728367940
Short name T105
Test name
Test status
Simulation time 15968100 ps
CPU time 20.71 seconds
Started Feb 18 02:51:25 PM PST 24
Finished Feb 18 02:51:46 PM PST 24
Peak memory 264464 kb
Host smart-0489c72a-16ed-4b04-a963-da0a7576aea0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728367940 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.3728367940
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.2996253617
Short name T986
Test name
Test status
Simulation time 4577809300 ps
CPU time 155.09 seconds
Started Feb 18 02:51:20 PM PST 24
Finished Feb 18 02:53:56 PM PST 24
Peak memory 289144 kb
Host smart-2e4fca82-69b6-4756-8aec-17f0529fecfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996253617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.2996253617
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.4007573998
Short name T106
Test name
Test status
Simulation time 19811700 ps
CPU time 22.2 seconds
Started Feb 18 02:52:13 PM PST 24
Finished Feb 18 02:52:36 PM PST 24
Peak memory 279592 kb
Host smart-b49d9ac4-fb37-4c61-95b7-121343238324
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007573998 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.4007573998
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.3304220695
Short name T350
Test name
Test status
Simulation time 2785139800 ps
CPU time 70.42 seconds
Started Feb 18 02:53:56 PM PST 24
Finished Feb 18 02:55:08 PM PST 24
Peak memory 258732 kb
Host smart-3d2164e9-662c-488c-b7a5-e68e55758624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304220695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3304220695
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3350423830
Short name T296
Test name
Test status
Simulation time 29559700 ps
CPU time 31.9 seconds
Started Feb 18 02:48:51 PM PST 24
Finished Feb 18 02:49:24 PM PST 24
Peak memory 273784 kb
Host smart-08f455c3-a019-4ae9-801d-975315c168c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350423830 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3350423830
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.2375910121
Short name T625
Test name
Test status
Simulation time 25625400 ps
CPU time 13.56 seconds
Started Feb 18 02:43:28 PM PST 24
Finished Feb 18 02:43:44 PM PST 24
Peak memory 264328 kb
Host smart-6430db59-c307-47ce-910d-3f44e7b60391
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375910121 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.2375910121
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.2214651589
Short name T45
Test name
Test status
Simulation time 829155300 ps
CPU time 146.17 seconds
Started Feb 18 02:44:11 PM PST 24
Finished Feb 18 02:46:40 PM PST 24
Peak memory 280884 kb
Host smart-478f3f8d-165d-4898-bd5e-f42e06b95d22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2214651589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2214651589
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1666670189
Short name T197
Test name
Test status
Simulation time 18787300 ps
CPU time 13.89 seconds
Started Feb 18 02:44:34 PM PST 24
Finished Feb 18 02:44:49 PM PST 24
Peak memory 264616 kb
Host smart-f73734fd-6d27-4735-934c-8f30c0ad5029
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1666670189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1666670189
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1151487089
Short name T239
Test name
Test status
Simulation time 185500800 ps
CPU time 392.67 seconds
Started Feb 18 01:38:41 PM PST 24
Finished Feb 18 01:45:53 PM PST 24
Peak memory 263432 kb
Host smart-ae79106a-d929-42d2-b653-146ec3d969f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151487089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.1151487089
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.3462179613
Short name T36
Test name
Test status
Simulation time 114261200 ps
CPU time 13.65 seconds
Started Feb 18 02:43:28 PM PST 24
Finished Feb 18 02:43:44 PM PST 24
Peak memory 264444 kb
Host smart-f4d75b92-0786-400f-8154-8f419897a98b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462179613 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3462179613
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2186876193
Short name T26
Test name
Test status
Simulation time 4248229400 ps
CPU time 2181.08 seconds
Started Feb 18 02:42:52 PM PST 24
Finished Feb 18 03:19:14 PM PST 24
Peak memory 264316 kb
Host smart-9cbfba46-1c44-400a-b223-7b54efffbf9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186876193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2186876193
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.101814775
Short name T538
Test name
Test status
Simulation time 780970300 ps
CPU time 911.44 seconds
Started Feb 18 02:42:53 PM PST 24
Finished Feb 18 02:58:06 PM PST 24
Peak memory 272500 kb
Host smart-67901a42-9799-4861-8dd0-311576791df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101814775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.101814775
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2184375192
Short name T118
Test name
Test status
Simulation time 386371544100 ps
CPU time 2438.25 seconds
Started Feb 18 02:42:54 PM PST 24
Finished Feb 18 03:23:33 PM PST 24
Peak memory 264396 kb
Host smart-1bf713d5-f7b8-403f-a423-2a49018353e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184375192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.2184375192
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.3537067498
Short name T393
Test name
Test status
Simulation time 83671200 ps
CPU time 101.25 seconds
Started Feb 18 02:42:53 PM PST 24
Finished Feb 18 02:44:35 PM PST 24
Peak memory 264432 kb
Host smart-436eab05-a4a2-43e7-bd0b-c6f3afefcd2d
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3537067498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.3537067498
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.1208914288
Short name T402
Test name
Test status
Simulation time 62113200 ps
CPU time 23.1 seconds
Started Feb 18 02:43:13 PM PST 24
Finished Feb 18 02:43:40 PM PST 24
Peak memory 264456 kb
Host smart-d9e3e20b-4c6f-4a93-96a5-6b38fa2f93e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208914288 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.1208914288
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3045000837
Short name T181
Test name
Test status
Simulation time 29989200 ps
CPU time 13.92 seconds
Started Feb 18 02:44:34 PM PST 24
Finished Feb 18 02:44:49 PM PST 24
Peak memory 264592 kb
Host smart-a31ec6f2-46fe-4c26-8bd5-d55343bd3c81
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045000837 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3045000837
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.3977892253
Short name T37
Test name
Test status
Simulation time 13747600 ps
CPU time 13.44 seconds
Started Feb 18 02:45:25 PM PST 24
Finished Feb 18 02:45:42 PM PST 24
Peak memory 264504 kb
Host smart-d2b78d05-238b-4dba-a410-ccfd23f5b8e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977892253 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3977892253
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.3827184926
Short name T11
Test name
Test status
Simulation time 400532700 ps
CPU time 15.02 seconds
Started Feb 18 02:45:25 PM PST 24
Finished Feb 18 02:45:45 PM PST 24
Peak memory 264388 kb
Host smart-a6d1f682-9182-4590-9938-3ead367dfee8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827184926 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.3827184926
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.3447769242
Short name T91
Test name
Test status
Simulation time 1060801933300 ps
CPU time 2011.56 seconds
Started Feb 18 02:46:34 PM PST 24
Finished Feb 18 03:20:08 PM PST 24
Peak memory 264364 kb
Host smart-849e6acc-3e58-40b8-9227-e1160397c870
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447769242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.3447769242
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1518453123
Short name T1101
Test name
Test status
Simulation time 4965711500 ps
CPU time 68.37 seconds
Started Feb 18 01:37:52 PM PST 24
Finished Feb 18 01:39:45 PM PST 24
Peak memory 259428 kb
Host smart-ed4db654-38ec-48ec-ba10-f8ace1db853c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518453123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.1518453123
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1844945063
Short name T1198
Test name
Test status
Simulation time 1265013300 ps
CPU time 62.8 seconds
Started Feb 18 01:37:51 PM PST 24
Finished Feb 18 01:39:39 PM PST 24
Peak memory 259500 kb
Host smart-c1986041-d424-49d9-9a9b-cb01e2393fc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844945063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.1844945063
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1185392770
Short name T1159
Test name
Test status
Simulation time 23840000 ps
CPU time 38.51 seconds
Started Feb 18 01:37:51 PM PST 24
Finished Feb 18 01:39:15 PM PST 24
Peak memory 259588 kb
Host smart-ae060011-a6b4-4a5d-b70a-ce47196ee149
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185392770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1185392770
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1086367915
Short name T1196
Test name
Test status
Simulation time 45168000 ps
CPU time 17.28 seconds
Started Feb 18 01:37:57 PM PST 24
Finished Feb 18 01:39:00 PM PST 24
Peak memory 276552 kb
Host smart-25210aad-6f97-4a24-8d4c-d4de3a82b947
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086367915 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1086367915
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1126375365
Short name T1121
Test name
Test status
Simulation time 55191600 ps
CPU time 17.75 seconds
Started Feb 18 01:37:52 PM PST 24
Finished Feb 18 01:38:55 PM PST 24
Peak memory 259668 kb
Host smart-25cf62d0-b6ab-40a4-81c7-02af5e811a2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126375365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.1126375365
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3272283059
Short name T1086
Test name
Test status
Simulation time 32952700 ps
CPU time 13.57 seconds
Started Feb 18 01:37:47 PM PST 24
Finished Feb 18 01:38:46 PM PST 24
Peak memory 261700 kb
Host smart-54deea7f-4de9-4c8e-af91-bde9f12a0fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272283059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3
272283059
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1287130491
Short name T1174
Test name
Test status
Simulation time 15743800 ps
CPU time 13.41 seconds
Started Feb 18 01:37:52 PM PST 24
Finished Feb 18 01:38:51 PM PST 24
Peak memory 260788 kb
Host smart-de9729e5-60dc-4b10-931a-31bf601d2a9e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287130491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.1287130491
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2568080246
Short name T273
Test name
Test status
Simulation time 1163593900 ps
CPU time 35.97 seconds
Started Feb 18 01:37:53 PM PST 24
Finished Feb 18 01:39:15 PM PST 24
Peak memory 259692 kb
Host smart-e3015fe6-ac2f-4fd6-8a46-845566c1eafe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568080246 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.2568080246
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3432418158
Short name T1132
Test name
Test status
Simulation time 11336000 ps
CPU time 13.14 seconds
Started Feb 18 01:37:48 PM PST 24
Finished Feb 18 01:38:47 PM PST 24
Peak memory 259500 kb
Host smart-8bbf1fd3-31e1-4352-ae5e-63640e67940b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432418158 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.3432418158
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3732329017
Short name T1145
Test name
Test status
Simulation time 12925100 ps
CPU time 12.96 seconds
Started Feb 18 01:37:48 PM PST 24
Finished Feb 18 01:38:47 PM PST 24
Peak memory 259516 kb
Host smart-5bdf14fb-59a9-44d5-8ae7-41087809ed27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732329017 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.3732329017
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2799340890
Short name T169
Test name
Test status
Simulation time 119111700 ps
CPU time 15.86 seconds
Started Feb 18 01:37:47 PM PST 24
Finished Feb 18 01:38:48 PM PST 24
Peak memory 263424 kb
Host smart-15763d71-071b-44a7-a498-7c857c54add6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799340890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2
799340890
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3905838632
Short name T205
Test name
Test status
Simulation time 237598500 ps
CPU time 34.08 seconds
Started Feb 18 01:38:00 PM PST 24
Finished Feb 18 01:39:19 PM PST 24
Peak memory 259496 kb
Host smart-c0af9883-f98e-4cd1-a719-f54061b68165
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905838632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.3905838632
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1159212587
Short name T1126
Test name
Test status
Simulation time 4976850900 ps
CPU time 50.96 seconds
Started Feb 18 01:38:01 PM PST 24
Finished Feb 18 01:39:36 PM PST 24
Peak memory 259560 kb
Host smart-2e7b1c95-1a67-414f-b2bb-6e040ca1ab6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159212587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1159212587
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1102543568
Short name T272
Test name
Test status
Simulation time 114071000 ps
CPU time 30.07 seconds
Started Feb 18 01:37:58 PM PST 24
Finished Feb 18 01:39:13 PM PST 24
Peak memory 259588 kb
Host smart-05482c65-4c27-449f-bb08-5fc1dd331542
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102543568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.1102543568
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1892447239
Short name T1131
Test name
Test status
Simulation time 134411700 ps
CPU time 19.53 seconds
Started Feb 18 01:38:04 PM PST 24
Finished Feb 18 01:39:08 PM PST 24
Peak memory 271100 kb
Host smart-81e20f9d-bb5e-4297-b662-43a5ec78f9ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892447239 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.1892447239
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3471107279
Short name T1153
Test name
Test status
Simulation time 458598200 ps
CPU time 15.33 seconds
Started Feb 18 01:37:56 PM PST 24
Finished Feb 18 01:38:57 PM PST 24
Peak memory 259588 kb
Host smart-a31168ee-cced-4404-9cf0-e6341fbbb132
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471107279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.3471107279
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3388811794
Short name T1152
Test name
Test status
Simulation time 63281200 ps
CPU time 13.61 seconds
Started Feb 18 01:38:00 PM PST 24
Finished Feb 18 01:38:58 PM PST 24
Peak memory 261584 kb
Host smart-6d116c69-1006-4d05-a716-4189a99b80aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388811794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3
388811794
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2567805302
Short name T221
Test name
Test status
Simulation time 58870100 ps
CPU time 13.38 seconds
Started Feb 18 01:37:58 PM PST 24
Finished Feb 18 01:39:04 PM PST 24
Peak memory 263228 kb
Host smart-2873010d-dcad-4e8d-a7f2-07f13b2ae574
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567805302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.2567805302
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4050000043
Short name T1129
Test name
Test status
Simulation time 27851700 ps
CPU time 13.4 seconds
Started Feb 18 01:37:55 PM PST 24
Finished Feb 18 01:38:54 PM PST 24
Peak memory 261748 kb
Host smart-bc35e2e3-5263-48c4-8659-544586b44612
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050000043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.4050000043
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.99928677
Short name T55
Test name
Test status
Simulation time 34052800 ps
CPU time 15.23 seconds
Started Feb 18 01:37:59 PM PST 24
Finished Feb 18 01:38:58 PM PST 24
Peak memory 261520 kb
Host smart-980194ee-592f-455b-b731-f1e1f82e13fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99928677 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.99928677
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2756870251
Short name T1178
Test name
Test status
Simulation time 14913200 ps
CPU time 15.61 seconds
Started Feb 18 01:37:50 PM PST 24
Finished Feb 18 01:38:51 PM PST 24
Peak memory 259464 kb
Host smart-8aa8f724-c211-444a-8a6a-b10260c73675
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756870251 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2756870251
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2712365753
Short name T1170
Test name
Test status
Simulation time 20754200 ps
CPU time 15.8 seconds
Started Feb 18 01:37:56 PM PST 24
Finished Feb 18 01:38:57 PM PST 24
Peak memory 259556 kb
Host smart-7527039d-b594-4ec0-993e-2e414ee9e7fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712365753 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.2712365753
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1076082555
Short name T1162
Test name
Test status
Simulation time 58292700 ps
CPU time 19.11 seconds
Started Feb 18 01:37:53 PM PST 24
Finished Feb 18 01:38:57 PM PST 24
Peak memory 263396 kb
Host smart-ac054c73-2bd1-47a7-b508-35202c46d2af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076082555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.1
076082555
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3952570635
Short name T1133
Test name
Test status
Simulation time 151232800 ps
CPU time 19.33 seconds
Started Feb 18 01:38:36 PM PST 24
Finished Feb 18 01:39:36 PM PST 24
Peak memory 278544 kb
Host smart-d05f46a3-9972-400d-962c-66746a64b416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952570635 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3952570635
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2826666451
Short name T1143
Test name
Test status
Simulation time 112662100 ps
CPU time 16.47 seconds
Started Feb 18 01:38:35 PM PST 24
Finished Feb 18 01:39:32 PM PST 24
Peak memory 259700 kb
Host smart-39a5d01d-c3ed-46d2-98e8-9b2c450c4f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826666451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2826666451
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2644282426
Short name T1136
Test name
Test status
Simulation time 81498800 ps
CPU time 13.36 seconds
Started Feb 18 01:38:36 PM PST 24
Finished Feb 18 01:39:31 PM PST 24
Peak memory 261844 kb
Host smart-690a5a28-32fd-4d45-bd8c-bc6d176bce3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644282426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
2644282426
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2092770985
Short name T1200
Test name
Test status
Simulation time 983590400 ps
CPU time 15.57 seconds
Started Feb 18 01:38:36 PM PST 24
Finished Feb 18 01:39:34 PM PST 24
Peak memory 259668 kb
Host smart-6d797ca9-c4af-4002-9493-0b76a54e30a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092770985 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.2092770985
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.533350173
Short name T1071
Test name
Test status
Simulation time 14985100 ps
CPU time 13.1 seconds
Started Feb 18 01:38:36 PM PST 24
Finished Feb 18 01:39:30 PM PST 24
Peak memory 259524 kb
Host smart-14f327da-f7f8-4901-a3ad-ec07cc7cf918
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533350173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.533350173
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2972993866
Short name T1102
Test name
Test status
Simulation time 12528400 ps
CPU time 15.89 seconds
Started Feb 18 01:38:33 PM PST 24
Finished Feb 18 01:39:32 PM PST 24
Peak memory 259448 kb
Host smart-f3fc8a4c-53b4-486c-8f1f-936d08ac8263
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972993866 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.2972993866
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.482963085
Short name T1135
Test name
Test status
Simulation time 86864600 ps
CPU time 19.48 seconds
Started Feb 18 01:38:35 PM PST 24
Finished Feb 18 01:39:36 PM PST 24
Peak memory 263436 kb
Host smart-9b111a4e-972f-4b29-add1-1e1d2310e0ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482963085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.482963085
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1824892800
Short name T1085
Test name
Test status
Simulation time 1147507800 ps
CPU time 24.13 seconds
Started Feb 18 01:38:40 PM PST 24
Finished Feb 18 01:39:48 PM PST 24
Peak memory 270664 kb
Host smart-c37f65c7-9576-4fc0-94dd-419bfaba9541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824892800 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1824892800
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.635518373
Short name T1169
Test name
Test status
Simulation time 34265900 ps
CPU time 16.03 seconds
Started Feb 18 01:38:54 PM PST 24
Finished Feb 18 01:39:47 PM PST 24
Peak memory 259600 kb
Host smart-99e72e98-e4ee-4f83-a696-b6badc3860e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635518373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_csr_rw.635518373
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1516607782
Short name T316
Test name
Test status
Simulation time 56830300 ps
CPU time 13.22 seconds
Started Feb 18 01:38:42 PM PST 24
Finished Feb 18 01:39:35 PM PST 24
Peak memory 261912 kb
Host smart-831d2b07-e8ae-4936-bdfd-546eee5dc3ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516607782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
1516607782
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2619237010
Short name T200
Test name
Test status
Simulation time 496030400 ps
CPU time 19.43 seconds
Started Feb 18 01:38:39 PM PST 24
Finished Feb 18 01:39:40 PM PST 24
Peak memory 259576 kb
Host smart-609a380e-adc8-4035-8c31-6ab24fa1ffa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619237010 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.2619237010
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3056677127
Short name T1179
Test name
Test status
Simulation time 14538200 ps
CPU time 15.4 seconds
Started Feb 18 01:38:43 PM PST 24
Finished Feb 18 01:39:37 PM PST 24
Peak memory 259524 kb
Host smart-37df73b7-98b9-404a-9151-6e277599b500
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056677127 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.3056677127
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1287916300
Short name T1151
Test name
Test status
Simulation time 17843300 ps
CPU time 15.72 seconds
Started Feb 18 01:38:42 PM PST 24
Finished Feb 18 01:39:38 PM PST 24
Peak memory 259540 kb
Host smart-b4c3dedd-bf87-4378-bc2c-4056d970fd54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287916300 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.1287916300
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4003080004
Short name T1164
Test name
Test status
Simulation time 61123500 ps
CPU time 18.34 seconds
Started Feb 18 01:38:33 PM PST 24
Finished Feb 18 01:39:34 PM PST 24
Peak memory 263440 kb
Host smart-1b559727-acb4-4335-8e63-7f9b888ded2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003080004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
4003080004
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1619464789
Short name T240
Test name
Test status
Simulation time 143295000 ps
CPU time 24.18 seconds
Started Feb 18 01:38:50 PM PST 24
Finished Feb 18 01:39:54 PM PST 24
Peak memory 277764 kb
Host smart-8496743a-ac1c-4c5b-afcb-6e4eb9ab857d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619464789 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1619464789
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3295297423
Short name T268
Test name
Test status
Simulation time 39729000 ps
CPU time 14.56 seconds
Started Feb 18 01:38:46 PM PST 24
Finished Feb 18 01:39:42 PM PST 24
Peak memory 259616 kb
Host smart-4be544a4-f2c5-4231-b679-4bafd706ebb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295297423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.3295297423
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2836132802
Short name T1142
Test name
Test status
Simulation time 69856300 ps
CPU time 13.48 seconds
Started Feb 18 01:38:46 PM PST 24
Finished Feb 18 01:39:48 PM PST 24
Peak memory 261620 kb
Host smart-8b7d5f6c-1eae-48d3-a3c4-c3a3a64dd549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836132802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
2836132802
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2631769336
Short name T1154
Test name
Test status
Simulation time 402421100 ps
CPU time 17.54 seconds
Started Feb 18 01:38:49 PM PST 24
Finished Feb 18 01:39:44 PM PST 24
Peak memory 259584 kb
Host smart-eb394dbf-3c65-4842-8912-faba0469941d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631769336 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.2631769336
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3916886340
Short name T1070
Test name
Test status
Simulation time 17391100 ps
CPU time 13.05 seconds
Started Feb 18 01:38:49 PM PST 24
Finished Feb 18 01:39:42 PM PST 24
Peak memory 259532 kb
Host smart-81027cf9-c39d-4b64-942a-43e04dba897b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916886340 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3916886340
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1578193457
Short name T1080
Test name
Test status
Simulation time 38380200 ps
CPU time 15.79 seconds
Started Feb 18 01:38:46 PM PST 24
Finished Feb 18 01:39:42 PM PST 24
Peak memory 259628 kb
Host smart-89f7b6bd-8c2e-452b-9f97-3dd18f7d9049
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578193457 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.1578193457
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2002640053
Short name T212
Test name
Test status
Simulation time 52924800 ps
CPU time 19.43 seconds
Started Feb 18 01:38:49 PM PST 24
Finished Feb 18 01:39:48 PM PST 24
Peak memory 263424 kb
Host smart-3e5699ca-63b2-407e-985e-1b34206c07fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002640053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
2002640053
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3204488531
Short name T320
Test name
Test status
Simulation time 2886743900 ps
CPU time 762.26 seconds
Started Feb 18 01:38:56 PM PST 24
Finished Feb 18 01:52:16 PM PST 24
Peak memory 263440 kb
Host smart-2fa9805b-cebd-4453-84e7-c4a2f11b5a45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204488531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.3204488531
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2001418043
Short name T1144
Test name
Test status
Simulation time 124192200 ps
CPU time 23.57 seconds
Started Feb 18 01:38:46 PM PST 24
Finished Feb 18 01:39:49 PM PST 24
Peak memory 270832 kb
Host smart-6420a375-135a-4949-b0d0-3fdfa3a31b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001418043 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2001418043
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2779098047
Short name T1083
Test name
Test status
Simulation time 29310100 ps
CPU time 17.11 seconds
Started Feb 18 01:38:53 PM PST 24
Finished Feb 18 01:39:48 PM PST 24
Peak memory 259600 kb
Host smart-f12630ec-e048-4480-bc88-887fc7fce122
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779098047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.2779098047
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.324072891
Short name T318
Test name
Test status
Simulation time 18942700 ps
CPU time 13.33 seconds
Started Feb 18 01:38:56 PM PST 24
Finished Feb 18 01:39:52 PM PST 24
Peak memory 261652 kb
Host smart-fd87e5f3-138c-4c5b-93c3-d9f16eb4d5d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324072891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.324072891
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4227993262
Short name T265
Test name
Test status
Simulation time 735483800 ps
CPU time 34.59 seconds
Started Feb 18 01:38:52 PM PST 24
Finished Feb 18 01:40:14 PM PST 24
Peak memory 259672 kb
Host smart-902309c5-a8ee-481a-88f3-4bc98debbdfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227993262 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.4227993262
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.35480300
Short name T1185
Test name
Test status
Simulation time 13350200 ps
CPU time 15.75 seconds
Started Feb 18 01:38:46 PM PST 24
Finished Feb 18 01:39:48 PM PST 24
Peak memory 259556 kb
Host smart-54820d19-717d-4997-afec-02634f2e7e22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35480300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.35480300
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3354192739
Short name T1093
Test name
Test status
Simulation time 44128500 ps
CPU time 15.56 seconds
Started Feb 18 01:38:48 PM PST 24
Finished Feb 18 01:39:44 PM PST 24
Peak memory 259528 kb
Host smart-fd989a5c-1731-4874-af4d-2865b0dbf613
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354192739 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.3354192739
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.260865113
Short name T1192
Test name
Test status
Simulation time 58432600 ps
CPU time 15.41 seconds
Started Feb 18 01:38:56 PM PST 24
Finished Feb 18 01:39:54 PM PST 24
Peak memory 263428 kb
Host smart-03155622-dbf7-400d-9f25-0add4337b1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260865113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.260865113
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.4101343642
Short name T327
Test name
Test status
Simulation time 338749600 ps
CPU time 468.71 seconds
Started Feb 18 01:38:49 PM PST 24
Finished Feb 18 01:47:17 PM PST 24
Peak memory 263396 kb
Host smart-5fea8b12-f942-430d-bd3a-4a8f55fe35a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101343642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.4101343642
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2937388149
Short name T1120
Test name
Test status
Simulation time 147741100 ps
CPU time 19.41 seconds
Started Feb 18 01:38:57 PM PST 24
Finished Feb 18 01:39:52 PM PST 24
Peak memory 271652 kb
Host smart-348abaeb-e83f-45ff-b772-4ada51f6c1f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937388149 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2937388149
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3485609717
Short name T261
Test name
Test status
Simulation time 51107400 ps
CPU time 16.63 seconds
Started Feb 18 01:38:56 PM PST 24
Finished Feb 18 01:39:56 PM PST 24
Peak memory 259528 kb
Host smart-efaa71eb-05a7-4c82-a1ce-3e32fef9c4bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485609717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.3485609717
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.455496600
Short name T1139
Test name
Test status
Simulation time 31905000 ps
CPU time 13.22 seconds
Started Feb 18 01:38:56 PM PST 24
Finished Feb 18 01:39:52 PM PST 24
Peak memory 261772 kb
Host smart-b0bfda65-e934-439c-afa2-36f6ad2d626b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455496600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.455496600
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4275902058
Short name T1128
Test name
Test status
Simulation time 235928900 ps
CPU time 18.18 seconds
Started Feb 18 01:38:58 PM PST 24
Finished Feb 18 01:39:53 PM PST 24
Peak memory 262800 kb
Host smart-d461280b-3058-4133-bae4-7ee9d1c47ece
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275902058 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.4275902058
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.90849045
Short name T1092
Test name
Test status
Simulation time 14407800 ps
CPU time 15.77 seconds
Started Feb 18 01:38:46 PM PST 24
Finished Feb 18 01:39:42 PM PST 24
Peak memory 259520 kb
Host smart-2e87a89d-ef39-4893-be80-bc0849741076
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90849045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.90849045
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3329745671
Short name T1127
Test name
Test status
Simulation time 95606900 ps
CPU time 13.24 seconds
Started Feb 18 01:38:56 PM PST 24
Finished Feb 18 01:39:52 PM PST 24
Peak memory 259480 kb
Host smart-befa3bf3-cc3e-4e40-9ce2-cbe11eee2457
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329745671 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.3329745671
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4071915940
Short name T1201
Test name
Test status
Simulation time 120022600 ps
CPU time 16.11 seconds
Started Feb 18 01:38:47 PM PST 24
Finished Feb 18 01:39:44 PM PST 24
Peak memory 263424 kb
Host smart-4017fcb3-cffd-43c8-9744-051ff2e540f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071915940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
4071915940
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4083468332
Short name T213
Test name
Test status
Simulation time 344410100 ps
CPU time 21.23 seconds
Started Feb 18 01:38:54 PM PST 24
Finished Feb 18 01:39:51 PM PST 24
Peak memory 271664 kb
Host smart-b667de55-539e-4d78-a698-0a3fba69250c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083468332 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.4083468332
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2660320317
Short name T1104
Test name
Test status
Simulation time 70143800 ps
CPU time 16.72 seconds
Started Feb 18 01:38:54 PM PST 24
Finished Feb 18 01:39:50 PM PST 24
Peak memory 259596 kb
Host smart-1815780a-64c0-4a6a-9aba-7aaaec30da98
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660320317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.2660320317
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1732383461
Short name T1098
Test name
Test status
Simulation time 136872100 ps
CPU time 13.53 seconds
Started Feb 18 01:39:01 PM PST 24
Finished Feb 18 01:39:57 PM PST 24
Peak memory 260120 kb
Host smart-9b4e171c-49c3-4802-afdd-bb56d68c0f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732383461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
1732383461
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1409506178
Short name T1190
Test name
Test status
Simulation time 162313900 ps
CPU time 19.65 seconds
Started Feb 18 01:39:04 PM PST 24
Finished Feb 18 01:40:06 PM PST 24
Peak memory 259592 kb
Host smart-e43d7032-eb83-4f17-93f1-605535e4a6da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409506178 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.1409506178
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.872346758
Short name T1074
Test name
Test status
Simulation time 20764100 ps
CPU time 15.82 seconds
Started Feb 18 01:38:58 PM PST 24
Finished Feb 18 01:39:56 PM PST 24
Peak memory 259512 kb
Host smart-048dc4ed-6950-484a-9492-2f0fa5dd3638
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872346758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.872346758
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3751982202
Short name T1068
Test name
Test status
Simulation time 33509300 ps
CPU time 15.65 seconds
Started Feb 18 01:38:58 PM PST 24
Finished Feb 18 01:39:51 PM PST 24
Peak memory 259472 kb
Host smart-64112535-e900-4741-b2f6-9d046ffce815
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751982202 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3751982202
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1059579132
Short name T1123
Test name
Test status
Simulation time 106023300 ps
CPU time 18.92 seconds
Started Feb 18 01:39:00 PM PST 24
Finished Feb 18 01:39:56 PM PST 24
Peak memory 263468 kb
Host smart-07a17c32-9dfe-434f-9a5f-21bd7157e7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059579132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1059579132
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1057579656
Short name T332
Test name
Test status
Simulation time 888023500 ps
CPU time 761.53 seconds
Started Feb 18 01:38:58 PM PST 24
Finished Feb 18 01:52:16 PM PST 24
Peak memory 263460 kb
Host smart-173eded6-c6e2-4949-8402-0282a8684860
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057579656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.1057579656
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4027838105
Short name T1111
Test name
Test status
Simulation time 217820400 ps
CPU time 25.18 seconds
Started Feb 18 01:38:58 PM PST 24
Finished Feb 18 01:40:02 PM PST 24
Peak memory 271616 kb
Host smart-bb3fd844-5327-473b-8bf9-ef01321250c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027838105 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.4027838105
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3351894434
Short name T1197
Test name
Test status
Simulation time 140499600 ps
CPU time 14.79 seconds
Started Feb 18 01:38:54 PM PST 24
Finished Feb 18 01:39:57 PM PST 24
Peak memory 259508 kb
Host smart-1194e09f-21ee-4407-a3fe-41120efb70be
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351894434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.3351894434
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3567221942
Short name T1077
Test name
Test status
Simulation time 23672600 ps
CPU time 13.91 seconds
Started Feb 18 01:38:57 PM PST 24
Finished Feb 18 01:39:47 PM PST 24
Peak memory 261952 kb
Host smart-b3b95bea-13ac-4b13-b081-89004d832b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567221942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
3567221942
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4140525653
Short name T1073
Test name
Test status
Simulation time 173619100 ps
CPU time 31.21 seconds
Started Feb 18 01:38:52 PM PST 24
Finished Feb 18 01:40:00 PM PST 24
Peak memory 259664 kb
Host smart-eea4205a-7df4-4091-ae4a-5de806ad2d03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140525653 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.4140525653
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1976849587
Short name T1069
Test name
Test status
Simulation time 30018400 ps
CPU time 15.56 seconds
Started Feb 18 01:39:02 PM PST 24
Finished Feb 18 01:39:55 PM PST 24
Peak memory 259456 kb
Host smart-ac937a46-9368-453b-8e7d-2a4d1496bd2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976849587 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.1976849587
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1047480726
Short name T1084
Test name
Test status
Simulation time 13778200 ps
CPU time 15.51 seconds
Started Feb 18 01:39:03 PM PST 24
Finished Feb 18 01:39:58 PM PST 24
Peak memory 259532 kb
Host smart-d48d54ba-cfff-4a52-b1f5-927f8d8db324
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047480726 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1047480726
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.402533816
Short name T195
Test name
Test status
Simulation time 139124800 ps
CPU time 16.95 seconds
Started Feb 18 01:38:54 PM PST 24
Finished Feb 18 01:39:56 PM PST 24
Peak memory 263264 kb
Host smart-d2e98ff2-ef7a-404c-ae39-a6beea3c4d06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402533816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.402533816
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.576067404
Short name T1109
Test name
Test status
Simulation time 78175000 ps
CPU time 17.74 seconds
Started Feb 18 01:39:10 PM PST 24
Finished Feb 18 01:40:06 PM PST 24
Peak memory 259620 kb
Host smart-33751598-a86c-4cdd-b866-241a10bfe360
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576067404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.flash_ctrl_csr_rw.576067404
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3827895738
Short name T1204
Test name
Test status
Simulation time 43808500 ps
CPU time 13.28 seconds
Started Feb 18 01:38:59 PM PST 24
Finished Feb 18 01:39:49 PM PST 24
Peak memory 261712 kb
Host smart-68737266-7681-4496-9c88-7de30fa4f96c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827895738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
3827895738
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1695255238
Short name T263
Test name
Test status
Simulation time 221515400 ps
CPU time 31.13 seconds
Started Feb 18 01:39:37 PM PST 24
Finished Feb 18 01:40:48 PM PST 24
Peak memory 259608 kb
Host smart-f350f0bd-e4c0-4177-8038-e856edcf312c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695255238 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1695255238
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1339669407
Short name T1199
Test name
Test status
Simulation time 14017700 ps
CPU time 15.46 seconds
Started Feb 18 01:39:04 PM PST 24
Finished Feb 18 01:39:58 PM PST 24
Peak memory 259452 kb
Host smart-e950bce1-34e2-4531-855b-f5b090813e8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339669407 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.1339669407
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.4073197425
Short name T1168
Test name
Test status
Simulation time 43227300 ps
CPU time 16.13 seconds
Started Feb 18 01:38:57 PM PST 24
Finished Feb 18 01:39:55 PM PST 24
Peak memory 259520 kb
Host smart-193f8448-dd2d-4590-b4eb-4b1ce4b69ab9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073197425 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.4073197425
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3155817846
Short name T1155
Test name
Test status
Simulation time 120125800 ps
CPU time 16.51 seconds
Started Feb 18 01:38:58 PM PST 24
Finished Feb 18 01:39:51 PM PST 24
Peak memory 263340 kb
Host smart-1e48b06a-3ad8-4f01-aa94-35b4e6cf0a09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155817846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
3155817846
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.361107692
Short name T330
Test name
Test status
Simulation time 184389100 ps
CPU time 453.27 seconds
Started Feb 18 01:38:55 PM PST 24
Finished Feb 18 01:47:08 PM PST 24
Peak memory 259652 kb
Host smart-1cad3545-a8b2-4926-b043-3df19e7202b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361107692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.361107692
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.586283184
Short name T171
Test name
Test status
Simulation time 92415000 ps
CPU time 18.27 seconds
Started Feb 18 01:39:13 PM PST 24
Finished Feb 18 01:40:08 PM PST 24
Peak memory 271588 kb
Host smart-462954ed-5a47-4dea-a388-c695a3bf020e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586283184 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.586283184
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2201334117
Short name T1181
Test name
Test status
Simulation time 236211900 ps
CPU time 17.61 seconds
Started Feb 18 01:39:04 PM PST 24
Finished Feb 18 01:40:04 PM PST 24
Peak memory 259604 kb
Host smart-dc9d0f93-87b3-4d9f-affb-f9d683f5b7a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201334117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.2201334117
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3792173005
Short name T1194
Test name
Test status
Simulation time 32768200 ps
CPU time 13.45 seconds
Started Feb 18 01:39:02 PM PST 24
Finished Feb 18 01:39:53 PM PST 24
Peak memory 261796 kb
Host smart-310f3444-0d45-4257-a189-1f0af7174b75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792173005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3792173005
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2303788351
Short name T277
Test name
Test status
Simulation time 106034700 ps
CPU time 18.37 seconds
Started Feb 18 01:38:59 PM PST 24
Finished Feb 18 01:39:59 PM PST 24
Peak memory 259688 kb
Host smart-b19b9d05-e592-4de0-b39e-7d496a64edd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303788351 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.2303788351
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1691880530
Short name T1180
Test name
Test status
Simulation time 15014600 ps
CPU time 15.62 seconds
Started Feb 18 01:39:01 PM PST 24
Finished Feb 18 01:39:53 PM PST 24
Peak memory 259532 kb
Host smart-0a3ed79b-b4d1-4b4f-81f0-0b3f7c76ba03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691880530 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1691880530
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3294167134
Short name T1118
Test name
Test status
Simulation time 12232000 ps
CPU time 13.27 seconds
Started Feb 18 01:39:10 PM PST 24
Finished Feb 18 01:40:01 PM PST 24
Peak memory 259520 kb
Host smart-fcba900b-a230-428d-87b0-af0f3ea9dd4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294167134 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3294167134
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3929075669
Short name T321
Test name
Test status
Simulation time 700281300 ps
CPU time 459.67 seconds
Started Feb 18 01:39:12 PM PST 24
Finished Feb 18 01:47:40 PM PST 24
Peak memory 263320 kb
Host smart-046022ff-72b2-49c1-b1ec-8d5e0b084188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929075669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.3929075669
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3366318975
Short name T1094
Test name
Test status
Simulation time 346082800 ps
CPU time 19.46 seconds
Started Feb 18 01:39:27 PM PST 24
Finished Feb 18 01:40:27 PM PST 24
Peak memory 271532 kb
Host smart-83c88b86-6e68-48e7-9b90-92c327bb3f86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366318975 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.3366318975
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2926874876
Short name T1124
Test name
Test status
Simulation time 274344300 ps
CPU time 15.25 seconds
Started Feb 18 01:39:23 PM PST 24
Finished Feb 18 01:40:20 PM PST 24
Peak memory 259528 kb
Host smart-3f9802f3-1fad-42f3-93fd-8fe04d4fe660
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926874876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.2926874876
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4000424308
Short name T1122
Test name
Test status
Simulation time 52227900 ps
CPU time 13.34 seconds
Started Feb 18 01:39:16 PM PST 24
Finished Feb 18 01:40:06 PM PST 24
Peak memory 261920 kb
Host smart-b383a1cb-cde2-476c-932c-f2a2c7f7807f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000424308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
4000424308
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2126553269
Short name T1117
Test name
Test status
Simulation time 38448900 ps
CPU time 15.1 seconds
Started Feb 18 01:39:17 PM PST 24
Finished Feb 18 01:40:15 PM PST 24
Peak memory 259664 kb
Host smart-833e62a9-0f01-4697-915e-39694b179aa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126553269 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2126553269
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2641091022
Short name T1090
Test name
Test status
Simulation time 14342400 ps
CPU time 13.12 seconds
Started Feb 18 01:39:09 PM PST 24
Finished Feb 18 01:39:59 PM PST 24
Peak memory 259512 kb
Host smart-0ca97af8-2a12-4174-85cc-59d79399dfe1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641091022 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.2641091022
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2825744175
Short name T1158
Test name
Test status
Simulation time 13814800 ps
CPU time 15.93 seconds
Started Feb 18 01:39:09 PM PST 24
Finished Feb 18 01:40:03 PM PST 24
Peak memory 259488 kb
Host smart-d54f2161-e7db-45a4-9782-d14fa585cb3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825744175 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2825744175
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3821820398
Short name T241
Test name
Test status
Simulation time 53552500 ps
CPU time 19.1 seconds
Started Feb 18 01:39:07 PM PST 24
Finished Feb 18 01:40:12 PM PST 24
Peak memory 263460 kb
Host smart-e0ee550a-6657-47cf-9efd-8e2f3744de2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821820398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
3821820398
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4122462490
Short name T1072
Test name
Test status
Simulation time 218062400 ps
CPU time 31.59 seconds
Started Feb 18 01:38:04 PM PST 24
Finished Feb 18 01:39:19 PM PST 24
Peak memory 259576 kb
Host smart-07c50cb1-d15c-4eae-913b-d3ba687c0c1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122462490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.4122462490
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1898752110
Short name T279
Test name
Test status
Simulation time 1271670000 ps
CPU time 65.53 seconds
Started Feb 18 01:38:06 PM PST 24
Finished Feb 18 01:39:55 PM PST 24
Peak memory 259584 kb
Host smart-85623be7-24e6-432a-a025-f869d1401ba0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898752110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.1898752110
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3799905648
Short name T1119
Test name
Test status
Simulation time 81841100 ps
CPU time 30.53 seconds
Started Feb 18 01:38:04 PM PST 24
Finished Feb 18 01:39:18 PM PST 24
Peak memory 259604 kb
Host smart-6f8e6bad-914f-420d-88f4-ff4c4b28d987
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799905648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.3799905648
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.742082613
Short name T1125
Test name
Test status
Simulation time 94781100 ps
CPU time 16.95 seconds
Started Feb 18 01:38:06 PM PST 24
Finished Feb 18 01:39:06 PM PST 24
Peak memory 259696 kb
Host smart-d99efde9-d2c1-4f00-95e4-8661b82b327b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742082613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_csr_rw.742082613
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.616358633
Short name T315
Test name
Test status
Simulation time 18560500 ps
CPU time 13.56 seconds
Started Feb 18 01:37:57 PM PST 24
Finished Feb 18 01:38:56 PM PST 24
Peak memory 261820 kb
Host smart-0744e499-c593-4d03-b6ca-06b8c485c3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616358633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.616358633
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2348194236
Short name T218
Test name
Test status
Simulation time 19435500 ps
CPU time 13.34 seconds
Started Feb 18 01:37:56 PM PST 24
Finished Feb 18 01:38:55 PM PST 24
Peak memory 262976 kb
Host smart-556a8c9c-b1ec-4a02-92ab-e9ff39923dbf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348194236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.2348194236
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3869265821
Short name T1167
Test name
Test status
Simulation time 16413300 ps
CPU time 13.21 seconds
Started Feb 18 01:38:04 PM PST 24
Finished Feb 18 01:39:01 PM PST 24
Peak memory 260824 kb
Host smart-5ec2ea84-a86a-4e65-82e9-c533ed793a21
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869265821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.3869265821
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.525519696
Short name T1183
Test name
Test status
Simulation time 817933200 ps
CPU time 36.24 seconds
Started Feb 18 01:38:04 PM PST 24
Finished Feb 18 01:39:24 PM PST 24
Peak memory 262456 kb
Host smart-619a2ac4-4436-4126-b1a5-7e65392defff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525519696 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.525519696
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2078620029
Short name T1150
Test name
Test status
Simulation time 22460900 ps
CPU time 15.86 seconds
Started Feb 18 01:37:57 PM PST 24
Finished Feb 18 01:38:58 PM PST 24
Peak memory 259536 kb
Host smart-67f2e361-467d-4dca-95af-00a517fde131
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078620029 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2078620029
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2260134622
Short name T1173
Test name
Test status
Simulation time 11737900 ps
CPU time 15.7 seconds
Started Feb 18 01:37:56 PM PST 24
Finished Feb 18 01:38:57 PM PST 24
Peak memory 259464 kb
Host smart-9df3dfbf-1cae-4250-b70d-d07a546701ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260134622 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2260134622
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.953069858
Short name T1182
Test name
Test status
Simulation time 27725500 ps
CPU time 15.76 seconds
Started Feb 18 01:37:58 PM PST 24
Finished Feb 18 01:38:59 PM PST 24
Peak memory 263432 kb
Host smart-6a955852-6759-48b5-a859-a8adacb00ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953069858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.953069858
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3888262535
Short name T329
Test name
Test status
Simulation time 5212957300 ps
CPU time 478.31 seconds
Started Feb 18 01:37:57 PM PST 24
Finished Feb 18 01:46:41 PM PST 24
Peak memory 260884 kb
Host smart-54d3cbe9-f791-46ef-b4c2-a2ae87e47e2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888262535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.3888262535
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2423463759
Short name T1130
Test name
Test status
Simulation time 30814500 ps
CPU time 13.43 seconds
Started Feb 18 01:39:23 PM PST 24
Finished Feb 18 01:40:35 PM PST 24
Peak memory 261756 kb
Host smart-0ed63b29-aaac-44e0-9e7c-1cacab7f5966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423463759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
2423463759
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1486691606
Short name T237
Test name
Test status
Simulation time 14677600 ps
CPU time 13.45 seconds
Started Feb 18 01:39:19 PM PST 24
Finished Feb 18 01:40:12 PM PST 24
Peak memory 261516 kb
Host smart-f500617b-d573-4ee4-ba75-41e3261e8726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486691606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
1486691606
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.389263819
Short name T1140
Test name
Test status
Simulation time 67607100 ps
CPU time 13.34 seconds
Started Feb 18 01:39:12 PM PST 24
Finished Feb 18 01:40:09 PM PST 24
Peak memory 261652 kb
Host smart-4bb3c2b4-b7e2-4868-a794-4cdb3fc9adb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389263819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.389263819
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4074407860
Short name T1137
Test name
Test status
Simulation time 42195000 ps
CPU time 13.46 seconds
Started Feb 18 01:39:18 PM PST 24
Finished Feb 18 01:40:12 PM PST 24
Peak memory 261916 kb
Host smart-985727eb-c679-4e27-8cc6-166e0be0d161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074407860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
4074407860
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.933141837
Short name T1189
Test name
Test status
Simulation time 56030300 ps
CPU time 13.41 seconds
Started Feb 18 01:39:14 PM PST 24
Finished Feb 18 01:40:04 PM PST 24
Peak memory 261820 kb
Host smart-57b65b50-6409-4c3d-8de6-2e83bc48c1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933141837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.933141837
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2482335666
Short name T1103
Test name
Test status
Simulation time 38037200 ps
CPU time 13.64 seconds
Started Feb 18 01:39:16 PM PST 24
Finished Feb 18 01:40:06 PM PST 24
Peak memory 261760 kb
Host smart-3b56cb65-09ce-4752-ad3d-989ed2a13cc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482335666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2482335666
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1581916347
Short name T1148
Test name
Test status
Simulation time 28390900 ps
CPU time 13.44 seconds
Started Feb 18 01:39:17 PM PST 24
Finished Feb 18 01:40:08 PM PST 24
Peak memory 261900 kb
Host smart-73a5adf0-64dc-4e89-9a02-de0f69619aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581916347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
1581916347
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3140370619
Short name T1203
Test name
Test status
Simulation time 80305100 ps
CPU time 13.21 seconds
Started Feb 18 01:39:13 PM PST 24
Finished Feb 18 01:40:04 PM PST 24
Peak memory 261924 kb
Host smart-1122824e-985c-419e-abdd-03cec19f438f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140370619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
3140370619
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2438205103
Short name T314
Test name
Test status
Simulation time 29832500 ps
CPU time 13.56 seconds
Started Feb 18 01:39:15 PM PST 24
Finished Feb 18 01:40:18 PM PST 24
Peak memory 261792 kb
Host smart-9f4f94e8-1773-4414-9f67-904bbbae8934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438205103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2438205103
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2342342412
Short name T1195
Test name
Test status
Simulation time 3260959000 ps
CPU time 63.93 seconds
Started Feb 18 01:38:11 PM PST 24
Finished Feb 18 01:39:59 PM PST 24
Peak memory 259452 kb
Host smart-ea35e27d-736b-4f14-baeb-cdc57952007a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342342412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2342342412
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1061768926
Short name T1082
Test name
Test status
Simulation time 4774153700 ps
CPU time 70.83 seconds
Started Feb 18 01:38:07 PM PST 24
Finished Feb 18 01:40:03 PM PST 24
Peak memory 259592 kb
Host smart-c73cef7a-0c56-4e2d-8557-0d7d32107722
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061768926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.1061768926
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1581438114
Short name T1091
Test name
Test status
Simulation time 20674600 ps
CPU time 30.43 seconds
Started Feb 18 01:38:04 PM PST 24
Finished Feb 18 01:39:18 PM PST 24
Peak memory 259596 kb
Host smart-9b45fa90-1558-4aca-81a7-39d9b5acfc83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581438114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.1581438114
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2979686680
Short name T266
Test name
Test status
Simulation time 354857000 ps
CPU time 20.98 seconds
Started Feb 18 01:38:14 PM PST 24
Finished Feb 18 01:39:19 PM PST 24
Peak memory 271616 kb
Host smart-143e27e1-9733-411b-b942-9cc1c4d12832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979686680 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2979686680
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1439175976
Short name T56
Test name
Test status
Simulation time 36658400 ps
CPU time 16.77 seconds
Started Feb 18 01:38:06 PM PST 24
Finished Feb 18 01:39:09 PM PST 24
Peak memory 259872 kb
Host smart-78c06715-4bba-418d-9452-8bc3a966795c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439175976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.1439175976
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3933014740
Short name T1166
Test name
Test status
Simulation time 72857300 ps
CPU time 13.55 seconds
Started Feb 18 01:38:05 PM PST 24
Finished Feb 18 01:39:02 PM PST 24
Peak memory 262016 kb
Host smart-7c535726-b6e3-4946-b449-59be174ffa09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933014740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3
933014740
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2521535496
Short name T220
Test name
Test status
Simulation time 19955200 ps
CPU time 13.43 seconds
Started Feb 18 01:38:05 PM PST 24
Finished Feb 18 01:39:01 PM PST 24
Peak memory 263192 kb
Host smart-fedd8b4b-45fd-4b85-a568-80a2af0d46e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521535496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.2521535496
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2663197511
Short name T1175
Test name
Test status
Simulation time 17918300 ps
CPU time 13.7 seconds
Started Feb 18 01:38:05 PM PST 24
Finished Feb 18 01:39:01 PM PST 24
Peak memory 260812 kb
Host smart-d6df07e6-e468-4a65-b45b-73aedef85051
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663197511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.2663197511
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1448698899
Short name T233
Test name
Test status
Simulation time 187506100 ps
CPU time 17.66 seconds
Started Feb 18 01:38:10 PM PST 24
Finished Feb 18 01:39:11 PM PST 24
Peak memory 259596 kb
Host smart-d5b3759f-8378-4185-967e-16c22bb7d708
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448698899 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.1448698899
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.429608938
Short name T1075
Test name
Test status
Simulation time 15202400 ps
CPU time 13.31 seconds
Started Feb 18 01:38:06 PM PST 24
Finished Feb 18 01:39:02 PM PST 24
Peak memory 259488 kb
Host smart-762a7f19-4f22-4c52-95a5-3912d9eaf29c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429608938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.429608938
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3920599427
Short name T1078
Test name
Test status
Simulation time 19092600 ps
CPU time 16.1 seconds
Started Feb 18 01:38:04 PM PST 24
Finished Feb 18 01:39:03 PM PST 24
Peak memory 259520 kb
Host smart-263ac551-800e-47e8-ba9a-2498d7399e9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920599427 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.3920599427
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2680616637
Short name T1088
Test name
Test status
Simulation time 31161300 ps
CPU time 16.1 seconds
Started Feb 18 01:38:03 PM PST 24
Finished Feb 18 01:39:02 PM PST 24
Peak memory 263328 kb
Host smart-69569841-c4d1-41cf-87da-fc0628c2394b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680616637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2
680616637
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2158496160
Short name T324
Test name
Test status
Simulation time 342322300 ps
CPU time 895.98 seconds
Started Feb 18 01:38:06 PM PST 24
Finished Feb 18 01:53:45 PM PST 24
Peak memory 263408 kb
Host smart-816a11bd-23d4-4180-95d1-de38cc724cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158496160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.2158496160
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2183686892
Short name T317
Test name
Test status
Simulation time 56462800 ps
CPU time 13.35 seconds
Started Feb 18 01:39:11 PM PST 24
Finished Feb 18 01:40:01 PM PST 24
Peak memory 261612 kb
Host smart-f39efc77-3ba0-4079-b91a-c92d1a512b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183686892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
2183686892
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1880698069
Short name T1134
Test name
Test status
Simulation time 52886000 ps
CPU time 13.56 seconds
Started Feb 18 01:39:24 PM PST 24
Finished Feb 18 01:40:16 PM PST 24
Peak memory 261604 kb
Host smart-1df58e31-62a8-4835-abe1-d207f02d5483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880698069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
1880698069
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1959357208
Short name T312
Test name
Test status
Simulation time 42242500 ps
CPU time 13.29 seconds
Started Feb 18 01:39:12 PM PST 24
Finished Feb 18 01:40:12 PM PST 24
Peak memory 261944 kb
Host smart-a186da77-a54c-4376-8104-3e2321609595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959357208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
1959357208
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4117775433
Short name T1141
Test name
Test status
Simulation time 58864300 ps
CPU time 13.24 seconds
Started Feb 18 01:39:17 PM PST 24
Finished Feb 18 01:40:08 PM PST 24
Peak memory 261672 kb
Host smart-dd4756b2-66c5-46e0-a6b6-7b0bae9921d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117775433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
4117775433
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1790716552
Short name T1113
Test name
Test status
Simulation time 42435100 ps
CPU time 13.71 seconds
Started Feb 18 01:39:17 PM PST 24
Finished Feb 18 01:40:08 PM PST 24
Peak memory 261692 kb
Host smart-b3e2ba9f-c058-4eea-a1e8-092fc1276e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790716552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
1790716552
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3194245274
Short name T1106
Test name
Test status
Simulation time 44249200 ps
CPU time 13.37 seconds
Started Feb 18 01:39:24 PM PST 24
Finished Feb 18 01:40:15 PM PST 24
Peak memory 261684 kb
Host smart-a8c27731-8b1b-43f3-a122-28acd758b43f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194245274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3194245274
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.634833358
Short name T235
Test name
Test status
Simulation time 17750300 ps
CPU time 13.2 seconds
Started Feb 18 01:39:14 PM PST 24
Finished Feb 18 01:40:04 PM PST 24
Peak memory 260820 kb
Host smart-ef90bb72-c790-4181-9c29-9a1de4ec37fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634833358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.634833358
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.640987745
Short name T310
Test name
Test status
Simulation time 119172100 ps
CPU time 13.39 seconds
Started Feb 18 01:39:25 PM PST 24
Finished Feb 18 01:40:26 PM PST 24
Peak memory 261772 kb
Host smart-68613fd8-3cbd-447b-9c7b-d0de13468257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640987745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.640987745
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1358481689
Short name T1138
Test name
Test status
Simulation time 36622000 ps
CPU time 13.28 seconds
Started Feb 18 01:39:18 PM PST 24
Finished Feb 18 01:40:12 PM PST 24
Peak memory 261776 kb
Host smart-fb0f8cac-1010-4f10-aa59-1467a271129e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358481689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
1358481689
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1680296123
Short name T274
Test name
Test status
Simulation time 1818636200 ps
CPU time 42.27 seconds
Started Feb 18 01:38:11 PM PST 24
Finished Feb 18 01:39:37 PM PST 24
Peak memory 259560 kb
Host smart-9fe319da-3fb4-498d-8178-45c68619849a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680296123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1680296123
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4114907672
Short name T1172
Test name
Test status
Simulation time 130889400 ps
CPU time 46.11 seconds
Started Feb 18 01:38:13 PM PST 24
Finished Feb 18 01:39:54 PM PST 24
Peak memory 259628 kb
Host smart-f6a8c641-04ed-4dcd-aaf0-a471696abd52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114907672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.4114907672
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1154357597
Short name T1147
Test name
Test status
Simulation time 141858500 ps
CPU time 19.85 seconds
Started Feb 18 01:38:09 PM PST 24
Finished Feb 18 01:39:20 PM PST 24
Peak memory 271624 kb
Host smart-3031d00f-5468-4484-8dae-46beb8a74254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154357597 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1154357597
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2114362058
Short name T278
Test name
Test status
Simulation time 76604900 ps
CPU time 16.47 seconds
Started Feb 18 01:38:15 PM PST 24
Finished Feb 18 01:39:14 PM PST 24
Peak memory 259616 kb
Host smart-2718cf1e-01c6-457d-ada5-099d322cab31
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114362058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.2114362058
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2672010725
Short name T1099
Test name
Test status
Simulation time 59553100 ps
CPU time 13.29 seconds
Started Feb 18 01:38:12 PM PST 24
Finished Feb 18 01:39:09 PM PST 24
Peak memory 261840 kb
Host smart-969811c8-4872-4604-8f2b-ee782b56b469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672010725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
672010725
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.495371004
Short name T219
Test name
Test status
Simulation time 43633700 ps
CPU time 13.53 seconds
Started Feb 18 01:38:10 PM PST 24
Finished Feb 18 01:39:06 PM PST 24
Peak memory 263276 kb
Host smart-64ae8ffe-5421-47a0-8707-a00334fb2ade
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495371004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.495371004
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1251920199
Short name T1097
Test name
Test status
Simulation time 25093700 ps
CPU time 13.16 seconds
Started Feb 18 01:38:11 PM PST 24
Finished Feb 18 01:39:08 PM PST 24
Peak memory 261700 kb
Host smart-e96df58f-67e7-45b7-a3d9-1f864e0e3eb9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251920199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.1251920199
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1308558394
Short name T1163
Test name
Test status
Simulation time 827614600 ps
CPU time 35.8 seconds
Started Feb 18 01:38:12 PM PST 24
Finished Feb 18 01:39:30 PM PST 24
Peak memory 261212 kb
Host smart-a2f9925d-6e83-486a-8e53-c1ee7d2fe777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308558394 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.1308558394
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4165017242
Short name T1095
Test name
Test status
Simulation time 85380900 ps
CPU time 15.86 seconds
Started Feb 18 01:38:10 PM PST 24
Finished Feb 18 01:39:08 PM PST 24
Peak memory 259468 kb
Host smart-c14be453-a467-44a5-9c5d-e84c93744ffc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165017242 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.4165017242
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2524503927
Short name T1116
Test name
Test status
Simulation time 30111300 ps
CPU time 15.48 seconds
Started Feb 18 01:38:10 PM PST 24
Finished Feb 18 01:39:08 PM PST 24
Peak memory 259504 kb
Host smart-51132839-aa7d-4768-98cf-b2e1dee03bda
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524503927 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.2524503927
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3567921137
Short name T1176
Test name
Test status
Simulation time 160450100 ps
CPU time 17.44 seconds
Started Feb 18 01:38:10 PM PST 24
Finished Feb 18 01:39:10 PM PST 24
Peak memory 263384 kb
Host smart-72df0f60-c4f9-4935-8374-b099188eb447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567921137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3
567921137
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.4167139060
Short name T1107
Test name
Test status
Simulation time 71025300 ps
CPU time 13.63 seconds
Started Feb 18 01:39:11 PM PST 24
Finished Feb 18 01:40:02 PM PST 24
Peak memory 261656 kb
Host smart-1a224791-2fda-40ee-b93f-48fc70d52b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167139060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
4167139060
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2893023303
Short name T1161
Test name
Test status
Simulation time 56629100 ps
CPU time 13.53 seconds
Started Feb 18 01:39:18 PM PST 24
Finished Feb 18 01:40:13 PM PST 24
Peak memory 261992 kb
Host smart-5002f929-de91-453d-a9df-97a639b31533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893023303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
2893023303
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4060399676
Short name T1188
Test name
Test status
Simulation time 17053700 ps
CPU time 13.27 seconds
Started Feb 18 01:39:17 PM PST 24
Finished Feb 18 01:40:13 PM PST 24
Peak memory 261760 kb
Host smart-deb56ee6-fe11-4977-9036-87bd7930deb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060399676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
4060399676
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.51091304
Short name T313
Test name
Test status
Simulation time 28504800 ps
CPU time 13.38 seconds
Started Feb 18 01:39:21 PM PST 24
Finished Feb 18 01:40:15 PM PST 24
Peak memory 261996 kb
Host smart-e1acbb6f-6b42-4e32-978d-328831805eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51091304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.51091304
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2562108845
Short name T1193
Test name
Test status
Simulation time 30580700 ps
CPU time 13.23 seconds
Started Feb 18 01:39:22 PM PST 24
Finished Feb 18 01:40:33 PM PST 24
Peak memory 261916 kb
Host smart-acada21d-7e53-4e81-8c7c-a17dafe053d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562108845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
2562108845
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1238478657
Short name T1114
Test name
Test status
Simulation time 40040200 ps
CPU time 13.38 seconds
Started Feb 18 01:39:26 PM PST 24
Finished Feb 18 01:40:20 PM PST 24
Peak memory 261872 kb
Host smart-22f8abb3-b4a9-41d9-9b1f-1275b0362ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238478657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
1238478657
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3499102644
Short name T1165
Test name
Test status
Simulation time 15106500 ps
CPU time 13.54 seconds
Started Feb 18 01:39:19 PM PST 24
Finished Feb 18 01:40:12 PM PST 24
Peak memory 262004 kb
Host smart-a1809213-975a-4d73-8a59-0863f2fae445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499102644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
3499102644
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1718880452
Short name T1157
Test name
Test status
Simulation time 27768600 ps
CPU time 13.29 seconds
Started Feb 18 01:39:26 PM PST 24
Finished Feb 18 01:40:23 PM PST 24
Peak memory 260144 kb
Host smart-5a91231b-30ba-445c-bdab-e46b61f44f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718880452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
1718880452
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3922437861
Short name T1105
Test name
Test status
Simulation time 17612400 ps
CPU time 13.4 seconds
Started Feb 18 01:39:21 PM PST 24
Finished Feb 18 01:40:29 PM PST 24
Peak memory 261944 kb
Host smart-7b41b368-dddb-4df5-aa52-6ae46d691fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922437861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3922437861
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.804214017
Short name T214
Test name
Test status
Simulation time 136119200 ps
CPU time 22.67 seconds
Started Feb 18 01:38:27 PM PST 24
Finished Feb 18 01:39:33 PM PST 24
Peak memory 271576 kb
Host smart-f285d3f0-e6d9-4923-87fa-4e666d3d4300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804214017 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.804214017
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3574469394
Short name T1186
Test name
Test status
Simulation time 28294300 ps
CPU time 16.56 seconds
Started Feb 18 01:38:25 PM PST 24
Finished Feb 18 01:39:34 PM PST 24
Peak memory 259700 kb
Host smart-1840562a-011b-4d9b-97d3-f26a5863f173
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574469394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.3574469394
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2511443459
Short name T311
Test name
Test status
Simulation time 86015300 ps
CPU time 13.29 seconds
Started Feb 18 01:38:24 PM PST 24
Finished Feb 18 01:39:18 PM PST 24
Peak memory 261984 kb
Host smart-ca136dba-fe0f-4b40-b8c6-62e52cf6b7a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511443459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2
511443459
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4120463632
Short name T1108
Test name
Test status
Simulation time 37734700 ps
CPU time 17.35 seconds
Started Feb 18 01:38:37 PM PST 24
Finished Feb 18 01:39:35 PM PST 24
Peak memory 259700 kb
Host smart-22df434a-8c89-4814-b4cf-443a166cdcc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120463632 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.4120463632
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2295340435
Short name T1081
Test name
Test status
Simulation time 11627300 ps
CPU time 15.77 seconds
Started Feb 18 01:38:17 PM PST 24
Finished Feb 18 01:39:14 PM PST 24
Peak memory 259444 kb
Host smart-91f551e2-0969-42b2-b7a8-c86df790898e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295340435 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.2295340435
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3114276372
Short name T1100
Test name
Test status
Simulation time 41521600 ps
CPU time 13.04 seconds
Started Feb 18 01:38:18 PM PST 24
Finished Feb 18 01:39:13 PM PST 24
Peak memory 259532 kb
Host smart-dda5eed1-66b4-4f39-b86b-1a0ed72f78b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114276372 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.3114276372
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1398509193
Short name T196
Test name
Test status
Simulation time 38941800 ps
CPU time 16.3 seconds
Started Feb 18 01:38:11 PM PST 24
Finished Feb 18 01:39:12 PM PST 24
Peak memory 263460 kb
Host smart-4b410721-3fd3-44bf-951b-46695cf538c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398509193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1
398509193
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3330091202
Short name T271
Test name
Test status
Simulation time 7825717000 ps
CPU time 912.37 seconds
Started Feb 18 01:38:10 PM PST 24
Finished Feb 18 01:54:05 PM PST 24
Peak memory 263484 kb
Host smart-68ca74d6-8e1b-4566-9e91-611d22057b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330091202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.3330091202
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.81084117
Short name T1177
Test name
Test status
Simulation time 157436800 ps
CPU time 20.04 seconds
Started Feb 18 01:38:36 PM PST 24
Finished Feb 18 01:39:36 PM PST 24
Peak memory 276632 kb
Host smart-6faf384a-dfd7-40b9-ab9a-67f89e9cc4e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81084117 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.81084117
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1035001689
Short name T269
Test name
Test status
Simulation time 99756500 ps
CPU time 16.54 seconds
Started Feb 18 01:38:29 PM PST 24
Finished Feb 18 01:39:28 PM PST 24
Peak memory 259720 kb
Host smart-ad4c1bbd-b32c-474c-92cf-9eff28a4cb35
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035001689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.1035001689
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3928973079
Short name T1112
Test name
Test status
Simulation time 15646900 ps
CPU time 13.21 seconds
Started Feb 18 01:38:24 PM PST 24
Finished Feb 18 01:39:19 PM PST 24
Peak memory 261784 kb
Host smart-dba279b8-8ec2-4904-bd1e-d16fea67747c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928973079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3
928973079
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.885658255
Short name T234
Test name
Test status
Simulation time 336120900 ps
CPU time 35.97 seconds
Started Feb 18 01:38:33 PM PST 24
Finished Feb 18 01:39:49 PM PST 24
Peak memory 259628 kb
Host smart-dfb59802-1598-4ed8-95d5-c3ebff5a1134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885658255 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.885658255
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.681709601
Short name T1110
Test name
Test status
Simulation time 21000300 ps
CPU time 15.63 seconds
Started Feb 18 01:38:33 PM PST 24
Finished Feb 18 01:39:31 PM PST 24
Peak memory 259500 kb
Host smart-138c2325-37bd-4337-9eff-5b52986c87ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681709601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.681709601
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3087985596
Short name T1146
Test name
Test status
Simulation time 18393000 ps
CPU time 15.8 seconds
Started Feb 18 01:38:34 PM PST 24
Finished Feb 18 01:39:35 PM PST 24
Peak memory 259592 kb
Host smart-c996bfe4-d45c-4d48-9bfd-1bf301e2b2e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087985596 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.3087985596
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.261935372
Short name T1115
Test name
Test status
Simulation time 95517300 ps
CPU time 18.97 seconds
Started Feb 18 01:38:27 PM PST 24
Finished Feb 18 01:39:27 PM PST 24
Peak memory 263464 kb
Host smart-ae5b7775-4f29-4b7a-90a5-8832a936f45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261935372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.261935372
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.893224382
Short name T170
Test name
Test status
Simulation time 1746434000 ps
CPU time 378.58 seconds
Started Feb 18 01:38:29 PM PST 24
Finished Feb 18 01:45:37 PM PST 24
Peak memory 259656 kb
Host smart-dcc1aeea-36ff-4404-8f29-c7f26244cbcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893224382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
tl_intg_err.893224382
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2660673252
Short name T264
Test name
Test status
Simulation time 66254300 ps
CPU time 16.98 seconds
Started Feb 18 01:38:35 PM PST 24
Finished Feb 18 01:39:34 PM PST 24
Peak memory 259544 kb
Host smart-c65be015-bbd0-47ae-8d60-e43bc343ae01
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660673252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.2660673252
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3179061422
Short name T1089
Test name
Test status
Simulation time 15044700 ps
CPU time 13.29 seconds
Started Feb 18 01:38:34 PM PST 24
Finished Feb 18 01:39:33 PM PST 24
Peak memory 261976 kb
Host smart-23d58f22-4bcb-4be0-a1c4-52614bc4df74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179061422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3
179061422
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2191285128
Short name T276
Test name
Test status
Simulation time 394373300 ps
CPU time 31.16 seconds
Started Feb 18 01:38:33 PM PST 24
Finished Feb 18 01:39:48 PM PST 24
Peak memory 259576 kb
Host smart-0e762508-9f51-4bb6-bd83-df6001eb046d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191285128 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.2191285128
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1187645227
Short name T1079
Test name
Test status
Simulation time 14113000 ps
CPU time 13.17 seconds
Started Feb 18 01:38:29 PM PST 24
Finished Feb 18 01:39:23 PM PST 24
Peak memory 259488 kb
Host smart-6297fd14-5af8-43fe-9678-6931b4712d45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187645227 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.1187645227
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.209619238
Short name T1202
Test name
Test status
Simulation time 11698100 ps
CPU time 13.01 seconds
Started Feb 18 01:38:25 PM PST 24
Finished Feb 18 01:39:19 PM PST 24
Peak memory 259528 kb
Host smart-3c5e56fe-e587-40bf-89d6-8fde52908d66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209619238 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.209619238
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.872455840
Short name T1184
Test name
Test status
Simulation time 47567000 ps
CPU time 18.28 seconds
Started Feb 18 01:38:32 PM PST 24
Finished Feb 18 01:39:31 PM PST 24
Peak memory 263432 kb
Host smart-1c47c1a7-000a-460c-a145-dc0aa9aa3808
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872455840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.872455840
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3866603031
Short name T270
Test name
Test status
Simulation time 1475489100 ps
CPU time 900.1 seconds
Started Feb 18 01:38:34 PM PST 24
Finished Feb 18 01:54:17 PM PST 24
Peak memory 260076 kb
Host smart-9a2ffff0-6c71-4c95-8668-c17971dc212d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866603031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.3866603031
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2976151840
Short name T280
Test name
Test status
Simulation time 31873100 ps
CPU time 17.01 seconds
Started Feb 18 01:38:41 PM PST 24
Finished Feb 18 01:39:37 PM PST 24
Peak memory 259596 kb
Host smart-3685d80b-b6cf-4c89-9c35-87764a1b057d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976151840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2976151840
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2974482074
Short name T1076
Test name
Test status
Simulation time 39701900 ps
CPU time 13.21 seconds
Started Feb 18 01:38:33 PM PST 24
Finished Feb 18 01:39:29 PM PST 24
Peak memory 261740 kb
Host smart-5417cc82-21c6-47f1-915f-249c7a2629b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974482074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.2
974482074
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3875019307
Short name T262
Test name
Test status
Simulation time 412041500 ps
CPU time 36.29 seconds
Started Feb 18 01:38:36 PM PST 24
Finished Feb 18 01:39:54 PM PST 24
Peak memory 259652 kb
Host smart-1afc3417-6540-4d97-84c3-640ae08eaf43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875019307 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3875019307
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2326000332
Short name T1096
Test name
Test status
Simulation time 55477400 ps
CPU time 13.28 seconds
Started Feb 18 01:38:29 PM PST 24
Finished Feb 18 01:39:25 PM PST 24
Peak memory 259516 kb
Host smart-2ae01925-2225-4b25-a326-b4f79bfbc807
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326000332 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2326000332
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2803807322
Short name T1149
Test name
Test status
Simulation time 21620300 ps
CPU time 15.46 seconds
Started Feb 18 01:38:36 PM PST 24
Finished Feb 18 01:39:41 PM PST 24
Peak memory 259468 kb
Host smart-52d63c96-734b-419e-b65f-588d59b05cad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803807322 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.2803807322
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1636178268
Short name T319
Test name
Test status
Simulation time 437181300 ps
CPU time 19.52 seconds
Started Feb 18 01:38:27 PM PST 24
Finished Feb 18 01:39:30 PM PST 24
Peak memory 263340 kb
Host smart-e82ef246-111d-402c-bbca-3922b442b2eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636178268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1
636178268
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2123198311
Short name T326
Test name
Test status
Simulation time 815441400 ps
CPU time 903.02 seconds
Started Feb 18 01:38:37 PM PST 24
Finished Feb 18 01:54:21 PM PST 24
Peak memory 263448 kb
Host smart-61f69e68-43dd-4886-8c24-3fad053a2762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123198311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.2123198311
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2963159739
Short name T1191
Test name
Test status
Simulation time 290040800 ps
CPU time 24.39 seconds
Started Feb 18 01:38:33 PM PST 24
Finished Feb 18 01:39:38 PM PST 24
Peak memory 271600 kb
Host smart-6cb6d81f-d58e-4403-b42a-5079eaa12925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963159739 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2963159739
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.661010903
Short name T1160
Test name
Test status
Simulation time 61174800 ps
CPU time 16.38 seconds
Started Feb 18 01:38:33 PM PST 24
Finished Feb 18 01:39:33 PM PST 24
Peak memory 259600 kb
Host smart-ce53ef5d-cee1-4bde-9c55-a8c3629b4055
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661010903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_csr_rw.661010903
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.844682217
Short name T1156
Test name
Test status
Simulation time 17438800 ps
CPU time 13.34 seconds
Started Feb 18 01:38:35 PM PST 24
Finished Feb 18 01:39:29 PM PST 24
Peak memory 261884 kb
Host smart-c198d7eb-5d3d-4c6e-a6fb-2c41eb8fd1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844682217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.844682217
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.419478042
Short name T1087
Test name
Test status
Simulation time 618762600 ps
CPU time 35.16 seconds
Started Feb 18 01:38:41 PM PST 24
Finished Feb 18 01:39:55 PM PST 24
Peak memory 262272 kb
Host smart-6733669f-83b8-48ac-8567-0ad2544dc1a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419478042 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.419478042
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.58507918
Short name T1171
Test name
Test status
Simulation time 15113700 ps
CPU time 13.24 seconds
Started Feb 18 01:38:35 PM PST 24
Finished Feb 18 01:39:30 PM PST 24
Peak memory 259516 kb
Host smart-141828e8-5a51-4381-a009-edd7003f308a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58507918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.58507918
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4257286015
Short name T1187
Test name
Test status
Simulation time 38717100 ps
CPU time 15.83 seconds
Started Feb 18 01:38:37 PM PST 24
Finished Feb 18 01:39:34 PM PST 24
Peak memory 259520 kb
Host smart-3b8c4c0d-4278-4899-9c68-c1e942570f47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257286015 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.4257286015
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.4186403538
Short name T328
Test name
Test status
Simulation time 1374690900 ps
CPU time 912.07 seconds
Started Feb 18 01:38:33 PM PST 24
Finished Feb 18 01:54:27 PM PST 24
Peak memory 263424 kb
Host smart-7fdab257-8022-408f-9b09-4d04ce278c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186403538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.4186403538
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.2842256308
Short name T611
Test name
Test status
Simulation time 135536200 ps
CPU time 14.1 seconds
Started Feb 18 02:43:44 PM PST 24
Finished Feb 18 02:44:01 PM PST 24
Peak memory 264216 kb
Host smart-5f11171f-50d9-4ebb-b0ee-1229263ea030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842256308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2
842256308
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.4152943634
Short name T912
Test name
Test status
Simulation time 21898100 ps
CPU time 15.78 seconds
Started Feb 18 02:43:18 PM PST 24
Finished Feb 18 02:43:35 PM PST 24
Peak memory 274804 kb
Host smart-cf76ca4a-971b-4dae-9be5-e7991990b38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152943634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.4152943634
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.927991322
Short name T616
Test name
Test status
Simulation time 185374900 ps
CPU time 104.93 seconds
Started Feb 18 02:43:09 PM PST 24
Finished Feb 18 02:44:57 PM PST 24
Peak memory 280904 kb
Host smart-a44bfa47-6735-4ec2-bebb-e3a2c7c22b00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927991322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_derr_detect.927991322
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.1480058939
Short name T948
Test name
Test status
Simulation time 8718051200 ps
CPU time 353.94 seconds
Started Feb 18 02:42:50 PM PST 24
Finished Feb 18 02:48:45 PM PST 24
Peak memory 261904 kb
Host smart-58c3220d-4f44-4122-9818-5658f8cb5546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480058939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.1480058939
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.1137923561
Short name T710
Test name
Test status
Simulation time 153019400 ps
CPU time 27.34 seconds
Started Feb 18 02:42:55 PM PST 24
Finished Feb 18 02:43:24 PM PST 24
Peak memory 264292 kb
Host smart-16d1130a-ca23-49c5-9183-0c1b7d591153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137923561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.1137923561
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.517048882
Short name T735
Test name
Test status
Simulation time 1174427300 ps
CPU time 36.22 seconds
Started Feb 18 02:43:25 PM PST 24
Finished Feb 18 02:44:03 PM PST 24
Peak memory 274644 kb
Host smart-92e3a1b6-35bb-4a59-b182-c4ebbe509e74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517048882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_fs_sup.517048882
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.357717705
Short name T500
Test name
Test status
Simulation time 87027000 ps
CPU time 81.05 seconds
Started Feb 18 02:42:40 PM PST 24
Finished Feb 18 02:44:04 PM PST 24
Peak memory 264216 kb
Host smart-65a73f01-a8b4-4f72-a020-6892b1345e1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357717705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.357717705
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.994137476
Short name T698
Test name
Test status
Simulation time 53182200 ps
CPU time 13.45 seconds
Started Feb 18 02:43:34 PM PST 24
Finished Feb 18 02:43:48 PM PST 24
Peak memory 264268 kb
Host smart-12505f70-8d74-4c3c-92c9-6a91856264f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994137476 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.994137476
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.3142181374
Short name T913
Test name
Test status
Simulation time 271924588800 ps
CPU time 1797.38 seconds
Started Feb 18 02:42:52 PM PST 24
Finished Feb 18 03:12:50 PM PST 24
Peak memory 262216 kb
Host smart-902e688e-2a75-4d9c-b806-ca29f7dd49b4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142181374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.3142181374
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.1326982859
Short name T823
Test name
Test status
Simulation time 5803032400 ps
CPU time 66.97 seconds
Started Feb 18 02:42:47 PM PST 24
Finished Feb 18 02:43:56 PM PST 24
Peak memory 261500 kb
Host smart-97f59cc2-7e44-42bc-b943-cce964ec45d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326982859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.1326982859
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.1125841060
Short name T623
Test name
Test status
Simulation time 1299047100 ps
CPU time 195.49 seconds
Started Feb 18 02:43:10 PM PST 24
Finished Feb 18 02:46:28 PM PST 24
Peak memory 292112 kb
Host smart-907e336c-8a62-4976-8171-051f6e180ae7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125841060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.1125841060
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.4128998151
Short name T676
Test name
Test status
Simulation time 15477070800 ps
CPU time 227.67 seconds
Started Feb 18 02:43:16 PM PST 24
Finished Feb 18 02:47:06 PM PST 24
Peak memory 290028 kb
Host smart-9b626047-b658-45db-83be-4b36c88984d7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128998151 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.4128998151
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3516990181
Short name T1041
Test name
Test status
Simulation time 71987159000 ps
CPU time 548.26 seconds
Started Feb 18 02:43:12 PM PST 24
Finished Feb 18 02:52:24 PM PST 24
Peak memory 264404 kb
Host smart-87ae48d0-521f-47a9-9fef-0887441cdf24
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351
6990181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.3516990181
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.1573225103
Short name T139
Test name
Test status
Simulation time 101723864700 ps
CPU time 667.52 seconds
Started Feb 18 02:42:53 PM PST 24
Finished Feb 18 02:54:01 PM PST 24
Peak memory 272192 kb
Host smart-1b58de76-17eb-4e1a-b8f5-610ec4ce4ba7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573225103 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.1573225103
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.1105826344
Short name T593
Test name
Test status
Simulation time 2182361500 ps
CPU time 192.89 seconds
Started Feb 18 02:43:07 PM PST 24
Finished Feb 18 02:46:22 PM PST 24
Peak memory 280984 kb
Host smart-b2583efa-1ac7-4b74-a3ac-fe0244a250c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105826344 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.1105826344
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.1439276028
Short name T133
Test name
Test status
Simulation time 14840100 ps
CPU time 14.14 seconds
Started Feb 18 02:43:29 PM PST 24
Finished Feb 18 02:43:45 PM PST 24
Peak memory 277056 kb
Host smart-5861f3c8-19e8-4e7f-a33e-af04e7a4e35c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1439276028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.1439276028
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.3849127480
Short name T548
Test name
Test status
Simulation time 1537377100 ps
CPU time 461.52 seconds
Started Feb 18 02:42:48 PM PST 24
Finished Feb 18 02:50:31 PM PST 24
Peak memory 261340 kb
Host smart-d73d717a-8e46-4587-8b45-fb91a26386c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849127480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3849127480
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3686350940
Short name T66
Test name
Test status
Simulation time 713302700 ps
CPU time 25.7 seconds
Started Feb 18 02:43:35 PM PST 24
Finished Feb 18 02:44:01 PM PST 24
Peak memory 264552 kb
Host smart-5ebf42e2-941a-4864-96c8-49fda56f229b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686350940 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3686350940
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.881169447
Short name T194
Test name
Test status
Simulation time 14438500 ps
CPU time 14.39 seconds
Started Feb 18 02:43:35 PM PST 24
Finished Feb 18 02:43:51 PM PST 24
Peak memory 264616 kb
Host smart-49f01d67-0d59-40db-9613-97775375e95c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881169447 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.881169447
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.3438571298
Short name T444
Test name
Test status
Simulation time 184578200 ps
CPU time 13.63 seconds
Started Feb 18 02:43:13 PM PST 24
Finished Feb 18 02:43:30 PM PST 24
Peak memory 264344 kb
Host smart-c1198bb2-27c0-4d73-97f5-1116239416bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438571298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.3438571298
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.488253429
Short name T147
Test name
Test status
Simulation time 1532904000 ps
CPU time 402 seconds
Started Feb 18 02:42:44 PM PST 24
Finished Feb 18 02:49:28 PM PST 24
Peak memory 280540 kb
Host smart-6fcbe707-5578-406d-8828-ef392c1b9b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488253429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.488253429
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.3353942280
Short name T627
Test name
Test status
Simulation time 217754800 ps
CPU time 32.19 seconds
Started Feb 18 02:43:19 PM PST 24
Finished Feb 18 02:43:52 PM PST 24
Peak memory 278504 kb
Host smart-9e378a31-fd47-45c4-a176-7c7f6dfbeef0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353942280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.3353942280
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.1694870686
Short name T407
Test name
Test status
Simulation time 143724200 ps
CPU time 45.15 seconds
Started Feb 18 02:43:37 PM PST 24
Finished Feb 18 02:44:23 PM PST 24
Peak memory 272700 kb
Host smart-004325d9-75fb-4bba-b21a-ecd3419bb36d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694870686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.1694870686
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.1670478091
Short name T648
Test name
Test status
Simulation time 44519500 ps
CPU time 32.91 seconds
Started Feb 18 02:43:14 PM PST 24
Finished Feb 18 02:43:50 PM PST 24
Peak memory 277024 kb
Host smart-2e83a378-e8cf-41b8-8cc6-76bee3b1d808
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670478091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.1670478091
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.2918887351
Short name T460
Test name
Test status
Simulation time 20636000 ps
CPU time 13.62 seconds
Started Feb 18 02:42:56 PM PST 24
Finished Feb 18 02:43:12 PM PST 24
Peak memory 264328 kb
Host smart-b6a9aad4-24ef-4b7e-a9cd-1cf02044345f
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2918887351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.2918887351
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.1393603433
Short name T576
Test name
Test status
Simulation time 53569800 ps
CPU time 23.11 seconds
Started Feb 18 02:43:02 PM PST 24
Finished Feb 18 02:43:28 PM PST 24
Peak memory 264508 kb
Host smart-0e61ff8f-8ae0-49d9-895e-c007a446d4c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393603433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.1393603433
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2281570941
Short name T103
Test name
Test status
Simulation time 41329604500 ps
CPU time 839.04 seconds
Started Feb 18 02:43:35 PM PST 24
Finished Feb 18 02:57:35 PM PST 24
Peak memory 258228 kb
Host smart-00bd41eb-2f6b-48e0-98f4-b56f4fa1315f
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281570941 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2281570941
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.2983636129
Short name T838
Test name
Test status
Simulation time 841011100 ps
CPU time 109.96 seconds
Started Feb 18 02:43:04 PM PST 24
Finished Feb 18 02:44:56 PM PST 24
Peak memory 280748 kb
Host smart-904deb66-3037-4de4-afa1-7a1f412c92fb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983636129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_ro.2983636129
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.2079232786
Short name T756
Test name
Test status
Simulation time 455431200 ps
CPU time 123.91 seconds
Started Feb 18 02:43:06 PM PST 24
Finished Feb 18 02:45:11 PM PST 24
Peak memory 280932 kb
Host smart-2acfe2f9-e2e5-4d27-acd9-b11e17a91b4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2079232786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2079232786
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.1895808793
Short name T246
Test name
Test status
Simulation time 2361120000 ps
CPU time 134.62 seconds
Started Feb 18 02:43:04 PM PST 24
Finished Feb 18 02:45:20 PM PST 24
Peak memory 289140 kb
Host smart-69948d53-56d2-4e30-8442-48a589e3f325
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895808793 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.1895808793
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1367861451
Short name T292
Test name
Test status
Simulation time 7067842100 ps
CPU time 569.86 seconds
Started Feb 18 02:43:03 PM PST 24
Finished Feb 18 02:52:35 PM PST 24
Peak memory 313044 kb
Host smart-537b24fd-bc34-4218-bdbd-14cbec617f6a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367861451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw.1367861451
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.3422291331
Short name T300
Test name
Test status
Simulation time 132478500 ps
CPU time 38.58 seconds
Started Feb 18 02:43:14 PM PST 24
Finished Feb 18 02:43:55 PM PST 24
Peak memory 264488 kb
Host smart-e1dbf771-1385-47d1-b80b-cc823ac73407
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422291331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.3422291331
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.4246423580
Short name T513
Test name
Test status
Simulation time 52258900 ps
CPU time 29.5 seconds
Started Feb 18 02:43:13 PM PST 24
Finished Feb 18 02:43:46 PM PST 24
Peak memory 265520 kb
Host smart-b2b55d70-1e19-4751-849a-df3865a28e31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246423580 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.4246423580
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.192355098
Short name T1040
Test name
Test status
Simulation time 52062017000 ps
CPU time 598.35 seconds
Started Feb 18 02:43:10 PM PST 24
Finished Feb 18 02:53:10 PM PST 24
Peak memory 311384 kb
Host smart-7ddc129e-0af4-49e2-878f-dc523bbbd3bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192355098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_se
rr.192355098
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.4167272909
Short name T355
Test name
Test status
Simulation time 4976787900 ps
CPU time 69.75 seconds
Started Feb 18 02:43:15 PM PST 24
Finished Feb 18 02:44:27 PM PST 24
Peak memory 263984 kb
Host smart-73bb86f9-b375-403a-818f-2e5ac1a54c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167272909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.4167272909
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.2048952419
Short name T1066
Test name
Test status
Simulation time 826779500 ps
CPU time 52.95 seconds
Started Feb 18 02:43:10 PM PST 24
Finished Feb 18 02:44:06 PM PST 24
Peak memory 264476 kb
Host smart-3f34a16c-a55a-44e7-8f99-52fac2826fea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048952419 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.2048952419
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.107504608
Short name T1003
Test name
Test status
Simulation time 910935600 ps
CPU time 84.82 seconds
Started Feb 18 02:43:14 PM PST 24
Finished Feb 18 02:44:42 PM PST 24
Peak memory 272744 kb
Host smart-fb12b963-8ff3-4a88-b5a0-4d400767dad4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107504608 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_counter.107504608
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.600439716
Short name T836
Test name
Test status
Simulation time 105355200 ps
CPU time 74.19 seconds
Started Feb 18 02:42:53 PM PST 24
Finished Feb 18 02:44:08 PM PST 24
Peak memory 274744 kb
Host smart-3d9627ab-ba15-4531-ba36-3472d3fd580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600439716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.600439716
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.1848172414
Short name T157
Test name
Test status
Simulation time 116973800 ps
CPU time 24.73 seconds
Started Feb 18 02:42:47 PM PST 24
Finished Feb 18 02:43:13 PM PST 24
Peak memory 258032 kb
Host smart-332caa20-141e-40a5-8b17-46f510da7d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848172414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1848172414
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.4084540785
Short name T820
Test name
Test status
Simulation time 540594400 ps
CPU time 1534.63 seconds
Started Feb 18 02:43:25 PM PST 24
Finished Feb 18 03:09:02 PM PST 24
Peak memory 288888 kb
Host smart-c40cb1e8-436c-47b1-9f34-e6ad45a7b120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084540785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.4084540785
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.4090020935
Short name T980
Test name
Test status
Simulation time 93108100 ps
CPU time 26.24 seconds
Started Feb 18 02:42:41 PM PST 24
Finished Feb 18 02:43:10 PM PST 24
Peak memory 258052 kb
Host smart-2c846e9f-23be-4965-8042-a2b254ad9d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090020935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.4090020935
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.517954886
Short name T609
Test name
Test status
Simulation time 4605605600 ps
CPU time 204.95 seconds
Started Feb 18 02:42:56 PM PST 24
Finished Feb 18 02:46:24 PM PST 24
Peak memory 264364 kb
Host smart-6a301b97-a54f-4d1f-9b06-5647d4c3df03
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517954886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_wo.517954886
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.993424164
Short name T10
Test name
Test status
Simulation time 85251400 ps
CPU time 14.72 seconds
Started Feb 18 02:43:20 PM PST 24
Finished Feb 18 02:43:36 PM PST 24
Peak memory 264368 kb
Host smart-ab1618a4-d452-4de3-aa66-51499fcc3484
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993424164 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.993424164
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.2130906401
Short name T898
Test name
Test status
Simulation time 227114500 ps
CPU time 14.36 seconds
Started Feb 18 02:42:56 PM PST 24
Finished Feb 18 02:43:12 PM PST 24
Peak memory 264240 kb
Host smart-6653407f-1cba-4ce8-94e3-d8a3cfe42807
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2130906401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.2130906401
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.899330622
Short name T454
Test name
Test status
Simulation time 108079400 ps
CPU time 13.71 seconds
Started Feb 18 02:44:42 PM PST 24
Finished Feb 18 02:45:00 PM PST 24
Peak memory 263908 kb
Host smart-e19ec2a8-fb31-47fa-9766-9e8cb8d7825e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899330622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.899330622
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.2653894451
Short name T230
Test name
Test status
Simulation time 122437300 ps
CPU time 14.01 seconds
Started Feb 18 02:44:35 PM PST 24
Finished Feb 18 02:44:50 PM PST 24
Peak memory 264296 kb
Host smart-e3b488bd-ee2f-4508-af4a-4d8dff5b0835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653894451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.2653894451
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.116802148
Short name T643
Test name
Test status
Simulation time 13904400 ps
CPU time 15.93 seconds
Started Feb 18 02:44:35 PM PST 24
Finished Feb 18 02:44:51 PM PST 24
Peak memory 273960 kb
Host smart-f15e4219-b213-4487-a42d-3a6c0be689f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116802148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.116802148
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.164216099
Short name T1052
Test name
Test status
Simulation time 126365200 ps
CPU time 104.47 seconds
Started Feb 18 02:44:15 PM PST 24
Finished Feb 18 02:46:00 PM PST 24
Peak memory 272744 kb
Host smart-d8cf706a-55b0-4816-b094-3eccc1c9c09e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164216099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_derr_detect.164216099
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.3207009420
Short name T52
Test name
Test status
Simulation time 1397788200 ps
CPU time 305.53 seconds
Started Feb 18 02:43:46 PM PST 24
Finished Feb 18 02:48:53 PM PST 24
Peak memory 260212 kb
Host smart-73f94148-0975-42a0-9d26-1a00b8f5f704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207009420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3207009420
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.1893887563
Short name T951
Test name
Test status
Simulation time 53031797400 ps
CPU time 2360.25 seconds
Started Feb 18 02:44:00 PM PST 24
Finished Feb 18 03:23:22 PM PST 24
Peak memory 263400 kb
Host smart-eb8d2e27-7335-4756-84e9-7a40c5badb74
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893887563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.1893887563
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.759636332
Short name T1038
Test name
Test status
Simulation time 984990000 ps
CPU time 2755.1 seconds
Started Feb 18 02:44:08 PM PST 24
Finished Feb 18 03:30:05 PM PST 24
Peak memory 263992 kb
Host smart-6082798c-240b-41a0-987b-bf56feb2d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759636332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.759636332
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.3838016747
Short name T204
Test name
Test status
Simulation time 3200278600 ps
CPU time 858.68 seconds
Started Feb 18 02:44:02 PM PST 24
Finished Feb 18 02:58:21 PM PST 24
Peak memory 264208 kb
Host smart-daf6f7b6-b76f-49e4-b399-108798c44a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838016747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3838016747
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.487555886
Short name T465
Test name
Test status
Simulation time 343138400 ps
CPU time 25.24 seconds
Started Feb 18 02:44:01 PM PST 24
Finished Feb 18 02:44:27 PM PST 24
Peak memory 264304 kb
Host smart-7f3cdd55-7e22-498b-a872-ae43ef1e9fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487555886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.487555886
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.2329476865
Short name T294
Test name
Test status
Simulation time 942495900 ps
CPU time 37.95 seconds
Started Feb 18 02:44:30 PM PST 24
Finished Feb 18 02:45:08 PM PST 24
Peak memory 275296 kb
Host smart-5be29865-3c23-4635-ba14-b48945b4e2bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329476865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.2329476865
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.2747512997
Short name T71
Test name
Test status
Simulation time 95579165000 ps
CPU time 2547.96 seconds
Started Feb 18 02:44:07 PM PST 24
Finished Feb 18 03:26:38 PM PST 24
Peak memory 263736 kb
Host smart-f4a5fb80-3dc0-4d41-9535-eea529b4dc2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747512997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.2747512997
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.3968492406
Short name T1028
Test name
Test status
Simulation time 93482500 ps
CPU time 129.17 seconds
Started Feb 18 02:43:47 PM PST 24
Finished Feb 18 02:45:58 PM PST 24
Peak memory 261272 kb
Host smart-ccaaa8b6-be59-4ae6-9cda-04107f8c57d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968492406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3968492406
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1314949284
Short name T750
Test name
Test status
Simulation time 10012750000 ps
CPU time 118.25 seconds
Started Feb 18 02:44:42 PM PST 24
Finished Feb 18 02:46:44 PM PST 24
Peak memory 340792 kb
Host smart-2586487b-ea3d-4d45-a3b5-99598ab08835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314949284 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1314949284
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.1824037565
Short name T619
Test name
Test status
Simulation time 45799600 ps
CPU time 13.87 seconds
Started Feb 18 02:44:44 PM PST 24
Finished Feb 18 02:45:01 PM PST 24
Peak memory 264416 kb
Host smart-bdaf6f18-454b-4190-8772-e790dfe98571
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824037565 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.1824037565
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.3241882383
Short name T728
Test name
Test status
Simulation time 80142145800 ps
CPU time 777.11 seconds
Started Feb 18 02:43:52 PM PST 24
Finished Feb 18 02:56:50 PM PST 24
Peak memory 262228 kb
Host smart-1ae00ce1-de51-4b61-b944-258421ef32d4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241882383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.3241882383
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.3411330924
Short name T378
Test name
Test status
Simulation time 3002684800 ps
CPU time 138 seconds
Started Feb 18 02:43:46 PM PST 24
Finished Feb 18 02:46:06 PM PST 24
Peak memory 260752 kb
Host smart-d405c622-2464-4310-ad0c-9f0734ed8ef8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411330924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.3411330924
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.1413466004
Short name T226
Test name
Test status
Simulation time 7309570100 ps
CPU time 653.89 seconds
Started Feb 18 02:44:16 PM PST 24
Finished Feb 18 02:55:11 PM PST 24
Peak memory 333788 kb
Host smart-e6bd36c1-a4ff-4de9-bf05-8e048c15c657
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413466004 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.1413466004
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.1991107696
Short name T252
Test name
Test status
Simulation time 5520116400 ps
CPU time 218.52 seconds
Started Feb 18 02:44:16 PM PST 24
Finished Feb 18 02:47:55 PM PST 24
Peak memory 283888 kb
Host smart-48cbe844-f9ba-44cb-a023-7507c7746ea4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991107696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.1991107696
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.85965372
Short name T626
Test name
Test status
Simulation time 17321023400 ps
CPU time 200.55 seconds
Started Feb 18 02:44:24 PM PST 24
Finished Feb 18 02:47:46 PM PST 24
Peak memory 292576 kb
Host smart-8b35fb4e-2977-42eb-9422-b501c955f903
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85965372 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.85965372
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.3207884812
Short name T121
Test name
Test status
Simulation time 15052768100 ps
CPU time 118.57 seconds
Started Feb 18 02:44:23 PM PST 24
Finished Feb 18 02:46:24 PM PST 24
Peak memory 264340 kb
Host smart-504df18d-fc81-44e1-b358-d867a9c703b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207884812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.3207884812
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.271387423
Short name T908
Test name
Test status
Simulation time 82983026800 ps
CPU time 326.46 seconds
Started Feb 18 02:44:22 PM PST 24
Finished Feb 18 02:49:51 PM PST 24
Peak memory 264336 kb
Host smart-7c2e2b74-2a2a-4137-a962-b167ec2b19e1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271
387423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.271387423
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.3079627299
Short name T398
Test name
Test status
Simulation time 28328600 ps
CPU time 13.45 seconds
Started Feb 18 02:44:44 PM PST 24
Finished Feb 18 02:45:00 PM PST 24
Peak memory 264336 kb
Host smart-a1a2efaa-c8a9-4133-8378-e7b92f8750c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079627299 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3079627299
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.4233573852
Short name T70
Test name
Test status
Simulation time 12892352300 ps
CPU time 413.59 seconds
Started Feb 18 02:43:53 PM PST 24
Finished Feb 18 02:50:47 PM PST 24
Peak memory 272804 kb
Host smart-7d71ca75-2211-4e40-b097-8cc8ff96d8a8
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233573852 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.4233573852
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.1286424638
Short name T471
Test name
Test status
Simulation time 2261900500 ps
CPU time 116.59 seconds
Started Feb 18 02:44:18 PM PST 24
Finished Feb 18 02:46:16 PM PST 24
Peak memory 280908 kb
Host smart-52044c4f-9cce-488a-91fd-c0e59c4d3737
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286424638 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1286424638
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.4285962113
Short name T565
Test name
Test status
Simulation time 26633900 ps
CPU time 68.82 seconds
Started Feb 18 02:43:46 PM PST 24
Finished Feb 18 02:44:56 PM PST 24
Peak memory 263868 kb
Host smart-8cc16e08-e927-4508-9581-7d107fbbed8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285962113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.4285962113
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.1265396306
Short name T69
Test name
Test status
Simulation time 757395700 ps
CPU time 25.93 seconds
Started Feb 18 02:44:28 PM PST 24
Finished Feb 18 02:44:55 PM PST 24
Peak memory 264540 kb
Host smart-05271e61-5171-4618-93c7-1c095f5428d8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265396306 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.1265396306
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.1144730503
Short name T721
Test name
Test status
Simulation time 40336700 ps
CPU time 13.94 seconds
Started Feb 18 02:44:23 PM PST 24
Finished Feb 18 02:44:39 PM PST 24
Peak memory 264356 kb
Host smart-d48c2ee0-0830-4aa6-9e50-0595855f0588
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144730503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.1144730503
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.3913695485
Short name T287
Test name
Test status
Simulation time 164873900 ps
CPU time 469.75 seconds
Started Feb 18 02:43:43 PM PST 24
Finished Feb 18 02:51:37 PM PST 24
Peak memory 280644 kb
Host smart-60def2e8-14bc-44b3-b95f-4c3542587a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913695485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3913695485
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.2890023861
Short name T191
Test name
Test status
Simulation time 2918903100 ps
CPU time 151.78 seconds
Started Feb 18 02:43:45 PM PST 24
Finished Feb 18 02:46:19 PM PST 24
Peak memory 264336 kb
Host smart-39882348-eb65-4671-b0bd-c6d712411620
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2890023861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.2890023861
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.1526513026
Short name T306
Test name
Test status
Simulation time 208194500 ps
CPU time 32.26 seconds
Started Feb 18 02:44:29 PM PST 24
Finished Feb 18 02:45:02 PM PST 24
Peak memory 273596 kb
Host smart-fea8b67f-f845-43a9-b871-77d89673b91e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526513026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.1526513026
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.3772421419
Short name T634
Test name
Test status
Simulation time 531882700 ps
CPU time 38.73 seconds
Started Feb 18 02:44:24 PM PST 24
Finished Feb 18 02:45:05 PM PST 24
Peak memory 265476 kb
Host smart-6a545d86-79d3-47bb-855e-6346ef4c1d34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772421419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.3772421419
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.3230834848
Short name T605
Test name
Test status
Simulation time 33116800 ps
CPU time 22.33 seconds
Started Feb 18 02:44:09 PM PST 24
Finished Feb 18 02:44:33 PM PST 24
Peak memory 263440 kb
Host smart-a6effa5d-c755-4b5e-8f84-077cb4bd8970
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230834848 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.3230834848
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.2681314805
Short name T714
Test name
Test status
Simulation time 122091400 ps
CPU time 22.82 seconds
Started Feb 18 02:44:12 PM PST 24
Finished Feb 18 02:44:37 PM PST 24
Peak memory 264368 kb
Host smart-9be1659f-a9dc-499f-883c-085370beb2bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681314805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.2681314805
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.1980723981
Short name T102
Test name
Test status
Simulation time 41800930300 ps
CPU time 816.72 seconds
Started Feb 18 02:44:37 PM PST 24
Finished Feb 18 02:58:15 PM PST 24
Peak memory 258080 kb
Host smart-0394d71c-e7c7-4f03-b6f6-fd8ab7588b26
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980723981 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.1980723981
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.1099286509
Short name T697
Test name
Test status
Simulation time 438926800 ps
CPU time 115.78 seconds
Started Feb 18 02:44:11 PM PST 24
Finished Feb 18 02:46:09 PM PST 24
Peak memory 280060 kb
Host smart-ed77e52c-0be3-4d99-8a0f-daaa2a35bc6c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099286509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_ro.1099286509
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.1300887797
Short name T433
Test name
Test status
Simulation time 2048050500 ps
CPU time 135.6 seconds
Started Feb 18 02:44:09 PM PST 24
Finished Feb 18 02:46:27 PM PST 24
Peak memory 293212 kb
Host smart-8143fc8c-cfcf-4372-b27b-03ceacd7fd16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300887797 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.1300887797
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2517871149
Short name T458
Test name
Test status
Simulation time 1376295500 ps
CPU time 334.06 seconds
Started Feb 18 02:44:10 PM PST 24
Finished Feb 18 02:49:46 PM PST 24
Peak memory 308352 kb
Host smart-52e5e64b-b8e8-4a6e-a536-608807e7e387
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517871149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw.2517871149
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.3231140192
Short name T528
Test name
Test status
Simulation time 77421500 ps
CPU time 31.26 seconds
Started Feb 18 02:44:22 PM PST 24
Finished Feb 18 02:44:54 PM PST 24
Peak memory 271516 kb
Host smart-8f03d110-b318-44f3-ba38-9a6523c4e979
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231140192 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.3231140192
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.1638683129
Short name T129
Test name
Test status
Simulation time 20722186800 ps
CPU time 621.71 seconds
Started Feb 18 02:44:11 PM PST 24
Finished Feb 18 02:54:36 PM PST 24
Peak memory 311220 kb
Host smart-06cc5210-b4f2-4523-ab27-a3f39979f795
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638683129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.1638683129
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.3922286846
Short name T901
Test name
Test status
Simulation time 1790854900 ps
CPU time 68.06 seconds
Started Feb 18 02:44:28 PM PST 24
Finished Feb 18 02:45:38 PM PST 24
Peak memory 263216 kb
Host smart-1540da12-afa7-4f89-84c5-296efbe44af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922286846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3922286846
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.3630077384
Short name T799
Test name
Test status
Simulation time 340245700 ps
CPU time 42.55 seconds
Started Feb 18 02:44:11 PM PST 24
Finished Feb 18 02:44:56 PM PST 24
Peak memory 264476 kb
Host smart-95b80251-da49-433f-a9b2-f1177729f9c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630077384 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.3630077384
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.2357608930
Short name T377
Test name
Test status
Simulation time 730658200 ps
CPU time 80.06 seconds
Started Feb 18 02:44:15 PM PST 24
Finished Feb 18 02:45:36 PM PST 24
Peak memory 272748 kb
Host smart-a482aa58-cd78-4d63-bd61-a3e384379472
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357608930 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.2357608930
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.2032173346
Short name T936
Test name
Test status
Simulation time 49419200 ps
CPU time 121.43 seconds
Started Feb 18 02:43:37 PM PST 24
Finished Feb 18 02:45:39 PM PST 24
Peak memory 274680 kb
Host smart-282ce474-f57b-4449-bb0e-c691e778c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032173346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.2032173346
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.4010675201
Short name T987
Test name
Test status
Simulation time 52327300 ps
CPU time 24.33 seconds
Started Feb 18 02:43:43 PM PST 24
Finished Feb 18 02:44:11 PM PST 24
Peak memory 258124 kb
Host smart-badf5e0c-4888-4b49-9359-d8d08b97e12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010675201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.4010675201
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.4757643
Short name T440
Test name
Test status
Simulation time 4362970200 ps
CPU time 1856.9 seconds
Started Feb 18 02:44:30 PM PST 24
Finished Feb 18 03:15:28 PM PST 24
Peak memory 297080 kb
Host smart-cb871768-4301-482d-9ced-9c728f7d6f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4757643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_a
ll.4757643
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2406731230
Short name T28
Test name
Test status
Simulation time 20651000 ps
CPU time 26.93 seconds
Started Feb 18 02:43:36 PM PST 24
Finished Feb 18 02:44:04 PM PST 24
Peak memory 258060 kb
Host smart-30715a47-df5e-478a-8b1e-f8867aa834a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406731230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2406731230
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.3293418335
Short name T476
Test name
Test status
Simulation time 3121492800 ps
CPU time 193.13 seconds
Started Feb 18 02:44:05 PM PST 24
Finished Feb 18 02:47:20 PM PST 24
Peak memory 264324 kb
Host smart-4a100ed7-e6e0-4f93-8f14-07e7fc49cf94
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293418335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_wo.3293418335
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.660728738
Short name T375
Test name
Test status
Simulation time 29421000 ps
CPU time 15.91 seconds
Started Feb 18 02:49:43 PM PST 24
Finished Feb 18 02:49:59 PM PST 24
Peak memory 274600 kb
Host smart-6edac5f0-5d93-41f8-a343-40e2cf47ff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660728738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.660728738
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.2240707294
Short name T463
Test name
Test status
Simulation time 33737000 ps
CPU time 20.67 seconds
Started Feb 18 02:49:39 PM PST 24
Finished Feb 18 02:50:01 PM PST 24
Peak memory 272636 kb
Host smart-a75e16f5-defb-48f3-a36c-9d65e87f25f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240707294 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.2240707294
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1420747138
Short name T846
Test name
Test status
Simulation time 10012756200 ps
CPU time 115.04 seconds
Started Feb 18 02:49:47 PM PST 24
Finished Feb 18 02:51:43 PM PST 24
Peak memory 320920 kb
Host smart-c87836bc-b2db-4ac8-add3-b5f45d69c67e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420747138 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1420747138
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.1083539253
Short name T817
Test name
Test status
Simulation time 80150991300 ps
CPU time 809.42 seconds
Started Feb 18 02:49:32 PM PST 24
Finished Feb 18 03:03:02 PM PST 24
Peak memory 261840 kb
Host smart-465f1e60-570d-45fc-a99c-909a534a0dd2
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083539253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.1083539253
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3377474772
Short name T509
Test name
Test status
Simulation time 9755444500 ps
CPU time 155.37 seconds
Started Feb 18 02:49:32 PM PST 24
Finished Feb 18 02:52:08 PM PST 24
Peak memory 258188 kb
Host smart-c18799d5-ef87-485c-a741-c158db49f632
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377474772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.3377474772
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.1946315901
Short name T844
Test name
Test status
Simulation time 2213079100 ps
CPU time 153.46 seconds
Started Feb 18 02:49:42 PM PST 24
Finished Feb 18 02:52:16 PM PST 24
Peak memory 293052 kb
Host smart-b1242860-1196-467d-9bcf-996affdb9082
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946315901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.1946315901
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.409657434
Short name T927
Test name
Test status
Simulation time 7951913600 ps
CPU time 214.09 seconds
Started Feb 18 02:49:42 PM PST 24
Finished Feb 18 02:53:17 PM PST 24
Peak memory 289052 kb
Host smart-2408a6d5-11d9-42db-bd5c-6b9254a3b21c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409657434 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.409657434
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.2728548555
Short name T357
Test name
Test status
Simulation time 11464812000 ps
CPU time 75.45 seconds
Started Feb 18 02:49:31 PM PST 24
Finished Feb 18 02:50:47 PM PST 24
Peak memory 259552 kb
Host smart-32663c54-2313-4357-8813-f21bfd60e5b4
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728548555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.2
728548555
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1689062732
Short name T136
Test name
Test status
Simulation time 17891735300 ps
CPU time 1188.82 seconds
Started Feb 18 02:49:32 PM PST 24
Finished Feb 18 03:09:22 PM PST 24
Peak memory 272976 kb
Host smart-43b4e7b0-f720-4b47-b085-ef0694e2d37d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689062732 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.1689062732
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.1517709049
Short name T1023
Test name
Test status
Simulation time 104142200 ps
CPU time 410 seconds
Started Feb 18 02:49:23 PM PST 24
Finished Feb 18 02:56:15 PM PST 24
Peak memory 264336 kb
Host smart-ae3f4187-d69e-4f83-abf9-92a5233df609
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517709049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.1517709049
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.3329900929
Short name T431
Test name
Test status
Simulation time 66111900 ps
CPU time 13.82 seconds
Started Feb 18 02:49:44 PM PST 24
Finished Feb 18 02:49:59 PM PST 24
Peak memory 264284 kb
Host smart-826f5110-b9d3-4d80-8ca3-0dc461faa8da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329900929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.3329900929
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.3241744925
Short name T77
Test name
Test status
Simulation time 98799900 ps
CPU time 372.65 seconds
Started Feb 18 02:49:25 PM PST 24
Finished Feb 18 02:55:40 PM PST 24
Peak memory 280664 kb
Host smart-0371e174-3a19-4b22-9a7c-e9822f145db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241744925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.3241744925
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.2517121410
Short name T550
Test name
Test status
Simulation time 163861800 ps
CPU time 38.9 seconds
Started Feb 18 02:49:44 PM PST 24
Finished Feb 18 02:50:25 PM PST 24
Peak memory 276240 kb
Host smart-b5222fd1-3d23-408d-8ec1-d934273fd2a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517121410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.2517121410
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.314910386
Short name T812
Test name
Test status
Simulation time 504596100 ps
CPU time 104.65 seconds
Started Feb 18 02:49:35 PM PST 24
Finished Feb 18 02:51:22 PM PST 24
Peak memory 280532 kb
Host smart-10589791-33b3-4d95-9c56-4c082a836388
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314910386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_ro.314910386
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.3958035860
Short name T954
Test name
Test status
Simulation time 6933991700 ps
CPU time 472.19 seconds
Started Feb 18 02:49:30 PM PST 24
Finished Feb 18 02:57:24 PM PST 24
Peak memory 308420 kb
Host smart-38705ab9-0e58-413c-a8a4-485b723547ad
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958035860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw.3958035860
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.2089491029
Short name T537
Test name
Test status
Simulation time 141646300 ps
CPU time 34.15 seconds
Started Feb 18 02:49:45 PM PST 24
Finished Feb 18 02:50:21 PM PST 24
Peak memory 273760 kb
Host smart-b9c86282-601c-4e8b-96cd-7d4fc71bb69d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089491029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.2089491029
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.3377640523
Short name T892
Test name
Test status
Simulation time 1978131000 ps
CPU time 74.64 seconds
Started Feb 18 02:49:44 PM PST 24
Finished Feb 18 02:51:00 PM PST 24
Peak memory 262708 kb
Host smart-18f519ff-f027-4685-a88b-5a0e9dd7585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377640523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.3377640523
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.2239477384
Short name T517
Test name
Test status
Simulation time 58808900 ps
CPU time 191.93 seconds
Started Feb 18 02:49:26 PM PST 24
Finished Feb 18 02:52:39 PM PST 24
Peak memory 275740 kb
Host smart-52aad618-94c6-43d8-a14e-f5e9aba440dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239477384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.2239477384
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.3664826649
Short name T450
Test name
Test status
Simulation time 10388887600 ps
CPU time 176.49 seconds
Started Feb 18 02:49:31 PM PST 24
Finished Feb 18 02:52:29 PM PST 24
Peak memory 264300 kb
Host smart-423a1241-4d92-4153-bef4-eca22224450d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664826649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.flash_ctrl_wo.3664826649
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.49292410
Short name T699
Test name
Test status
Simulation time 69831000 ps
CPU time 13.63 seconds
Started Feb 18 02:50:11 PM PST 24
Finished Feb 18 02:50:33 PM PST 24
Peak memory 264204 kb
Host smart-043a6694-4c90-47d9-a439-216bbed2cfda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49292410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.49292410
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.395593732
Short name T387
Test name
Test status
Simulation time 28762700 ps
CPU time 16.3 seconds
Started Feb 18 02:50:06 PM PST 24
Finished Feb 18 02:50:30 PM PST 24
Peak memory 273980 kb
Host smart-6f621725-02e9-4a97-b78a-a9501352cae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395593732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.395593732
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2962000500
Short name T527
Test name
Test status
Simulation time 43771600 ps
CPU time 13.61 seconds
Started Feb 18 02:50:13 PM PST 24
Finished Feb 18 02:50:35 PM PST 24
Peak memory 263620 kb
Host smart-9a218070-52a2-46b3-921d-ecb594728ba1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962000500 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2962000500
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.2013660955
Short name T114
Test name
Test status
Simulation time 190193261000 ps
CPU time 883.17 seconds
Started Feb 18 02:49:47 PM PST 24
Finished Feb 18 03:04:31 PM PST 24
Peak memory 262820 kb
Host smart-c8af0c76-b007-4cba-aee6-b76abfa08948
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013660955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.2013660955
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.1668252537
Short name T505
Test name
Test status
Simulation time 12465540000 ps
CPU time 81.75 seconds
Started Feb 18 02:49:49 PM PST 24
Finished Feb 18 02:51:13 PM PST 24
Peak memory 260892 kb
Host smart-a3397926-9825-4e5b-9f1b-e7bf61714a08
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668252537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.1668252537
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.1280789527
Short name T1060
Test name
Test status
Simulation time 1196804700 ps
CPU time 181.42 seconds
Started Feb 18 02:50:00 PM PST 24
Finished Feb 18 02:53:04 PM PST 24
Peak memory 292116 kb
Host smart-c476c989-5c8f-4005-9bc9-504c061129b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280789527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.1280789527
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3460384525
Short name T1008
Test name
Test status
Simulation time 8641489600 ps
CPU time 218.46 seconds
Started Feb 18 02:49:59 PM PST 24
Finished Feb 18 02:53:38 PM PST 24
Peak memory 290152 kb
Host smart-3720956f-b912-4c07-a798-85a75a12b497
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460384525 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.3460384525
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.4214198706
Short name T994
Test name
Test status
Simulation time 8769867200 ps
CPU time 66.62 seconds
Started Feb 18 02:49:54 PM PST 24
Finished Feb 18 02:51:02 PM PST 24
Peak memory 259628 kb
Host smart-5632c3b7-7aaf-4eb7-a1f2-bbe610c58408
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214198706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.4
214198706
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3327590949
Short name T427
Test name
Test status
Simulation time 15373100 ps
CPU time 14.01 seconds
Started Feb 18 02:50:13 PM PST 24
Finished Feb 18 02:50:36 PM PST 24
Peak memory 263712 kb
Host smart-455df96b-567d-4aeb-8946-a1d6c3c650f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327590949 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.3327590949
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.742299664
Short name T27
Test name
Test status
Simulation time 1418643400 ps
CPU time 134.97 seconds
Started Feb 18 02:49:52 PM PST 24
Finished Feb 18 02:52:08 PM PST 24
Peak memory 264180 kb
Host smart-3f36a25f-5d8f-499b-a26b-20472116ffc5
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742299664 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_mp_regions.742299664
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.1464944556
Short name T917
Test name
Test status
Simulation time 2879719700 ps
CPU time 378.52 seconds
Started Feb 18 02:49:49 PM PST 24
Finished Feb 18 02:56:09 PM PST 24
Peak memory 261316 kb
Host smart-3531d5f9-9ead-4f4d-8569-05b6b7b97177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464944556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1464944556
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.3721346625
Short name T601
Test name
Test status
Simulation time 28121500 ps
CPU time 13.6 seconds
Started Feb 18 02:50:00 PM PST 24
Finished Feb 18 02:50:15 PM PST 24
Peak memory 264356 kb
Host smart-1be8c139-5cc3-44c9-badd-c9262b765b70
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721346625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.3721346625
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.2589060357
Short name T934
Test name
Test status
Simulation time 30499900 ps
CPU time 103.7 seconds
Started Feb 18 02:49:50 PM PST 24
Finished Feb 18 02:51:35 PM PST 24
Peak memory 267400 kb
Host smart-14fdf02d-8846-4025-9d69-2d1375aeb5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589060357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2589060357
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.740901718
Short name T254
Test name
Test status
Simulation time 469965300 ps
CPU time 39.87 seconds
Started Feb 18 02:49:58 PM PST 24
Finished Feb 18 02:50:39 PM PST 24
Peak memory 265572 kb
Host smart-7c0bebeb-4f6c-4e59-8b3a-8040aa70d944
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740901718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_re_evict.740901718
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.769883918
Short name T551
Test name
Test status
Simulation time 1710845800 ps
CPU time 119.19 seconds
Started Feb 18 02:50:03 PM PST 24
Finished Feb 18 02:52:03 PM PST 24
Peak memory 280856 kb
Host smart-8af6c1aa-790b-4b9e-826e-bfac117dc06f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769883918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_ro.769883918
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.1623487703
Short name T842
Test name
Test status
Simulation time 6248157100 ps
CPU time 477.39 seconds
Started Feb 18 02:50:01 PM PST 24
Finished Feb 18 02:58:00 PM PST 24
Peak memory 313612 kb
Host smart-4d22326a-ebf1-4af9-8da6-3f92671c9bff
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623487703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw.1623487703
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.3626442896
Short name T765
Test name
Test status
Simulation time 149770500 ps
CPU time 33.61 seconds
Started Feb 18 02:50:00 PM PST 24
Finished Feb 18 02:50:34 PM PST 24
Peak memory 273688 kb
Host smart-a704ebda-6fbb-4187-9865-2ca75d7acd2c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626442896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.3626442896
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.2176007982
Short name T293
Test name
Test status
Simulation time 76893100 ps
CPU time 31.46 seconds
Started Feb 18 02:50:00 PM PST 24
Finished Feb 18 02:50:33 PM PST 24
Peak memory 272724 kb
Host smart-0e318fcc-de47-4526-ae6a-7d228563af95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176007982 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.2176007982
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.555231040
Short name T891
Test name
Test status
Simulation time 2787992100 ps
CPU time 75.87 seconds
Started Feb 18 02:50:13 PM PST 24
Finished Feb 18 02:51:38 PM PST 24
Peak memory 262444 kb
Host smart-f4a8afa6-f985-42ad-8bd5-50d7c517cc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555231040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.555231040
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.239418801
Short name T968
Test name
Test status
Simulation time 70295000 ps
CPU time 144.03 seconds
Started Feb 18 02:49:49 PM PST 24
Finished Feb 18 02:52:15 PM PST 24
Peak memory 274884 kb
Host smart-4ff3303a-b906-4219-be78-2fd5af7aa4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239418801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.239418801
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.3780405300
Short name T1006
Test name
Test status
Simulation time 8165133100 ps
CPU time 170.31 seconds
Started Feb 18 02:49:52 PM PST 24
Finished Feb 18 02:52:43 PM PST 24
Peak memory 264320 kb
Host smart-ba5205ff-65db-46c1-a8a5-ec8c4aad3fb8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780405300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.flash_ctrl_wo.3780405300
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.2676505943
Short name T530
Test name
Test status
Simulation time 61665500 ps
CPU time 13.89 seconds
Started Feb 18 02:50:26 PM PST 24
Finished Feb 18 02:50:42 PM PST 24
Peak memory 263944 kb
Host smart-a1bff2ce-84c1-4c9b-9111-8872b279aafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676505943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
2676505943
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.728636753
Short name T782
Test name
Test status
Simulation time 17948600 ps
CPU time 16.4 seconds
Started Feb 18 02:50:27 PM PST 24
Finished Feb 18 02:50:45 PM PST 24
Peak memory 274616 kb
Host smart-76669b9c-5830-4458-abaa-237df1574a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728636753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.728636753
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1267435249
Short name T335
Test name
Test status
Simulation time 34458700 ps
CPU time 21.98 seconds
Started Feb 18 02:50:25 PM PST 24
Finished Feb 18 02:50:49 PM PST 24
Peak memory 279676 kb
Host smart-5168c7ee-937e-4839-b2d4-7d40a9f71798
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267435249 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1267435249
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2627953662
Short name T733
Test name
Test status
Simulation time 10098602900 ps
CPU time 37.11 seconds
Started Feb 18 02:50:28 PM PST 24
Finished Feb 18 02:51:06 PM PST 24
Peak memory 264432 kb
Host smart-358fd56e-5e71-4349-b04e-eb32df836534
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627953662 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2627953662
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.2321627081
Short name T613
Test name
Test status
Simulation time 74794300 ps
CPU time 13.37 seconds
Started Feb 18 02:50:27 PM PST 24
Finished Feb 18 02:50:42 PM PST 24
Peak memory 264328 kb
Host smart-f54d2078-7299-4ba3-8da9-ef7960f5851e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321627081 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.2321627081
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2019892666
Short name T945
Test name
Test status
Simulation time 1870049900 ps
CPU time 66.91 seconds
Started Feb 18 02:50:19 PM PST 24
Finished Feb 18 02:51:33 PM PST 24
Peak memory 261452 kb
Host smart-827590a4-e9d3-4916-a3ba-18b893f0e384
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019892666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.2019892666
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.1415641336
Short name T953
Test name
Test status
Simulation time 2122448400 ps
CPU time 151.59 seconds
Started Feb 18 02:50:24 PM PST 24
Finished Feb 18 02:52:59 PM PST 24
Peak memory 292780 kb
Host smart-8f3beea8-f794-48cc-a109-cd6ac21f80d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415641336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.1415641336
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3856535614
Short name T979
Test name
Test status
Simulation time 50188366500 ps
CPU time 194.72 seconds
Started Feb 18 02:50:25 PM PST 24
Finished Feb 18 02:53:42 PM PST 24
Peak memory 283644 kb
Host smart-ff3becd1-99c6-4806-a499-2a09c1c2d9d4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856535614 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.3856535614
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.1780224742
Short name T145
Test name
Test status
Simulation time 1661295400 ps
CPU time 77.2 seconds
Started Feb 18 02:50:19 PM PST 24
Finished Feb 18 02:51:43 PM PST 24
Peak memory 259716 kb
Host smart-750dba2c-bf79-4d39-8e76-7e4b5b2a0028
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780224742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1
780224742
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.3555655743
Short name T459
Test name
Test status
Simulation time 15877200 ps
CPU time 13.25 seconds
Started Feb 18 02:50:26 PM PST 24
Finished Feb 18 02:50:41 PM PST 24
Peak memory 264252 kb
Host smart-1b92ce4c-552b-41a4-98d6-67ca82d86163
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555655743 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.3555655743
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.943767519
Short name T650
Test name
Test status
Simulation time 1569261000 ps
CPU time 165.08 seconds
Started Feb 18 02:50:18 PM PST 24
Finished Feb 18 02:53:10 PM PST 24
Peak memory 264256 kb
Host smart-41dae914-0d45-45ce-90da-af49a2898920
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943767519 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_mp_regions.943767519
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.2465803665
Short name T484
Test name
Test status
Simulation time 92332200 ps
CPU time 202.09 seconds
Started Feb 18 02:50:17 PM PST 24
Finished Feb 18 02:53:47 PM PST 24
Peak memory 261328 kb
Host smart-43702226-57ed-4f18-93e7-27d6d444f8d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465803665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2465803665
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.1055907267
Short name T690
Test name
Test status
Simulation time 116262600 ps
CPU time 15.01 seconds
Started Feb 18 02:50:25 PM PST 24
Finished Feb 18 02:50:43 PM PST 24
Peak memory 263632 kb
Host smart-01c7e67b-80c2-4a25-838c-21bdeb658fb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055907267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.1055907267
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.3312097129
Short name T983
Test name
Test status
Simulation time 480303000 ps
CPU time 1142.29 seconds
Started Feb 18 02:50:19 PM PST 24
Finished Feb 18 03:09:28 PM PST 24
Peak memory 287916 kb
Host smart-be0e16b1-738d-43e6-a120-e4c5454997b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312097129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3312097129
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.3031542446
Short name T464
Test name
Test status
Simulation time 490906700 ps
CPU time 35.73 seconds
Started Feb 18 02:50:22 PM PST 24
Finished Feb 18 02:51:02 PM PST 24
Peak memory 277108 kb
Host smart-cdcdf2c2-b576-4d3f-9d6e-02b10ff8bdfa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031542446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.3031542446
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.1830010007
Short name T553
Test name
Test status
Simulation time 505738700 ps
CPU time 126.71 seconds
Started Feb 18 02:50:19 PM PST 24
Finished Feb 18 02:52:33 PM PST 24
Peak memory 280568 kb
Host smart-e820b43f-4dcd-408b-a424-d0a243497e0c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830010007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_ro.1830010007
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.3428662940
Short name T732
Test name
Test status
Simulation time 2647026100 ps
CPU time 578.86 seconds
Started Feb 18 02:50:18 PM PST 24
Finished Feb 18 03:00:05 PM PST 24
Peak memory 313584 kb
Host smart-04394546-da06-46a6-be64-85563c1a7a85
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428662940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_rw.3428662940
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.261232228
Short name T744
Test name
Test status
Simulation time 53052300 ps
CPU time 31.5 seconds
Started Feb 18 02:50:23 PM PST 24
Finished Feb 18 02:50:59 PM PST 24
Peak memory 275864 kb
Host smart-d080ba8c-2d3d-4310-a02b-e5a18ea933e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261232228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_rw_evict.261232228
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.3377689856
Short name T543
Test name
Test status
Simulation time 90131300 ps
CPU time 30.95 seconds
Started Feb 18 02:50:23 PM PST 24
Finished Feb 18 02:50:58 PM PST 24
Peak memory 271672 kb
Host smart-880be64d-72bc-4a78-bc6f-b90fb43a8a53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377689856 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.3377689856
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2074640783
Short name T689
Test name
Test status
Simulation time 1395845900 ps
CPU time 64.6 seconds
Started Feb 18 02:50:22 PM PST 24
Finished Feb 18 02:51:31 PM PST 24
Peak memory 258692 kb
Host smart-c3188146-73e3-4e81-a2ad-08746e2717a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074640783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2074640783
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2979189873
Short name T478
Test name
Test status
Simulation time 47483000 ps
CPU time 73.74 seconds
Started Feb 18 02:50:13 PM PST 24
Finished Feb 18 02:51:36 PM PST 24
Peak memory 273708 kb
Host smart-e7530c23-5835-4a6b-b096-6029ff8c846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979189873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2979189873
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.326564690
Short name T566
Test name
Test status
Simulation time 9108295200 ps
CPU time 138.08 seconds
Started Feb 18 02:50:18 PM PST 24
Finished Feb 18 02:52:44 PM PST 24
Peak memory 264372 kb
Host smart-8aee762f-c6f1-47c5-961d-281a7e26ad1c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326564690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_wo.326564690
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.1249507278
Short name T587
Test name
Test status
Simulation time 28684400 ps
CPU time 13.67 seconds
Started Feb 18 02:51:07 PM PST 24
Finished Feb 18 02:51:23 PM PST 24
Peak memory 264228 kb
Host smart-d2f0b840-146e-4e20-89cb-7ea5ab8b1716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249507278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
1249507278
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.1326025878
Short name T909
Test name
Test status
Simulation time 16171300 ps
CPU time 15.94 seconds
Started Feb 18 02:50:55 PM PST 24
Finished Feb 18 02:51:12 PM PST 24
Peak memory 273800 kb
Host smart-74e3ea1a-b15d-48c2-9427-8f0c3cf9427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326025878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1326025878
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3565072589
Short name T981
Test name
Test status
Simulation time 10012084700 ps
CPU time 121.81 seconds
Started Feb 18 02:50:52 PM PST 24
Finished Feb 18 02:52:55 PM PST 24
Peak memory 313876 kb
Host smart-b1a1dc49-efe7-49ee-bf21-c8b3f77e3f3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565072589 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.3565072589
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1529719920
Short name T1059
Test name
Test status
Simulation time 33640400 ps
CPU time 14.24 seconds
Started Feb 18 02:51:08 PM PST 24
Finished Feb 18 02:51:26 PM PST 24
Peak memory 263588 kb
Host smart-bfab78eb-b971-4eaa-a0e7-c5f704f9bbb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529719920 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1529719920
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2538069527
Short name T805
Test name
Test status
Simulation time 190198259900 ps
CPU time 773.36 seconds
Started Feb 18 02:50:35 PM PST 24
Finished Feb 18 03:03:30 PM PST 24
Peak memory 258132 kb
Host smart-b0b6f868-a711-420d-9da8-43e6d268245f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538069527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.2538069527
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.828044875
Short name T578
Test name
Test status
Simulation time 6559248200 ps
CPU time 121.17 seconds
Started Feb 18 02:50:26 PM PST 24
Finished Feb 18 02:52:29 PM PST 24
Peak memory 258164 kb
Host smart-bb585c15-06cb-49c1-85f2-44e4f7a20301
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828044875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_h
w_sec_otp.828044875
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.2262908228
Short name T852
Test name
Test status
Simulation time 2244496200 ps
CPU time 183.29 seconds
Started Feb 18 02:50:41 PM PST 24
Finished Feb 18 02:53:46 PM PST 24
Peak memory 289092 kb
Host smart-95080184-5b77-4b94-b88e-2c6e79495aca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262908228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.2262908228
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.125187873
Short name T541
Test name
Test status
Simulation time 8985528200 ps
CPU time 275.8 seconds
Started Feb 18 02:50:41 PM PST 24
Finished Feb 18 02:55:18 PM PST 24
Peak memory 283928 kb
Host smart-91c59e71-d1fc-420c-af00-154e5ad450c5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125187873 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.125187873
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.3683059515
Short name T361
Test name
Test status
Simulation time 7078178700 ps
CPU time 69.4 seconds
Started Feb 18 02:50:35 PM PST 24
Finished Feb 18 02:51:46 PM PST 24
Peak memory 259660 kb
Host smart-03afb578-a012-4ab0-ad17-85ef9dc8706f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683059515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3
683059515
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2932808029
Short name T504
Test name
Test status
Simulation time 15341700 ps
CPU time 13.58 seconds
Started Feb 18 02:50:56 PM PST 24
Finished Feb 18 02:51:11 PM PST 24
Peak memory 264288 kb
Host smart-b2b62250-29b3-41a4-aad7-76377fc47a7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932808029 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2932808029
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.3543173926
Short name T536
Test name
Test status
Simulation time 3900416100 ps
CPU time 117.05 seconds
Started Feb 18 02:50:34 PM PST 24
Finished Feb 18 02:52:33 PM PST 24
Peak memory 260360 kb
Host smart-ec922cc3-3584-49ac-ada4-7f54eaa84bd6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543173926 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.3543173926
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.975271968
Short name T391
Test name
Test status
Simulation time 100511100 ps
CPU time 135.15 seconds
Started Feb 18 02:50:35 PM PST 24
Finished Feb 18 02:52:52 PM PST 24
Peak memory 258832 kb
Host smart-17062730-5a85-4691-9765-d857cb9a6d0d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975271968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ot
p_reset.975271968
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.2607048067
Short name T659
Test name
Test status
Simulation time 5439613500 ps
CPU time 351.18 seconds
Started Feb 18 02:50:27 PM PST 24
Finished Feb 18 02:56:20 PM PST 24
Peak memory 260636 kb
Host smart-d2375182-5477-408b-b79e-aa711c149bf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607048067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2607048067
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.2437297975
Short name T962
Test name
Test status
Simulation time 68057200 ps
CPU time 13.83 seconds
Started Feb 18 02:50:40 PM PST 24
Finished Feb 18 02:50:56 PM PST 24
Peak memory 264308 kb
Host smart-864d1de8-c2ba-414c-b3b1-655e8abad97c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437297975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.2437297975
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.740134927
Short name T874
Test name
Test status
Simulation time 3248870800 ps
CPU time 1444.39 seconds
Started Feb 18 02:50:28 PM PST 24
Finished Feb 18 03:14:34 PM PST 24
Peak memory 286612 kb
Host smart-5cf8bfae-308e-4d2b-960a-42a3cc800382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740134927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.740134927
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.3515666640
Short name T997
Test name
Test status
Simulation time 946489300 ps
CPU time 112.6 seconds
Started Feb 18 02:50:40 PM PST 24
Finished Feb 18 02:52:35 PM PST 24
Peak memory 280876 kb
Host smart-4105b4e1-6b06-4bdc-99a7-ac17e8c9ed90
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515666640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_ro.3515666640
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.3058486705
Short name T498
Test name
Test status
Simulation time 6003500600 ps
CPU time 527.6 seconds
Started Feb 18 02:50:40 PM PST 24
Finished Feb 18 02:59:30 PM PST 24
Peak memory 313492 kb
Host smart-ac0c1439-cf93-43ff-ab78-5d65a5ac1cf8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058486705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw.3058486705
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.3008835666
Short name T920
Test name
Test status
Simulation time 153486900 ps
CPU time 33.64 seconds
Started Feb 18 02:50:42 PM PST 24
Finished Feb 18 02:51:17 PM PST 24
Peak memory 277332 kb
Host smart-b624c653-9024-4757-9e41-d5ab906ea486
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008835666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.3008835666
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.4158039838
Short name T534
Test name
Test status
Simulation time 80924700 ps
CPU time 30.56 seconds
Started Feb 18 02:50:40 PM PST 24
Finished Feb 18 02:51:13 PM PST 24
Peak memory 265464 kb
Host smart-51408495-52d1-4a2c-870d-64b9fe933f82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158039838 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.4158039838
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.1841055085
Short name T621
Test name
Test status
Simulation time 860912400 ps
CPU time 68.88 seconds
Started Feb 18 02:50:55 PM PST 24
Finished Feb 18 02:52:04 PM PST 24
Peak memory 258632 kb
Host smart-fd1af22b-5fd3-401e-9e62-2f47578d9156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841055085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.1841055085
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.2243166146
Short name T949
Test name
Test status
Simulation time 44817400 ps
CPU time 123.45 seconds
Started Feb 18 02:50:27 PM PST 24
Finished Feb 18 02:52:32 PM PST 24
Peak memory 276564 kb
Host smart-beaddc66-1d8e-4043-8069-6747c4e0e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243166146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2243166146
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.1330018370
Short name T975
Test name
Test status
Simulation time 2649220300 ps
CPU time 216.83 seconds
Started Feb 18 02:50:38 PM PST 24
Finished Feb 18 02:54:16 PM PST 24
Peak memory 264304 kb
Host smart-8abc3ea9-8121-4767-95fd-0662b71514c1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330018370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.flash_ctrl_wo.1330018370
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.579227191
Short name T685
Test name
Test status
Simulation time 49273900 ps
CPU time 13.57 seconds
Started Feb 18 02:51:19 PM PST 24
Finished Feb 18 02:51:33 PM PST 24
Peak memory 263732 kb
Host smart-8cb1a7c9-28a5-46a0-b6c0-701226d168c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579227191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.579227191
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.899928752
Short name T711
Test name
Test status
Simulation time 19811900 ps
CPU time 13.61 seconds
Started Feb 18 02:51:08 PM PST 24
Finished Feb 18 02:51:26 PM PST 24
Peak memory 273696 kb
Host smart-b9ed190a-3b06-4545-94e3-49de0bc2c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899928752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.899928752
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2053624366
Short name T98
Test name
Test status
Simulation time 10042755300 ps
CPU time 49.88 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 02:52:05 PM PST 24
Peak memory 263796 kb
Host smart-1b501e3d-e097-4c2e-ae2e-172e434efd1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053624366 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2053624366
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1320137495
Short name T881
Test name
Test status
Simulation time 14978400 ps
CPU time 13.4 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 02:51:28 PM PST 24
Peak memory 264256 kb
Host smart-feccf4ee-b50c-42b7-bca7-aea6e919113c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320137495 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.1320137495
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2235817497
Short name T597
Test name
Test status
Simulation time 7168866300 ps
CPU time 157.9 seconds
Started Feb 18 02:51:09 PM PST 24
Finished Feb 18 02:53:52 PM PST 24
Peak memory 261196 kb
Host smart-f5dc2b42-c0c5-49c6-a11d-6f1bc0cedfaa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235817497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2235817497
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.2806873801
Short name T244
Test name
Test status
Simulation time 2339745200 ps
CPU time 166.01 seconds
Started Feb 18 02:51:08 PM PST 24
Finished Feb 18 02:53:56 PM PST 24
Peak memory 292116 kb
Host smart-0781120c-2390-42b4-98b2-57782ac6a9e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806873801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.2806873801
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1397774637
Short name T617
Test name
Test status
Simulation time 8548591400 ps
CPU time 236.26 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 02:55:10 PM PST 24
Peak memory 283556 kb
Host smart-5d93fd8b-0426-46df-9aee-a7669b1ec1c8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397774637 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1397774637
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1904924122
Short name T474
Test name
Test status
Simulation time 3288564900 ps
CPU time 66.83 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 02:52:22 PM PST 24
Peak memory 258924 kb
Host smart-52b2a77e-a04b-47aa-a498-70d57d8b8348
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904924122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
904924122
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.294832921
Short name T872
Test name
Test status
Simulation time 46385100 ps
CPU time 13.42 seconds
Started Feb 18 02:51:17 PM PST 24
Finished Feb 18 02:51:31 PM PST 24
Peak memory 264272 kb
Host smart-51a7ce28-fe05-44fa-a012-fab3e4697450
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294832921 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.294832921
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.3637049499
Short name T137
Test name
Test status
Simulation time 39676825300 ps
CPU time 295.54 seconds
Started Feb 18 02:51:06 PM PST 24
Finished Feb 18 02:56:03 PM PST 24
Peak memory 272464 kb
Host smart-2474fd18-a742-4907-b811-27a03e05e241
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637049499 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.3637049499
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.3792700366
Short name T87
Test name
Test status
Simulation time 81888300 ps
CPU time 136.92 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 02:53:31 PM PST 24
Peak memory 258684 kb
Host smart-42a4bee6-b388-4751-bc80-9bf7cec12626
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792700366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.3792700366
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.2681358470
Short name T608
Test name
Test status
Simulation time 1575750800 ps
CPU time 537.48 seconds
Started Feb 18 02:51:05 PM PST 24
Finished Feb 18 03:00:04 PM PST 24
Peak memory 261416 kb
Host smart-066543d5-8d3f-41df-bd64-b056eb817a13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2681358470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.2681358470
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.255230025
Short name T797
Test name
Test status
Simulation time 18640600 ps
CPU time 13.49 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 02:51:28 PM PST 24
Peak memory 264308 kb
Host smart-7096b5c9-97ba-44f0-99c9-b178d688ab2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255230025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_res
et.255230025
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.3138058641
Short name T570
Test name
Test status
Simulation time 29015200 ps
CPU time 81.44 seconds
Started Feb 18 02:51:09 PM PST 24
Finished Feb 18 02:52:34 PM PST 24
Peak memory 267176 kb
Host smart-7745d977-3665-4a10-861d-3bb639e6ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138058641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3138058641
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.1075604123
Short name T456
Test name
Test status
Simulation time 92039300 ps
CPU time 36.45 seconds
Started Feb 18 02:51:17 PM PST 24
Finished Feb 18 02:51:55 PM PST 24
Peak memory 272656 kb
Host smart-4b5da18e-238e-46da-b65d-42bb1e817a21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075604123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.1075604123
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.3619206635
Short name T5
Test name
Test status
Simulation time 501694800 ps
CPU time 112.13 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 02:53:06 PM PST 24
Peak memory 280536 kb
Host smart-7d0e9cad-6bd6-444d-bf76-f44de1ab3d62
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619206635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_ro.3619206635
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.4069494936
Short name T561
Test name
Test status
Simulation time 7107094200 ps
CPU time 541.18 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 03:00:16 PM PST 24
Peak memory 313536 kb
Host smart-b84ac593-5721-4c31-9c84-71607d1721c5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069494936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_rw.4069494936
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.1093771913
Short name T935
Test name
Test status
Simulation time 724244600 ps
CPU time 34.69 seconds
Started Feb 18 02:51:09 PM PST 24
Finished Feb 18 02:51:47 PM PST 24
Peak memory 277340 kb
Host smart-fa0adb24-0fc7-4299-b854-4042c69c8a4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093771913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.1093771913
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.2386321374
Short name T683
Test name
Test status
Simulation time 33870000 ps
CPU time 32.1 seconds
Started Feb 18 02:51:10 PM PST 24
Finished Feb 18 02:51:46 PM PST 24
Peak memory 275968 kb
Host smart-1b685868-8bcc-4ce3-bb9b-5f87a3949248
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386321374 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.2386321374
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.482182626
Short name T638
Test name
Test status
Simulation time 79998000 ps
CPU time 76.04 seconds
Started Feb 18 02:51:05 PM PST 24
Finished Feb 18 02:52:23 PM PST 24
Peak memory 273788 kb
Host smart-38fe77a2-bb21-47c4-a7d6-188f87b70757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482182626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.482182626
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.1775036133
Short name T895
Test name
Test status
Simulation time 5042711800 ps
CPU time 200.52 seconds
Started Feb 18 02:51:06 PM PST 24
Finished Feb 18 02:54:28 PM PST 24
Peak memory 264364 kb
Host smart-dfebc341-a2ac-4165-a574-c674adc45a46
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775036133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.flash_ctrl_wo.1775036133
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.2159875262
Short name T914
Test name
Test status
Simulation time 43259600 ps
CPU time 13.55 seconds
Started Feb 18 02:51:27 PM PST 24
Finished Feb 18 02:51:41 PM PST 24
Peak memory 263704 kb
Host smart-9273d154-801f-4e39-a3d0-9c6d3891f1f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159875262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
2159875262
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1846325675
Short name T924
Test name
Test status
Simulation time 55006200 ps
CPU time 15.81 seconds
Started Feb 18 02:51:29 PM PST 24
Finished Feb 18 02:51:47 PM PST 24
Peak memory 274860 kb
Host smart-1e920b25-80c7-4e4f-ac46-dc4e20ff0cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846325675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1846325675
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1402807806
Short name T1001
Test name
Test status
Simulation time 10013377300 ps
CPU time 129.49 seconds
Started Feb 18 02:51:27 PM PST 24
Finished Feb 18 02:53:37 PM PST 24
Peak memory 358812 kb
Host smart-321872bd-38ec-491b-8da4-42ddfeee4419
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402807806 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.1402807806
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3616938678
Short name T769
Test name
Test status
Simulation time 15938100 ps
CPU time 13.44 seconds
Started Feb 18 02:51:27 PM PST 24
Finished Feb 18 02:51:41 PM PST 24
Peak memory 264300 kb
Host smart-1462900c-c103-49bd-a850-0c15bca49a9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616938678 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.3616938678
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.430370130
Short name T117
Test name
Test status
Simulation time 80143424800 ps
CPU time 816.52 seconds
Started Feb 18 02:51:19 PM PST 24
Finished Feb 18 03:04:56 PM PST 24
Peak memory 262092 kb
Host smart-cf998536-fac5-40fe-bb27-f347f2f3d04d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430370130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.flash_ctrl_hw_rma_reset.430370130
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.3513805737
Short name T535
Test name
Test status
Simulation time 14643071000 ps
CPU time 121.64 seconds
Started Feb 18 02:51:18 PM PST 24
Finished Feb 18 02:53:21 PM PST 24
Peak memory 258144 kb
Host smart-9ced7006-58e3-454f-a32b-f25c9e85165b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513805737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.3513805737
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2860435492
Short name T546
Test name
Test status
Simulation time 39701543000 ps
CPU time 260.97 seconds
Started Feb 18 02:51:19 PM PST 24
Finished Feb 18 02:55:41 PM PST 24
Peak memory 283892 kb
Host smart-b802bc08-8e85-4005-b8c2-ee05464051ad
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860435492 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2860435492
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.2863627518
Short name T966
Test name
Test status
Simulation time 9843474700 ps
CPU time 102.07 seconds
Started Feb 18 02:51:20 PM PST 24
Finished Feb 18 02:53:03 PM PST 24
Peak memory 259616 kb
Host smart-0773c415-749e-4d35-8f27-81caed29b517
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863627518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.2
863627518
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.2153841424
Short name T624
Test name
Test status
Simulation time 18978800 ps
CPU time 13.62 seconds
Started Feb 18 02:51:26 PM PST 24
Finished Feb 18 02:51:41 PM PST 24
Peak memory 264320 kb
Host smart-09d9d180-e9b1-4d56-a950-26a495077700
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153841424 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.2153841424
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.979921675
Short name T23
Test name
Test status
Simulation time 13779933500 ps
CPU time 366.21 seconds
Started Feb 18 02:51:19 PM PST 24
Finished Feb 18 02:57:26 PM PST 24
Peak memory 272548 kb
Host smart-9545140d-6d4e-415d-b1c0-50afb9449ab6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979921675 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_mp_regions.979921675
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.603841897
Short name T955
Test name
Test status
Simulation time 39168200 ps
CPU time 113.58 seconds
Started Feb 18 02:51:19 PM PST 24
Finished Feb 18 02:53:13 PM PST 24
Peak memory 258588 kb
Host smart-6776b789-dba1-4ab7-bb01-473c76f92c30
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603841897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot
p_reset.603841897
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.920195321
Short name T739
Test name
Test status
Simulation time 4512103300 ps
CPU time 387 seconds
Started Feb 18 02:51:18 PM PST 24
Finished Feb 18 02:57:45 PM PST 24
Peak memory 264264 kb
Host smart-cfda136b-4386-41bf-9ce3-14780b9c1197
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920195321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.920195321
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.2760406739
Short name T635
Test name
Test status
Simulation time 31919800 ps
CPU time 13.79 seconds
Started Feb 18 02:51:21 PM PST 24
Finished Feb 18 02:51:35 PM PST 24
Peak memory 264348 kb
Host smart-c080cc93-7607-40e5-86c0-99dc9f2009c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760406739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.2760406739
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.981365353
Short name T1004
Test name
Test status
Simulation time 267477300 ps
CPU time 543.73 seconds
Started Feb 18 02:51:13 PM PST 24
Finished Feb 18 03:00:21 PM PST 24
Peak memory 280764 kb
Host smart-9cc3ace9-526a-45c7-9c3f-2b9de14d05e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981365353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.981365353
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.33496757
Short name T1024
Test name
Test status
Simulation time 205968900 ps
CPU time 35.03 seconds
Started Feb 18 02:51:21 PM PST 24
Finished Feb 18 02:51:56 PM PST 24
Peak memory 272720 kb
Host smart-767ac6cf-cebd-4a22-b331-999fe3a93640
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33496757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flas
h_ctrl_re_evict.33496757
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.1763716890
Short name T413
Test name
Test status
Simulation time 2514714500 ps
CPU time 112.98 seconds
Started Feb 18 02:51:21 PM PST 24
Finished Feb 18 02:53:15 PM PST 24
Peak memory 280832 kb
Host smart-e5faefc8-7eee-4167-9c7c-6bede84095be
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763716890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_ro.1763716890
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.422835938
Short name T126
Test name
Test status
Simulation time 6093105000 ps
CPU time 494.1 seconds
Started Feb 18 02:51:22 PM PST 24
Finished Feb 18 02:59:37 PM PST 24
Peak memory 312680 kb
Host smart-93b5a33e-4689-4e24-9256-ad0e151728fd
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422835938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ct
rl_rw.422835938
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.344983892
Short name T630
Test name
Test status
Simulation time 71045300 ps
CPU time 31.21 seconds
Started Feb 18 02:51:19 PM PST 24
Finished Feb 18 02:51:52 PM PST 24
Peak memory 265508 kb
Host smart-4e7ab859-068a-444f-9f35-a153fbe7f57d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344983892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_rw_evict.344983892
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.508214823
Short name T415
Test name
Test status
Simulation time 29038900 ps
CPU time 30.65 seconds
Started Feb 18 02:51:19 PM PST 24
Finished Feb 18 02:51:50 PM PST 24
Peak memory 273724 kb
Host smart-93f8b583-dadb-44fe-8a06-0c143dbac329
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508214823 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.508214823
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.3967321459
Short name T1029
Test name
Test status
Simulation time 1639301800 ps
CPU time 71.75 seconds
Started Feb 18 02:51:26 PM PST 24
Finished Feb 18 02:52:39 PM PST 24
Peak memory 263364 kb
Host smart-d7e99833-8492-47d0-8d67-76110dac0b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967321459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3967321459
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.2882794971
Short name T828
Test name
Test status
Simulation time 19942700 ps
CPU time 99.45 seconds
Started Feb 18 02:51:12 PM PST 24
Finished Feb 18 02:52:55 PM PST 24
Peak memory 275124 kb
Host smart-4b4c75d4-83f5-45d2-9792-01be254c7c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882794971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2882794971
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.3634140917
Short name T533
Test name
Test status
Simulation time 1884042900 ps
CPU time 161.23 seconds
Started Feb 18 02:51:20 PM PST 24
Finished Feb 18 02:54:02 PM PST 24
Peak memory 264336 kb
Host smart-076c956d-f15a-4aff-8896-ca14792045c9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634140917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.flash_ctrl_wo.3634140917
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.2698657520
Short name T167
Test name
Test status
Simulation time 104331700 ps
CPU time 14.18 seconds
Started Feb 18 02:52:01 PM PST 24
Finished Feb 18 02:52:16 PM PST 24
Peak memory 264188 kb
Host smart-cf8854f3-2191-477a-a54c-cb2df329be4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698657520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
2698657520
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.1186040587
Short name T596
Test name
Test status
Simulation time 15015300 ps
CPU time 16.33 seconds
Started Feb 18 02:51:51 PM PST 24
Finished Feb 18 02:52:09 PM PST 24
Peak memory 274812 kb
Host smart-f44e478f-dd4d-4559-8917-5e880ad94d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186040587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1186040587
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.3692129558
Short name T660
Test name
Test status
Simulation time 10541800 ps
CPU time 21.92 seconds
Started Feb 18 02:51:43 PM PST 24
Finished Feb 18 02:52:06 PM PST 24
Peak memory 279704 kb
Host smart-4da1f069-0876-4cde-a008-5b5268646ea7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692129558 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.3692129558
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2359861346
Short name T940
Test name
Test status
Simulation time 46308200 ps
CPU time 13.74 seconds
Started Feb 18 02:51:59 PM PST 24
Finished Feb 18 02:52:14 PM PST 24
Peak memory 263580 kb
Host smart-e8be7c71-e44b-4dae-9649-b730a91c7a3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359861346 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2359861346
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1965918376
Short name T861
Test name
Test status
Simulation time 40125225100 ps
CPU time 759.51 seconds
Started Feb 18 02:51:34 PM PST 24
Finished Feb 18 03:04:16 PM PST 24
Peak memory 258168 kb
Host smart-23c22805-c699-496e-99f0-9d385a159ebb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965918376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.1965918376
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3603233038
Short name T410
Test name
Test status
Simulation time 5066282600 ps
CPU time 132.8 seconds
Started Feb 18 02:51:34 PM PST 24
Finished Feb 18 02:53:50 PM PST 24
Peak memory 258192 kb
Host smart-c14590de-57da-40cf-b0dd-6eb99b24baeb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603233038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.3603233038
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.209327605
Short name T1046
Test name
Test status
Simulation time 5134184100 ps
CPU time 175.09 seconds
Started Feb 18 02:51:53 PM PST 24
Finished Feb 18 02:54:50 PM PST 24
Peak memory 283940 kb
Host smart-c2fffd8c-7740-4427-bfe2-25d5f4fd979f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209327605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas
h_ctrl_intr_rd.209327605
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2862096963
Short name T539
Test name
Test status
Simulation time 52492028200 ps
CPU time 193.79 seconds
Started Feb 18 02:51:54 PM PST 24
Finished Feb 18 02:55:09 PM PST 24
Peak memory 283940 kb
Host smart-28548989-0063-4d2d-93a8-9554a172a2ed
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862096963 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2862096963
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.117948740
Short name T495
Test name
Test status
Simulation time 3397980800 ps
CPU time 72.64 seconds
Started Feb 18 02:51:33 PM PST 24
Finished Feb 18 02:52:49 PM PST 24
Peak memory 259624 kb
Host smart-5dabfb8f-f6a5-4c31-8183-f1f11ae07789
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117948740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.117948740
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.75045692
Short name T148
Test name
Test status
Simulation time 53382354000 ps
CPU time 349.11 seconds
Started Feb 18 02:51:32 PM PST 24
Finished Feb 18 02:57:23 PM PST 24
Peak memory 272120 kb
Host smart-b7eaae15-ef05-4077-9b20-4e8648dd3599
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75045692 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_mp_regions.75045692
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.759840873
Short name T667
Test name
Test status
Simulation time 157752800 ps
CPU time 390.14 seconds
Started Feb 18 02:51:32 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 264288 kb
Host smart-fddfed38-3fed-4f8b-aa9f-9f07b0dbaad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759840873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.759840873
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.2762013700
Short name T400
Test name
Test status
Simulation time 74574100 ps
CPU time 13.78 seconds
Started Feb 18 02:51:53 PM PST 24
Finished Feb 18 02:52:08 PM PST 24
Peak memory 264320 kb
Host smart-dc19d6df-05e0-4dfe-9744-ea31bda3982b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762013700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.2762013700
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.1904180641
Short name T155
Test name
Test status
Simulation time 512727300 ps
CPU time 1010.79 seconds
Started Feb 18 02:51:28 PM PST 24
Finished Feb 18 03:08:21 PM PST 24
Peak memory 286412 kb
Host smart-6675b576-86fa-44c0-b52d-5ab6ebbf6b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904180641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1904180641
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.4171767143
Short name T584
Test name
Test status
Simulation time 295945700 ps
CPU time 37 seconds
Started Feb 18 02:51:51 PM PST 24
Finished Feb 18 02:52:28 PM PST 24
Peak memory 271544 kb
Host smart-17bda9f2-4600-4a9d-97f2-a66b22440b40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171767143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.4171767143
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.3564568928
Short name T447
Test name
Test status
Simulation time 770582400 ps
CPU time 120.15 seconds
Started Feb 18 02:51:51 PM PST 24
Finished Feb 18 02:53:52 PM PST 24
Peak memory 280860 kb
Host smart-c2ae71b5-1ac3-48fb-b118-090a191ea324
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564568928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_ro.3564568928
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.3056061852
Short name T408
Test name
Test status
Simulation time 9148837400 ps
CPU time 604.8 seconds
Started Feb 18 02:51:47 PM PST 24
Finished Feb 18 03:01:53 PM PST 24
Peak memory 313488 kb
Host smart-1617eefe-7bb2-4eca-88cc-e161241b3246
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056061852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw.3056061852
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.2798126577
Short name T449
Test name
Test status
Simulation time 29972800 ps
CPU time 31.87 seconds
Started Feb 18 02:52:02 PM PST 24
Finished Feb 18 02:52:35 PM PST 24
Peak memory 273796 kb
Host smart-b7be5d8b-dd5f-497d-a870-0576038a2a7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798126577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.2798126577
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2026457221
Short name T851
Test name
Test status
Simulation time 84639200 ps
CPU time 28.89 seconds
Started Feb 18 02:51:54 PM PST 24
Finished Feb 18 02:52:24 PM PST 24
Peak memory 265472 kb
Host smart-9eb8dcf0-d3b6-41c2-8456-9efe705c07dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026457221 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2026457221
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3442898711
Short name T1050
Test name
Test status
Simulation time 3003819900 ps
CPU time 70.8 seconds
Started Feb 18 02:51:54 PM PST 24
Finished Feb 18 02:53:06 PM PST 24
Peak memory 258688 kb
Host smart-f1408b3f-a4b9-4fc6-bbe2-df8945fb4d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442898711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3442898711
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.1712718177
Short name T430
Test name
Test status
Simulation time 20440400 ps
CPU time 52.53 seconds
Started Feb 18 02:51:27 PM PST 24
Finished Feb 18 02:52:20 PM PST 24
Peak memory 269516 kb
Host smart-651b13ed-f435-4508-8b90-cf27f4132eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712718177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1712718177
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.2015557349
Short name T662
Test name
Test status
Simulation time 3728977000 ps
CPU time 140.02 seconds
Started Feb 18 02:51:46 PM PST 24
Finished Feb 18 02:54:06 PM PST 24
Peak memory 264376 kb
Host smart-d0fb0f89-0cce-4a3e-b04f-62eca10b9337
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015557349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.flash_ctrl_wo.2015557349
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.575254624
Short name T384
Test name
Test status
Simulation time 169703400 ps
CPU time 14.12 seconds
Started Feb 18 02:52:06 PM PST 24
Finished Feb 18 02:52:21 PM PST 24
Peak memory 263880 kb
Host smart-e3936927-8c15-4c1f-99c6-7e857e2a5e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575254624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.575254624
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.1390837383
Short name T759
Test name
Test status
Simulation time 46085500 ps
CPU time 13.25 seconds
Started Feb 18 02:52:04 PM PST 24
Finished Feb 18 02:52:19 PM PST 24
Peak memory 283068 kb
Host smart-da4bc610-711c-4468-9a00-89f44b47954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390837383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1390837383
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.2656856893
Short name T109
Test name
Test status
Simulation time 10341100 ps
CPU time 22.13 seconds
Started Feb 18 02:52:01 PM PST 24
Finished Feb 18 02:52:24 PM PST 24
Peak memory 279756 kb
Host smart-486c0585-26a8-4746-8cb9-0b64ffcb998b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656856893 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.2656856893
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2352731127
Short name T672
Test name
Test status
Simulation time 10107379400 ps
CPU time 36.9 seconds
Started Feb 18 02:52:06 PM PST 24
Finished Feb 18 02:52:46 PM PST 24
Peak memory 264396 kb
Host smart-cff35df4-a03d-4e37-85c1-4378eee4d250
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352731127 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.2352731127
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.1323272453
Short name T1056
Test name
Test status
Simulation time 15537900 ps
CPU time 13.33 seconds
Started Feb 18 02:52:12 PM PST 24
Finished Feb 18 02:52:27 PM PST 24
Peak memory 263476 kb
Host smart-92c8c50b-5e6a-4175-a406-2533daacc33c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323272453 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.1323272453
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.4139795665
Short name T978
Test name
Test status
Simulation time 8543498600 ps
CPU time 97.86 seconds
Started Feb 18 02:51:56 PM PST 24
Finished Feb 18 02:53:35 PM PST 24
Peak memory 258200 kb
Host smart-83c791cb-70a5-4d39-afd2-176d515534dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139795665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.4139795665
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.3892552830
Short name T734
Test name
Test status
Simulation time 1419341800 ps
CPU time 154.55 seconds
Started Feb 18 02:52:00 PM PST 24
Finished Feb 18 02:54:36 PM PST 24
Peak memory 283928 kb
Host smart-a7670367-c3bc-4d96-bba8-22b91a3a7880
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892552830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.3892552830
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.3876717780
Short name T863
Test name
Test status
Simulation time 9512489200 ps
CPU time 204.65 seconds
Started Feb 18 02:52:01 PM PST 24
Finished Feb 18 02:55:27 PM PST 24
Peak memory 283708 kb
Host smart-9e891155-7d45-482e-abe7-a01089ec09f9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876717780 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.3876717780
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.89716592
Short name T156
Test name
Test status
Simulation time 12619256900 ps
CPU time 73.34 seconds
Started Feb 18 02:51:54 PM PST 24
Finished Feb 18 02:53:09 PM PST 24
Peak memory 259624 kb
Host smart-b2d626dd-d9b3-4b38-88f7-616a013007c3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89716592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.89716592
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.3166362649
Short name T282
Test name
Test status
Simulation time 15696900 ps
CPU time 13.43 seconds
Started Feb 18 02:52:04 PM PST 24
Finished Feb 18 02:52:19 PM PST 24
Peak memory 264340 kb
Host smart-5721c72f-4952-45e3-a551-94c57d1b7612
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166362649 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.3166362649
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.687852542
Short name T150
Test name
Test status
Simulation time 6542540600 ps
CPU time 518.21 seconds
Started Feb 18 02:52:00 PM PST 24
Finished Feb 18 03:00:38 PM PST 24
Peak memory 272232 kb
Host smart-e374aa2c-ec3d-4e57-a8d5-0101fed3290e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687852542 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_mp_regions.687852542
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.2476246354
Short name T1057
Test name
Test status
Simulation time 72372200 ps
CPU time 136.59 seconds
Started Feb 18 02:51:56 PM PST 24
Finished Feb 18 02:54:14 PM PST 24
Peak memory 258656 kb
Host smart-600f7c3d-e23b-4e61-a25a-8cddd94babb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476246354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.2476246354
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1995342763
Short name T991
Test name
Test status
Simulation time 1437967400 ps
CPU time 450.46 seconds
Started Feb 18 02:52:07 PM PST 24
Finished Feb 18 02:59:40 PM PST 24
Peak memory 261280 kb
Host smart-79f7116a-20a2-47dc-8859-cc587ceb58e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995342763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1995342763
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.3079412157
Short name T1061
Test name
Test status
Simulation time 20506400 ps
CPU time 13.7 seconds
Started Feb 18 02:52:00 PM PST 24
Finished Feb 18 02:52:14 PM PST 24
Peak memory 264332 kb
Host smart-528f8520-38d2-457d-a0bf-ccba4bf54593
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079412157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.3079412157
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.2056739973
Short name T138
Test name
Test status
Simulation time 3195488900 ps
CPU time 713 seconds
Started Feb 18 02:51:53 PM PST 24
Finished Feb 18 03:03:48 PM PST 24
Peak memory 283740 kb
Host smart-a7cedf3a-f0e6-4282-a479-247ff99e6bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056739973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2056739973
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.2621828785
Short name T793
Test name
Test status
Simulation time 625897200 ps
CPU time 96.96 seconds
Started Feb 18 02:51:59 PM PST 24
Finished Feb 18 02:53:37 PM PST 24
Peak memory 280856 kb
Host smart-56c941ca-c70e-45a2-95ae-b578f488e168
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621828785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_ro.2621828785
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.3012819394
Short name T1009
Test name
Test status
Simulation time 3274136700 ps
CPU time 620.19 seconds
Started Feb 18 02:52:00 PM PST 24
Finished Feb 18 03:02:21 PM PST 24
Peak memory 313572 kb
Host smart-0dc5e992-ee50-4d69-b39b-3074bfbe5c53
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012819394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw.3012819394
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.2318557215
Short name T664
Test name
Test status
Simulation time 38116000 ps
CPU time 31.58 seconds
Started Feb 18 02:52:02 PM PST 24
Finished Feb 18 02:52:34 PM PST 24
Peak memory 273700 kb
Host smart-06419e28-a987-46a1-99b2-0fec4b68f46a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318557215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.2318557215
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2814689347
Short name T545
Test name
Test status
Simulation time 33952500 ps
CPU time 31.2 seconds
Started Feb 18 02:52:00 PM PST 24
Finished Feb 18 02:52:32 PM PST 24
Peak memory 272740 kb
Host smart-c5164802-e6c9-4f84-b38e-caeabb63ce8c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814689347 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2814689347
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.3456778972
Short name T564
Test name
Test status
Simulation time 22013700 ps
CPU time 49.65 seconds
Started Feb 18 02:52:07 PM PST 24
Finished Feb 18 02:52:59 PM PST 24
Peak memory 269364 kb
Host smart-7636a041-dc1a-4f96-8020-1f6aaf4ca111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456778972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.3456778972
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.2932579278
Short name T491
Test name
Test status
Simulation time 4596005200 ps
CPU time 194.38 seconds
Started Feb 18 02:52:00 PM PST 24
Finished Feb 18 02:55:15 PM PST 24
Peak memory 264368 kb
Host smart-ed8ee6b2-cec1-4746-b5db-1446a8c8022b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932579278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.flash_ctrl_wo.2932579278
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3192844059
Short name T771
Test name
Test status
Simulation time 91166400 ps
CPU time 13.87 seconds
Started Feb 18 02:52:19 PM PST 24
Finished Feb 18 02:52:34 PM PST 24
Peak memory 263936 kb
Host smart-19c93a07-305b-41e1-9bcd-b7a98f8c3b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192844059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3192844059
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.4188878146
Short name T518
Test name
Test status
Simulation time 15006500 ps
CPU time 15.83 seconds
Started Feb 18 02:52:17 PM PST 24
Finished Feb 18 02:52:35 PM PST 24
Peak memory 274040 kb
Host smart-18a53e54-f73d-48b7-8311-1b616b3f13b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188878146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.4188878146
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3386572461
Short name T847
Test name
Test status
Simulation time 10019843600 ps
CPU time 72.23 seconds
Started Feb 18 02:52:19 PM PST 24
Finished Feb 18 02:53:32 PM PST 24
Peak memory 279404 kb
Host smart-35b6d0ff-dab0-474a-b453-2a3e9377c342
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386572461 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3386572461
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2582783134
Short name T286
Test name
Test status
Simulation time 6307062300 ps
CPU time 103.51 seconds
Started Feb 18 02:52:05 PM PST 24
Finished Feb 18 02:53:50 PM PST 24
Peak memory 258276 kb
Host smart-f78cf01c-7f24-489e-8945-47727e9a4cfe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582783134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2582783134
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.442666175
Short name T1013
Test name
Test status
Simulation time 5303444600 ps
CPU time 178.97 seconds
Started Feb 18 02:52:12 PM PST 24
Finished Feb 18 02:55:12 PM PST 24
Peak memory 291864 kb
Host smart-c988e263-05fd-47f5-8e6e-af161e858a2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442666175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flas
h_ctrl_intr_rd.442666175
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.2193800897
Short name T1017
Test name
Test status
Simulation time 18750590400 ps
CPU time 191.82 seconds
Started Feb 18 02:52:12 PM PST 24
Finished Feb 18 02:55:25 PM PST 24
Peak memory 290024 kb
Host smart-3c5e6446-7a1a-4f3a-9dc2-66bcb9258982
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193800897 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.2193800897
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.430847882
Short name T201
Test name
Test status
Simulation time 2186858400 ps
CPU time 66.55 seconds
Started Feb 18 02:52:11 PM PST 24
Finished Feb 18 02:53:19 PM PST 24
Peak memory 259496 kb
Host smart-0136ef7f-c8d6-4ad8-acfa-cb6ad9197992
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430847882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.430847882
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.4130437241
Short name T629
Test name
Test status
Simulation time 15411700 ps
CPU time 14.12 seconds
Started Feb 18 02:52:20 PM PST 24
Finished Feb 18 02:52:35 PM PST 24
Peak memory 264200 kb
Host smart-8ebb3afc-8e69-4a22-b7e4-107ffdeedd28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130437241 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.4130437241
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.1828290654
Short name T466
Test name
Test status
Simulation time 4387267100 ps
CPU time 183.82 seconds
Started Feb 18 02:52:10 PM PST 24
Finished Feb 18 02:55:16 PM PST 24
Peak memory 260364 kb
Host smart-e84b1891-90a6-4537-80fc-9d0bdac5b5c4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828290654 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.1828290654
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.2567426200
Short name T128
Test name
Test status
Simulation time 175333900 ps
CPU time 198.17 seconds
Started Feb 18 02:52:06 PM PST 24
Finished Feb 18 02:55:27 PM PST 24
Peak memory 260352 kb
Host smart-0d930b70-bdb8-4093-9797-2eb6c4ec81b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567426200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2567426200
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.4227623736
Short name T984
Test name
Test status
Simulation time 7214436200 ps
CPU time 273.2 seconds
Started Feb 18 02:52:11 PM PST 24
Finished Feb 18 02:56:45 PM PST 24
Peak memory 264316 kb
Host smart-0e9b5b64-bfdf-484d-87fb-e9a5cd977ad8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227623736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.4227623736
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.1010427494
Short name T742
Test name
Test status
Simulation time 150220200 ps
CPU time 551.71 seconds
Started Feb 18 02:52:07 PM PST 24
Finished Feb 18 03:01:22 PM PST 24
Peak memory 282012 kb
Host smart-c8633b1a-c1db-4e14-a005-4f66fcb53ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010427494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1010427494
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.1900773483
Short name T864
Test name
Test status
Simulation time 104452200 ps
CPU time 34.67 seconds
Started Feb 18 02:52:12 PM PST 24
Finished Feb 18 02:52:48 PM PST 24
Peak memory 273704 kb
Host smart-ddb847ff-9d62-487c-88ab-096669250228
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900773483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.1900773483
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.362627058
Short name T706
Test name
Test status
Simulation time 538661500 ps
CPU time 133.24 seconds
Started Feb 18 02:52:11 PM PST 24
Finished Feb 18 02:54:25 PM PST 24
Peak memory 288256 kb
Host smart-59726774-5d12-493a-86bc-073a912e455c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362627058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.flash_ctrl_ro.362627058
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.3415668789
Short name T655
Test name
Test status
Simulation time 18515306700 ps
CPU time 515.66 seconds
Started Feb 18 02:52:14 PM PST 24
Finished Feb 18 03:00:51 PM PST 24
Peak memory 313520 kb
Host smart-0b57e7e8-52e8-40db-a67e-4baa2b2593ff
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415668789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw.3415668789
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.111335223
Short name T521
Test name
Test status
Simulation time 45760000 ps
CPU time 31.72 seconds
Started Feb 18 02:52:15 PM PST 24
Finished Feb 18 02:52:47 PM PST 24
Peak memory 265504 kb
Host smart-7b7653ff-0426-4071-932d-ab1d607611fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111335223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_rw_evict.111335223
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2293491395
Short name T967
Test name
Test status
Simulation time 75790600 ps
CPU time 31.31 seconds
Started Feb 18 02:52:13 PM PST 24
Finished Feb 18 02:52:45 PM PST 24
Peak memory 273784 kb
Host smart-f712d7b9-6d73-4ad4-9b9b-9c9b6c58164c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293491395 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2293491395
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.1604072590
Short name T411
Test name
Test status
Simulation time 2598240500 ps
CPU time 57.73 seconds
Started Feb 18 02:52:19 PM PST 24
Finished Feb 18 02:53:17 PM PST 24
Peak memory 263344 kb
Host smart-7e076c5c-a3ef-4681-a847-2d14368c21de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604072590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1604072590
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.3533605937
Short name T926
Test name
Test status
Simulation time 38388400 ps
CPU time 98.66 seconds
Started Feb 18 02:52:08 PM PST 24
Finished Feb 18 02:53:49 PM PST 24
Peak memory 275120 kb
Host smart-3ba423c3-9654-40b4-ad81-df4b1ff0dc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533605937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.3533605937
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.2378414385
Short name T636
Test name
Test status
Simulation time 2323829100 ps
CPU time 197.67 seconds
Started Feb 18 02:52:14 PM PST 24
Finished Feb 18 02:55:33 PM PST 24
Peak memory 263732 kb
Host smart-9af2fde6-a479-4d24-b252-645c561ccc7e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378414385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.flash_ctrl_wo.2378414385
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.1245867191
Short name T507
Test name
Test status
Simulation time 71392200 ps
CPU time 13.93 seconds
Started Feb 18 02:52:35 PM PST 24
Finished Feb 18 02:52:50 PM PST 24
Peak memory 264212 kb
Host smart-5ef17e7a-f891-40b7-b7fd-8cc38ce149e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245867191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
1245867191
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.555758508
Short name T618
Test name
Test status
Simulation time 52329300 ps
CPU time 13.33 seconds
Started Feb 18 02:52:33 PM PST 24
Finished Feb 18 02:52:48 PM PST 24
Peak memory 274660 kb
Host smart-9cae00f8-3cfa-4621-adbe-2ebbd923324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555758508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.555758508
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2197325118
Short name T94
Test name
Test status
Simulation time 10012822000 ps
CPU time 298.84 seconds
Started Feb 18 02:52:38 PM PST 24
Finished Feb 18 02:57:38 PM PST 24
Peak memory 323532 kb
Host smart-4780804b-fd60-44fc-8221-11826728d80d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197325118 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2197325118
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.3671415857
Short name T856
Test name
Test status
Simulation time 552257500 ps
CPU time 56.31 seconds
Started Feb 18 02:52:18 PM PST 24
Finished Feb 18 02:53:16 PM PST 24
Peak memory 261292 kb
Host smart-55f4c8ed-e7bd-4e5e-9ef9-6925a13240c6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671415857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.3671415857
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.2684582801
Short name T637
Test name
Test status
Simulation time 1132700800 ps
CPU time 150.94 seconds
Started Feb 18 02:52:28 PM PST 24
Finished Feb 18 02:55:00 PM PST 24
Peak memory 291924 kb
Host smart-84c1f316-59fc-44f4-9469-9ad210aa6278
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684582801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.2684582801
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3076958875
Short name T679
Test name
Test status
Simulation time 7943368600 ps
CPU time 213.62 seconds
Started Feb 18 02:52:29 PM PST 24
Finished Feb 18 02:56:05 PM PST 24
Peak memory 283872 kb
Host smart-1c19f3a1-026a-442b-866b-ed13ace46658
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076958875 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.3076958875
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.4285894019
Short name T814
Test name
Test status
Simulation time 6847952600 ps
CPU time 67.08 seconds
Started Feb 18 02:52:27 PM PST 24
Finished Feb 18 02:53:35 PM PST 24
Peak memory 259444 kb
Host smart-f33225e8-7647-45a1-bf45-90338bd0f431
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285894019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.4
285894019
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.4070354524
Short name T590
Test name
Test status
Simulation time 19517000 ps
CPU time 13.5 seconds
Started Feb 18 02:52:33 PM PST 24
Finished Feb 18 02:52:48 PM PST 24
Peak memory 264328 kb
Host smart-a2f040f3-c08e-4ee2-aeb0-6c875b02b8f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070354524 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.4070354524
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.1511279478
Short name T151
Test name
Test status
Simulation time 15757975900 ps
CPU time 344.96 seconds
Started Feb 18 02:52:23 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 271872 kb
Host smart-738a84f2-03f4-4a74-8534-4c2b6521d9b9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511279478 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.1511279478
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.4061516168
Short name T506
Test name
Test status
Simulation time 8171693700 ps
CPU time 618.27 seconds
Started Feb 18 02:52:19 PM PST 24
Finished Feb 18 03:02:38 PM PST 24
Peak memory 264288 kb
Host smart-7efaf39f-9585-4067-9050-e8a4d4ebb466
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061516168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.4061516168
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.3714056659
Short name T762
Test name
Test status
Simulation time 119994800 ps
CPU time 13.46 seconds
Started Feb 18 02:52:24 PM PST 24
Finished Feb 18 02:52:39 PM PST 24
Peak memory 264356 kb
Host smart-4954b5f7-af57-47f0-a25f-8d27f8591d7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714056659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.3714056659
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1754617467
Short name T1022
Test name
Test status
Simulation time 390243100 ps
CPU time 614.99 seconds
Started Feb 18 02:52:19 PM PST 24
Finished Feb 18 03:02:35 PM PST 24
Peak memory 282212 kb
Host smart-35f9ec6f-0564-4adc-ad0e-d931c36d25b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754617467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1754617467
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.893734131
Short name T1036
Test name
Test status
Simulation time 73297400 ps
CPU time 32.12 seconds
Started Feb 18 02:52:27 PM PST 24
Finished Feb 18 02:53:00 PM PST 24
Peak memory 276512 kb
Host smart-fb6c3bb5-6b30-429b-9b46-36fff703a0cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893734131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_re_evict.893734131
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.637705475
Short name T943
Test name
Test status
Simulation time 2103353900 ps
CPU time 124.6 seconds
Started Feb 18 02:52:33 PM PST 24
Finished Feb 18 02:54:39 PM PST 24
Peak memory 280772 kb
Host smart-f9a3f262-2534-4ae5-ae2c-1f065d93d7b3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637705475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.flash_ctrl_ro.637705475
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.4103922799
Short name T403
Test name
Test status
Simulation time 15628479600 ps
CPU time 556.18 seconds
Started Feb 18 02:52:27 PM PST 24
Finished Feb 18 03:01:45 PM PST 24
Peak memory 313028 kb
Host smart-18e32d74-8981-45fd-964d-2f7ebc31136e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103922799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw.4103922799
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.406644337
Short name T830
Test name
Test status
Simulation time 78002000 ps
CPU time 30.72 seconds
Started Feb 18 02:52:27 PM PST 24
Finished Feb 18 02:52:59 PM PST 24
Peak memory 265580 kb
Host smart-c5e37eaf-41b8-4d6c-a522-e705edf6f5fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406644337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_rw_evict.406644337
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.184509712
Short name T389
Test name
Test status
Simulation time 70704500 ps
CPU time 29.15 seconds
Started Feb 18 02:52:29 PM PST 24
Finished Feb 18 02:53:00 PM PST 24
Peak memory 265500 kb
Host smart-5760d1d0-3556-4348-813d-4092d98fc1e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184509712 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.184509712
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.2747007124
Short name T529
Test name
Test status
Simulation time 38518500 ps
CPU time 172.47 seconds
Started Feb 18 02:52:16 PM PST 24
Finished Feb 18 02:55:09 PM PST 24
Peak memory 275564 kb
Host smart-119ce85f-507e-4892-8c72-79a0aeab30c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747007124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.2747007124
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.3600598202
Short name T134
Test name
Test status
Simulation time 8317815400 ps
CPU time 158.43 seconds
Started Feb 18 02:52:23 PM PST 24
Finished Feb 18 02:55:02 PM PST 24
Peak memory 264312 kb
Host smart-e649b3e1-1be6-467f-9d41-4916f7cfce6a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600598202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.flash_ctrl_wo.3600598202
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2510437453
Short name T993
Test name
Test status
Simulation time 57343700 ps
CPU time 13.95 seconds
Started Feb 18 02:45:32 PM PST 24
Finished Feb 18 02:45:48 PM PST 24
Peak memory 262940 kb
Host smart-2269c148-031e-44bf-b09d-0a0d5a25f71c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510437453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
510437453
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.4135941413
Short name T232
Test name
Test status
Simulation time 38680900 ps
CPU time 13.71 seconds
Started Feb 18 02:45:32 PM PST 24
Finished Feb 18 02:45:47 PM PST 24
Peak memory 264308 kb
Host smart-b9b33193-85e9-416d-8d6e-2e267116db5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135941413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.4135941413
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3027496470
Short name T646
Test name
Test status
Simulation time 27156800 ps
CPU time 14.3 seconds
Started Feb 18 02:45:24 PM PST 24
Finished Feb 18 02:45:42 PM PST 24
Peak memory 274932 kb
Host smart-79b7f454-7f7c-4b6a-a462-d8f6e767b595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027496470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3027496470
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.3347084784
Short name T952
Test name
Test status
Simulation time 504832200 ps
CPU time 108.99 seconds
Started Feb 18 02:45:13 PM PST 24
Finished Feb 18 02:47:04 PM PST 24
Peak memory 280128 kb
Host smart-88eb884b-7e8a-4632-97e6-71dd5c9c5add
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347084784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.3347084784
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.3815697199
Short name T781
Test name
Test status
Simulation time 20504800 ps
CPU time 21.89 seconds
Started Feb 18 02:45:26 PM PST 24
Finished Feb 18 02:45:52 PM PST 24
Peak memory 272792 kb
Host smart-142ede43-f60e-4b1c-aa34-10cb0d797c30
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815697199 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.3815697199
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.3094817052
Short name T62
Test name
Test status
Simulation time 2378979900 ps
CPU time 431.75 seconds
Started Feb 18 02:44:53 PM PST 24
Finished Feb 18 02:52:11 PM PST 24
Peak memory 260232 kb
Host smart-7cdb5951-4c63-4ce5-9a87-3c271cd13a95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094817052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.3094817052
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.1040394543
Short name T665
Test name
Test status
Simulation time 9810770900 ps
CPU time 2334.5 seconds
Started Feb 18 02:45:01 PM PST 24
Finished Feb 18 03:24:01 PM PST 24
Peak memory 263156 kb
Host smart-c4bdbb95-618e-43d4-820a-b4518bcfc8bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040394543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.1040394543
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.533791047
Short name T161
Test name
Test status
Simulation time 2642186500 ps
CPU time 2380.43 seconds
Started Feb 18 02:44:59 PM PST 24
Finished Feb 18 03:24:46 PM PST 24
Peak memory 260680 kb
Host smart-dd78c65f-9440-4695-baec-3a3115f7b832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533791047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.533791047
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.350548654
Short name T1048
Test name
Test status
Simulation time 2705923400 ps
CPU time 783.31 seconds
Started Feb 18 02:45:01 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 264244 kb
Host smart-6298d7f0-f1e9-4db9-89f8-72851a78a990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350548654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.350548654
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.292768281
Short name T865
Test name
Test status
Simulation time 1487529000 ps
CPU time 28.05 seconds
Started Feb 18 02:45:00 PM PST 24
Finished Feb 18 02:45:33 PM PST 24
Peak memory 264276 kb
Host smart-f1f45dd1-704b-4c89-8e38-0013a222ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292768281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.292768281
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.3121344067
Short name T164
Test name
Test status
Simulation time 304353900 ps
CPU time 39.42 seconds
Started Feb 18 02:45:25 PM PST 24
Finished Feb 18 02:46:09 PM PST 24
Peak memory 272624 kb
Host smart-eb095a07-deca-4fa4-9088-5f56452cb9cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121344067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.3121344067
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.2009594058
Short name T800
Test name
Test status
Simulation time 191201677600 ps
CPU time 2775.92 seconds
Started Feb 18 02:45:01 PM PST 24
Finished Feb 18 03:31:22 PM PST 24
Peak memory 263736 kb
Host smart-eb912363-a2ac-41a9-b125-5470d47092f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009594058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.2009594058
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.1480241698
Short name T801
Test name
Test status
Simulation time 322549577900 ps
CPU time 2049.4 seconds
Started Feb 18 02:45:01 PM PST 24
Finished Feb 18 03:19:16 PM PST 24
Peak memory 263816 kb
Host smart-404d2415-2147-4afd-9750-5f42d8558ffb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480241698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.1480241698
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.820176256
Short name T1042
Test name
Test status
Simulation time 10031032500 ps
CPU time 54.96 seconds
Started Feb 18 02:45:33 PM PST 24
Finished Feb 18 02:46:30 PM PST 24
Peak memory 270516 kb
Host smart-98b3d842-53f8-499d-8d13-45764d7c179a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820176256 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.820176256
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2200105958
Short name T67
Test name
Test status
Simulation time 15822400 ps
CPU time 13.91 seconds
Started Feb 18 02:45:32 PM PST 24
Finished Feb 18 02:45:48 PM PST 24
Peak memory 263404 kb
Host smart-49130a06-29d5-4876-8dcf-bf5bbb4283b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200105958 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.2200105958
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.3040522771
Short name T749
Test name
Test status
Simulation time 359292272800 ps
CPU time 1732.48 seconds
Started Feb 18 02:44:53 PM PST 24
Finished Feb 18 03:13:53 PM PST 24
Peak memory 262752 kb
Host smart-e5cb2352-0a83-40ea-982e-c54ef7651b33
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040522771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.3040522771
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3737007280
Short name T113
Test name
Test status
Simulation time 40120276000 ps
CPU time 717.79 seconds
Started Feb 18 02:44:51 PM PST 24
Finished Feb 18 02:56:54 PM PST 24
Peak memory 263280 kb
Host smart-3b2869ed-88d3-476e-88a9-74c64a01aeec
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737007280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.3737007280
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.653760061
Short name T442
Test name
Test status
Simulation time 8478625100 ps
CPU time 127.57 seconds
Started Feb 18 02:44:52 PM PST 24
Finished Feb 18 02:47:06 PM PST 24
Peak memory 258212 kb
Host smart-924e0e24-4112-460d-a645-1033727aeaee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653760061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw
_sec_otp.653760061
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.1733450068
Short name T229
Test name
Test status
Simulation time 4936394300 ps
CPU time 524.79 seconds
Started Feb 18 02:45:19 PM PST 24
Finished Feb 18 02:54:05 PM PST 24
Peak memory 322176 kb
Host smart-95920104-4824-4cbf-b79e-64719cfeba1e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733450068 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.1733450068
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.1327039146
Short name T514
Test name
Test status
Simulation time 4346938200 ps
CPU time 169.13 seconds
Started Feb 18 02:45:19 PM PST 24
Finished Feb 18 02:48:10 PM PST 24
Peak memory 291676 kb
Host smart-95e113c2-4cf6-40a4-95cd-838b2ae988f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327039146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.1327039146
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2240118897
Short name T462
Test name
Test status
Simulation time 16946393500 ps
CPU time 197.39 seconds
Started Feb 18 02:45:18 PM PST 24
Finished Feb 18 02:48:37 PM PST 24
Peak memory 288980 kb
Host smart-020befa6-b9ca-44c0-9c50-7a628c7168d2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240118897 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.2240118897
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.2343163914
Short name T487
Test name
Test status
Simulation time 7327217300 ps
CPU time 91.23 seconds
Started Feb 18 02:45:22 PM PST 24
Finished Feb 18 02:46:56 PM PST 24
Peak memory 264320 kb
Host smart-576a022a-135e-44e5-bb5b-dc40dcc5c050
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343163914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.2343163914
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1692785460
Short name T439
Test name
Test status
Simulation time 90284993700 ps
CPU time 364.13 seconds
Started Feb 18 02:45:19 PM PST 24
Finished Feb 18 02:51:24 PM PST 24
Peak memory 264328 kb
Host smart-dbe36fc8-e65e-444b-a0a0-86c60fea7ba9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169
2785460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1692785460
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.1500292478
Short name T193
Test name
Test status
Simulation time 1956601900 ps
CPU time 78.96 seconds
Started Feb 18 02:45:02 PM PST 24
Finished Feb 18 02:46:26 PM PST 24
Peak memory 259648 kb
Host smart-a6c8a2b1-5102-4e0a-9057-f919e1f8e262
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500292478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.1500292478
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.2171744038
Short name T83
Test name
Test status
Simulation time 27434200 ps
CPU time 13.59 seconds
Started Feb 18 02:45:32 PM PST 24
Finished Feb 18 02:45:47 PM PST 24
Peak memory 264308 kb
Host smart-05847c7f-c386-4e28-aa64-adf06eec2e87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171744038 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.2171744038
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.2134426117
Short name T58
Test name
Test status
Simulation time 1681880200 ps
CPU time 72.1 seconds
Started Feb 18 02:45:05 PM PST 24
Finished Feb 18 02:46:21 PM PST 24
Peak memory 259644 kb
Host smart-a7193660-c38d-4fa7-a69e-387cdf47ae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134426117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2134426117
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.2833226503
Short name T144
Test name
Test status
Simulation time 14326228100 ps
CPU time 179.26 seconds
Started Feb 18 02:45:00 PM PST 24
Finished Feb 18 02:48:05 PM PST 24
Peak memory 261504 kb
Host smart-4485697b-8402-48d4-a345-d11470657051
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833226503 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.2833226503
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.3982784529
Short name T707
Test name
Test status
Simulation time 73422500 ps
CPU time 116.95 seconds
Started Feb 18 02:44:58 PM PST 24
Finished Feb 18 02:47:01 PM PST 24
Peak memory 258804 kb
Host smart-d93dcc5d-5540-4015-9f30-e4de512cf112
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982784529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.3982784529
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.1628022966
Short name T841
Test name
Test status
Simulation time 2983984600 ps
CPU time 201.27 seconds
Started Feb 18 02:45:21 PM PST 24
Finished Feb 18 02:48:43 PM PST 24
Peak memory 293296 kb
Host smart-bb407d1f-4d88-47b7-b082-2fbea8246b74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628022966 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.1628022966
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.705508584
Short name T492
Test name
Test status
Simulation time 451168200 ps
CPU time 69.1 seconds
Started Feb 18 02:44:54 PM PST 24
Finished Feb 18 02:46:10 PM PST 24
Peak memory 264172 kb
Host smart-e133155b-6c4e-410b-b6c0-29b14360a676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705508584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.705508584
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.2473337625
Short name T1007
Test name
Test status
Simulation time 20096100 ps
CPU time 13.49 seconds
Started Feb 18 02:45:24 PM PST 24
Finished Feb 18 02:45:41 PM PST 24
Peak memory 264356 kb
Host smart-b6d88b58-dea0-4b4a-8e71-6a100085b91d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473337625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.2473337625
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.1929171596
Short name T571
Test name
Test status
Simulation time 21031190700 ps
CPU time 652.06 seconds
Started Feb 18 02:44:43 PM PST 24
Finished Feb 18 02:55:39 PM PST 24
Peak memory 283088 kb
Host smart-736347bb-a4f7-43cf-aa48-1bec44825481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929171596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1929171596
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1716664999
Short name T207
Test name
Test status
Simulation time 2796302000 ps
CPU time 152.07 seconds
Started Feb 18 02:44:48 PM PST 24
Finished Feb 18 02:47:25 PM PST 24
Peak memory 264296 kb
Host smart-628c22ad-a386-45e9-a043-17ad6cba852c
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1716664999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1716664999
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.644352010
Short name T1039
Test name
Test status
Simulation time 73073800 ps
CPU time 31.7 seconds
Started Feb 18 02:45:24 PM PST 24
Finished Feb 18 02:46:00 PM PST 24
Peak memory 271412 kb
Host smart-6411c044-71a7-4da0-8a88-335b137e3590
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644352010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rd_intg.644352010
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.3887197411
Short name T963
Test name
Test status
Simulation time 431333200 ps
CPU time 39.22 seconds
Started Feb 18 02:45:18 PM PST 24
Finished Feb 18 02:45:58 PM PST 24
Peak memory 265500 kb
Host smart-784c437a-e127-47cb-b7c3-9c9921635d58
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887197411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.3887197411
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.768470369
Short name T1025
Test name
Test status
Simulation time 31982500 ps
CPU time 22.4 seconds
Started Feb 18 02:45:13 PM PST 24
Finished Feb 18 02:45:38 PM PST 24
Peak memory 264372 kb
Host smart-77d9df55-2e52-4e62-a233-7eb441873911
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768470369 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.768470369
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2664936018
Short name T3
Test name
Test status
Simulation time 24392000 ps
CPU time 22.92 seconds
Started Feb 18 02:45:11 PM PST 24
Finished Feb 18 02:45:36 PM PST 24
Peak memory 263848 kb
Host smart-5341a35e-ad3e-49ff-87e4-7d2f9a020746
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664936018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.2664936018
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.2222295677
Short name T680
Test name
Test status
Simulation time 813584200 ps
CPU time 116.26 seconds
Started Feb 18 02:45:11 PM PST 24
Finished Feb 18 02:47:11 PM PST 24
Peak memory 280632 kb
Host smart-cbfbc630-5ce0-4387-a1d5-6a9a3fc3cc6b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222295677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_ro.2222295677
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.1759244587
Short name T1062
Test name
Test status
Simulation time 1600055700 ps
CPU time 155.2 seconds
Started Feb 18 02:45:11 PM PST 24
Finished Feb 18 02:47:49 PM PST 24
Peak memory 280980 kb
Host smart-ceff84d6-613a-4168-98ee-f508457f7538
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1759244587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1759244587
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.241629252
Short name T486
Test name
Test status
Simulation time 1102523400 ps
CPU time 145.38 seconds
Started Feb 18 02:45:09 PM PST 24
Finished Feb 18 02:47:37 PM PST 24
Peak memory 289160 kb
Host smart-140ae50d-f4f5-4d6a-928c-fe3a0cca0a7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241629252 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.241629252
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.1787689407
Short name T961
Test name
Test status
Simulation time 17150742500 ps
CPU time 670.99 seconds
Started Feb 18 02:45:12 PM PST 24
Finished Feb 18 02:56:26 PM PST 24
Peak memory 313528 kb
Host smart-a30ebc8b-a96b-4e33-bfc5-fce6f96efc3d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787689407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw.1787689407
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.732946895
Short name T127
Test name
Test status
Simulation time 3047946000 ps
CPU time 443.42 seconds
Started Feb 18 02:45:14 PM PST 24
Finished Feb 18 02:52:39 PM PST 24
Peak memory 327496 kb
Host smart-64b942ef-3b5d-4a07-88a3-14c091d01207
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732946895 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_rw_derr.732946895
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.1448135970
Short name T187
Test name
Test status
Simulation time 71700200 ps
CPU time 28.49 seconds
Started Feb 18 02:45:23 PM PST 24
Finished Feb 18 02:45:55 PM PST 24
Peak memory 265532 kb
Host smart-a198e5d5-5d00-4b22-8f0a-881335ea7619
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448135970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.1448135970
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2311462532
Short name T840
Test name
Test status
Simulation time 31392800 ps
CPU time 31.79 seconds
Started Feb 18 02:45:23 PM PST 24
Finished Feb 18 02:45:59 PM PST 24
Peak memory 271604 kb
Host smart-103c6b21-7870-4bda-9a85-da17561fe628
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311462532 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2311462532
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.300860871
Short name T822
Test name
Test status
Simulation time 4199144600 ps
CPU time 480.69 seconds
Started Feb 18 02:45:11 PM PST 24
Finished Feb 18 02:53:15 PM PST 24
Peak memory 319324 kb
Host smart-2d04183a-7b16-4302-8f62-23dfdcb3c9e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300860871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_se
rr.300860871
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.1526330452
Short name T176
Test name
Test status
Simulation time 4007334200 ps
CPU time 4896.13 seconds
Started Feb 18 02:45:26 PM PST 24
Finished Feb 18 04:07:07 PM PST 24
Peak memory 281748 kb
Host smart-4be24135-2939-44b2-a331-a6c1095a1921
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526330452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1526330452
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.1209573093
Short name T347
Test name
Test status
Simulation time 10982827000 ps
CPU time 74.93 seconds
Started Feb 18 02:45:25 PM PST 24
Finished Feb 18 02:46:44 PM PST 24
Peak memory 264284 kb
Host smart-b400f111-5369-4d90-bfcf-da9f13adfa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209573093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.1209573093
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.597467874
Short name T789
Test name
Test status
Simulation time 1363584700 ps
CPU time 73.49 seconds
Started Feb 18 02:45:11 PM PST 24
Finished Feb 18 02:46:27 PM PST 24
Peak memory 264444 kb
Host smart-d9f97cfe-32c1-44a2-8868-5e987bf8cfff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597467874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_serr_address.597467874
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.134982438
Short name T911
Test name
Test status
Simulation time 8841435100 ps
CPU time 80.67 seconds
Started Feb 18 02:45:12 PM PST 24
Finished Feb 18 02:46:35 PM PST 24
Peak memory 272752 kb
Host smart-c360fe14-3e18-4ad3-b0ae-9e6f3f990a72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134982438 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_counter.134982438
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.3757931023
Short name T602
Test name
Test status
Simulation time 45099100 ps
CPU time 171.28 seconds
Started Feb 18 02:44:42 PM PST 24
Finished Feb 18 02:47:37 PM PST 24
Peak memory 275464 kb
Host smart-83ff748d-299e-4fc6-9cbc-a9125078513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757931023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3757931023
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.1480597013
Short name T831
Test name
Test status
Simulation time 55135700 ps
CPU time 26.64 seconds
Started Feb 18 02:44:44 PM PST 24
Finished Feb 18 02:45:14 PM PST 24
Peak memory 258132 kb
Host smart-b67b2d94-1c35-490b-a123-0ea6522c794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480597013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1480597013
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.4074624138
Short name T809
Test name
Test status
Simulation time 1355013900 ps
CPU time 1940.67 seconds
Started Feb 18 02:45:26 PM PST 24
Finished Feb 18 03:17:51 PM PST 24
Peak memory 290384 kb
Host smart-85e0f692-7384-436d-bbac-b71fe65ceb9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074624138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.4074624138
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.859186412
Short name T768
Test name
Test status
Simulation time 43736300 ps
CPU time 26.48 seconds
Started Feb 18 02:44:43 PM PST 24
Finished Feb 18 02:45:13 PM PST 24
Peak memory 258508 kb
Host smart-aa0dda7b-6ab2-432f-b213-983976d69149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859186412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.859186412
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.828265385
Short name T4
Test name
Test status
Simulation time 5318686400 ps
CPU time 226.78 seconds
Started Feb 18 02:45:00 PM PST 24
Finished Feb 18 02:48:53 PM PST 24
Peak memory 264340 kb
Host smart-792b5394-6857-460a-b7ec-58c1feeebc8e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828265385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_wo.828265385
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.636988930
Short name T745
Test name
Test status
Simulation time 139495500 ps
CPU time 14.31 seconds
Started Feb 18 02:52:45 PM PST 24
Finished Feb 18 02:53:05 PM PST 24
Peak memory 264200 kb
Host smart-05fa591b-efa0-40f5-824b-2041d1a3321b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636988930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.636988930
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.291361639
Short name T671
Test name
Test status
Simulation time 28740700 ps
CPU time 15.83 seconds
Started Feb 18 02:52:42 PM PST 24
Finished Feb 18 02:53:01 PM PST 24
Peak memory 273700 kb
Host smart-2d264600-639e-4314-8cb7-af141e271a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291361639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.291361639
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.3296738957
Short name T104
Test name
Test status
Simulation time 28882200 ps
CPU time 21.65 seconds
Started Feb 18 02:52:42 PM PST 24
Finished Feb 18 02:53:08 PM PST 24
Peak memory 279720 kb
Host smart-ba68462a-6994-4a2a-8b7d-2b9a2a6b3c45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296738957 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.3296738957
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2104213845
Short name T989
Test name
Test status
Simulation time 28888678800 ps
CPU time 105.84 seconds
Started Feb 18 02:52:43 PM PST 24
Finished Feb 18 02:54:33 PM PST 24
Peak memory 261424 kb
Host smart-a8114155-ee37-4e05-9580-1294096aaf7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104213845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2104213845
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.509759285
Short name T569
Test name
Test status
Simulation time 4784794400 ps
CPU time 177.11 seconds
Started Feb 18 02:52:37 PM PST 24
Finished Feb 18 02:55:35 PM PST 24
Peak memory 289072 kb
Host smart-ed75712f-264e-4b02-ad8b-5969adabd0ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509759285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flas
h_ctrl_intr_rd.509759285
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3160175236
Short name T493
Test name
Test status
Simulation time 63040978300 ps
CPU time 247.12 seconds
Started Feb 18 02:52:37 PM PST 24
Finished Feb 18 02:56:45 PM PST 24
Peak memory 283892 kb
Host smart-fdecaee2-1500-4c74-862e-018a18b70dc4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160175236 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.3160175236
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.2308792459
Short name T649
Test name
Test status
Simulation time 218114900 ps
CPU time 113.85 seconds
Started Feb 18 02:52:39 PM PST 24
Finished Feb 18 02:54:33 PM PST 24
Peak memory 258708 kb
Host smart-4586ca74-ab2f-49b8-bf90-522e7e6ea04f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308792459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.2308792459
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.1632254165
Short name T396
Test name
Test status
Simulation time 18088300 ps
CPU time 13.9 seconds
Started Feb 18 02:52:37 PM PST 24
Finished Feb 18 02:52:52 PM PST 24
Peak memory 264276 kb
Host smart-0ab8e64f-93dd-4008-8494-cb20630ff1ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632254165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.1632254165
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.2989905652
Short name T606
Test name
Test status
Simulation time 160278900 ps
CPU time 31.23 seconds
Started Feb 18 02:52:40 PM PST 24
Finished Feb 18 02:53:12 PM PST 24
Peak memory 273684 kb
Host smart-1833f738-5b83-4b4d-bf89-6cabc335c178
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989905652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.2989905652
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2096575671
Short name T188
Test name
Test status
Simulation time 29007200 ps
CPU time 31.25 seconds
Started Feb 18 02:52:45 PM PST 24
Finished Feb 18 02:53:21 PM PST 24
Peak memory 273732 kb
Host smart-f469a064-841d-427e-9037-d96f2895e7e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096575671 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2096575671
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.3871789628
Short name T925
Test name
Test status
Simulation time 8438592100 ps
CPU time 81.88 seconds
Started Feb 18 02:52:37 PM PST 24
Finished Feb 18 02:53:59 PM PST 24
Peak memory 258680 kb
Host smart-f4adb63f-97d4-4508-a5a3-24b1d7afc32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871789628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3871789628
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.382828972
Short name T206
Test name
Test status
Simulation time 6810511400 ps
CPU time 156.32 seconds
Started Feb 18 02:52:29 PM PST 24
Finished Feb 18 02:55:07 PM PST 24
Peak memory 280652 kb
Host smart-cfef606e-acbd-4091-894c-a5f460fe2f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382828972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.382828972
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.2029034616
Short name T919
Test name
Test status
Simulation time 137775600 ps
CPU time 14.16 seconds
Started Feb 18 02:53:00 PM PST 24
Finished Feb 18 02:53:16 PM PST 24
Peak memory 263940 kb
Host smart-54ba8054-a4a5-44ea-be3e-61321dd9a19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029034616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
2029034616
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.4291859023
Short name T857
Test name
Test status
Simulation time 26335900 ps
CPU time 15.52 seconds
Started Feb 18 02:52:45 PM PST 24
Finished Feb 18 02:53:06 PM PST 24
Peak memory 274848 kb
Host smart-e8ca14f8-6cb6-4ccb-af96-f0251f6538e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291859023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.4291859023
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.1042352377
Short name T497
Test name
Test status
Simulation time 22074600 ps
CPU time 22.32 seconds
Started Feb 18 02:52:44 PM PST 24
Finished Feb 18 02:53:11 PM PST 24
Peak memory 279760 kb
Host smart-db486f55-e7ef-458a-8eb9-b53d12fc9047
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042352377 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.1042352377
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.1703225774
Short name T503
Test name
Test status
Simulation time 10590613700 ps
CPU time 210.49 seconds
Started Feb 18 02:52:44 PM PST 24
Finished Feb 18 02:56:20 PM PST 24
Peak memory 258200 kb
Host smart-52fa55fc-1308-4415-9e0a-906ee30d9236
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703225774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.1703225774
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1065292899
Short name T247
Test name
Test status
Simulation time 4564983600 ps
CPU time 151.43 seconds
Started Feb 18 02:52:44 PM PST 24
Finished Feb 18 02:55:21 PM PST 24
Peak memory 293060 kb
Host smart-161a85fc-e55e-4334-bbf3-cf390c1a9091
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065292899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1065292899
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.4070337386
Short name T933
Test name
Test status
Simulation time 9006865900 ps
CPU time 182.76 seconds
Started Feb 18 02:52:42 PM PST 24
Finished Feb 18 02:55:48 PM PST 24
Peak memory 289036 kb
Host smart-df8be76a-9331-4522-8553-b27ca9702b2c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070337386 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.4070337386
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.3551252987
Short name T777
Test name
Test status
Simulation time 65262100 ps
CPU time 13.57 seconds
Started Feb 18 02:52:43 PM PST 24
Finished Feb 18 02:53:00 PM PST 24
Peak memory 264316 kb
Host smart-e9fabd13-c741-4fc2-9320-11a94491f540
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551252987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.3551252987
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.70039471
Short name T143
Test name
Test status
Simulation time 32067900 ps
CPU time 31.73 seconds
Started Feb 18 02:52:44 PM PST 24
Finished Feb 18 02:53:21 PM PST 24
Peak memory 272736 kb
Host smart-63950832-bc06-4bcc-91a9-864d19ae0aca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70039471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flas
h_ctrl_rw_evict.70039471
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.18185569
Short name T544
Test name
Test status
Simulation time 157344400 ps
CPU time 31.82 seconds
Started Feb 18 02:52:42 PM PST 24
Finished Feb 18 02:53:16 PM PST 24
Peak memory 273744 kb
Host smart-57e0aaa7-9af5-4429-93bf-555435de0095
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18185569 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.18185569
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.646189390
Short name T558
Test name
Test status
Simulation time 400110900 ps
CPU time 58.61 seconds
Started Feb 18 02:52:43 PM PST 24
Finished Feb 18 02:53:46 PM PST 24
Peak memory 262088 kb
Host smart-f7a5028d-0a57-4537-b1dd-9adb946fc4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646189390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.646189390
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.403518262
Short name T508
Test name
Test status
Simulation time 37023700 ps
CPU time 124.7 seconds
Started Feb 18 02:52:43 PM PST 24
Finished Feb 18 02:54:52 PM PST 24
Peak memory 274612 kb
Host smart-25c0eb16-1c64-4cb4-a400-84ff616de2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403518262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.403518262
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.2717214174
Short name T896
Test name
Test status
Simulation time 27010800 ps
CPU time 13.65 seconds
Started Feb 18 02:52:55 PM PST 24
Finished Feb 18 02:53:10 PM PST 24
Peak memory 264240 kb
Host smart-e602cf1b-24e3-4b71-9e1d-4a315d1f3bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717214174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
2717214174
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.3218471931
Short name T824
Test name
Test status
Simulation time 69653800 ps
CPU time 15.7 seconds
Started Feb 18 02:52:55 PM PST 24
Finished Feb 18 02:53:12 PM PST 24
Peak memory 273808 kb
Host smart-2d4d2b42-69ab-4567-bcb1-e0b16406b039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218471931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3218471931
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.26321531
Short name T288
Test name
Test status
Simulation time 5990714000 ps
CPU time 132.44 seconds
Started Feb 18 02:52:55 PM PST 24
Finished Feb 18 02:55:09 PM PST 24
Peak memory 261492 kb
Host smart-9cb2a9dd-38e3-4a27-a987-cab7a0765bbc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26321531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw
_sec_otp.26321531
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.4341899
Short name T178
Test name
Test status
Simulation time 1208057900 ps
CPU time 167.83 seconds
Started Feb 18 02:52:54 PM PST 24
Finished Feb 18 02:55:43 PM PST 24
Peak memory 291680 kb
Host smart-d846208c-8993-4285-b06b-0f0d0b3e9b54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4341899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=
flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_
ctrl_intr_rd.4341899
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2448918478
Short name T604
Test name
Test status
Simulation time 16713150200 ps
CPU time 223.99 seconds
Started Feb 18 02:52:55 PM PST 24
Finished Feb 18 02:56:40 PM PST 24
Peak memory 289988 kb
Host smart-e2a5fdf0-2601-449f-a724-cc861c5e4efb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448918478 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.2448918478
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.4202052795
Short name T639
Test name
Test status
Simulation time 20801700 ps
CPU time 13.41 seconds
Started Feb 18 02:52:54 PM PST 24
Finished Feb 18 02:53:08 PM PST 24
Peak memory 263704 kb
Host smart-84bbf224-14a9-44e9-b201-a13c4faf6b6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202052795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.4202052795
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.3924483994
Short name T900
Test name
Test status
Simulation time 179464600 ps
CPU time 34.95 seconds
Started Feb 18 02:52:55 PM PST 24
Finished Feb 18 02:53:31 PM PST 24
Peak memory 276232 kb
Host smart-eee2d5bd-07ee-44cc-b893-c5d10e83d8e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924483994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.3924483994
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.48743219
Short name T524
Test name
Test status
Simulation time 91616700 ps
CPU time 31.97 seconds
Started Feb 18 02:52:54 PM PST 24
Finished Feb 18 02:53:28 PM PST 24
Peak memory 273852 kb
Host smart-dc522977-2837-4add-93b8-d7aa148f1f9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48743219 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.48743219
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.1654489870
Short name T153
Test name
Test status
Simulation time 2249417800 ps
CPU time 62.2 seconds
Started Feb 18 02:52:56 PM PST 24
Finished Feb 18 02:53:59 PM PST 24
Peak memory 262692 kb
Host smart-4e76defc-d1f3-46d3-8d62-29a80c28e0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654489870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1654489870
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.1499909335
Short name T722
Test name
Test status
Simulation time 321711800 ps
CPU time 147.19 seconds
Started Feb 18 02:52:57 PM PST 24
Finished Feb 18 02:55:25 PM PST 24
Peak memory 275148 kb
Host smart-f518b187-e5e8-4039-99af-a28637153e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499909335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1499909335
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.670508512
Short name T972
Test name
Test status
Simulation time 20766300 ps
CPU time 14.06 seconds
Started Feb 18 02:52:57 PM PST 24
Finished Feb 18 02:53:12 PM PST 24
Peak memory 264240 kb
Host smart-33cf281c-6f4f-4379-96fa-86718966b2dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670508512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.670508512
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.2103206823
Short name T383
Test name
Test status
Simulation time 44192400 ps
CPU time 16.29 seconds
Started Feb 18 02:52:56 PM PST 24
Finished Feb 18 02:53:14 PM PST 24
Peak memory 274932 kb
Host smart-4122e511-720b-4bed-8b44-d5fa23cf5d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103206823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2103206823
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.228349817
Short name T681
Test name
Test status
Simulation time 3758940500 ps
CPU time 164 seconds
Started Feb 18 02:52:59 PM PST 24
Finished Feb 18 02:55:45 PM PST 24
Peak memory 261396 kb
Host smart-e5da42d7-891d-4bf3-a1a8-70cf3a2f2aa1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228349817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_h
w_sec_otp.228349817
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.1673150879
Short name T869
Test name
Test status
Simulation time 5181559600 ps
CPU time 165.22 seconds
Started Feb 18 02:52:58 PM PST 24
Finished Feb 18 02:55:45 PM PST 24
Peak memory 284044 kb
Host smart-d541a48c-cb9e-4b22-b12f-2b2069b47790
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673150879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.1673150879
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.1598039332
Short name T59
Test name
Test status
Simulation time 32507486900 ps
CPU time 215.02 seconds
Started Feb 18 02:52:57 PM PST 24
Finished Feb 18 02:56:33 PM PST 24
Peak memory 291612 kb
Host smart-5c31a5ed-832f-4abe-8b40-d54073ab8be7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598039332 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.1598039332
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.1361895527
Short name T939
Test name
Test status
Simulation time 37735400 ps
CPU time 131.33 seconds
Started Feb 18 02:52:57 PM PST 24
Finished Feb 18 02:55:09 PM PST 24
Peak memory 258768 kb
Host smart-7a059ec1-efab-49e2-9a50-9d12a1eeca71
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361895527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.1361895527
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.3420385689
Short name T78
Test name
Test status
Simulation time 24027200 ps
CPU time 14.41 seconds
Started Feb 18 02:52:57 PM PST 24
Finished Feb 18 02:53:13 PM PST 24
Peak memory 264276 kb
Host smart-c2763d28-8690-4196-9e26-98779d7df6b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420385689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.3420385689
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.2377581030
Short name T738
Test name
Test status
Simulation time 170809000 ps
CPU time 33.99 seconds
Started Feb 18 02:53:00 PM PST 24
Finished Feb 18 02:53:36 PM PST 24
Peak memory 272684 kb
Host smart-d7f93827-2bcf-4246-ab0b-48ac6db733cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377581030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.2377581030
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1517263461
Short name T600
Test name
Test status
Simulation time 75310200 ps
CPU time 29.24 seconds
Started Feb 18 02:52:59 PM PST 24
Finished Feb 18 02:53:30 PM PST 24
Peak memory 272688 kb
Host smart-dacd07ba-f276-4cec-bdde-b281f3e22fcf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517263461 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.1517263461
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.264614535
Short name T554
Test name
Test status
Simulation time 851605200 ps
CPU time 57.03 seconds
Started Feb 18 02:52:59 PM PST 24
Finished Feb 18 02:53:58 PM PST 24
Peak memory 258676 kb
Host smart-54a57f1a-c39f-475e-b1c7-d69f858d5db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264614535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.264614535
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.1388405233
Short name T990
Test name
Test status
Simulation time 37844900 ps
CPU time 126.18 seconds
Started Feb 18 02:53:00 PM PST 24
Finished Feb 18 02:55:08 PM PST 24
Peak memory 276036 kb
Host smart-c1c560be-d608-4283-980d-6ae80524b02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388405233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.1388405233
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.2352177016
Short name T829
Test name
Test status
Simulation time 152444600 ps
CPU time 13.81 seconds
Started Feb 18 02:53:02 PM PST 24
Finished Feb 18 02:53:18 PM PST 24
Peak memory 264268 kb
Host smart-84d814f9-0a3d-48bd-8bd7-d2a684c9033f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352177016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
2352177016
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.2412639746
Short name T882
Test name
Test status
Simulation time 14840000 ps
CPU time 16.05 seconds
Started Feb 18 02:53:08 PM PST 24
Finished Feb 18 02:53:25 PM PST 24
Peak memory 274940 kb
Host smart-1fd75761-8537-41b8-9e63-8e1f6e694a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412639746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2412639746
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.1794879800
Short name T41
Test name
Test status
Simulation time 10620200 ps
CPU time 20.97 seconds
Started Feb 18 02:53:05 PM PST 24
Finished Feb 18 02:53:27 PM PST 24
Peak memory 272696 kb
Host smart-cce1855a-67fc-4973-bc12-560c51ecf36b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794879800 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.1794879800
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.4054406910
Short name T826
Test name
Test status
Simulation time 4054204100 ps
CPU time 195.75 seconds
Started Feb 18 02:52:57 PM PST 24
Finished Feb 18 02:56:14 PM PST 24
Peak memory 261468 kb
Host smart-89f7be7c-7e25-4775-ac07-62827886e2b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054406910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.4054406910
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.3364876516
Short name T20
Test name
Test status
Simulation time 1276402900 ps
CPU time 174.51 seconds
Started Feb 18 02:53:03 PM PST 24
Finished Feb 18 02:56:00 PM PST 24
Peak memory 288968 kb
Host smart-f1f9d550-2c97-409b-8ed5-2c54ed7e865c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364876516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.3364876516
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3246939665
Short name T483
Test name
Test status
Simulation time 8516268800 ps
CPU time 183.28 seconds
Started Feb 18 02:53:07 PM PST 24
Finished Feb 18 02:56:11 PM PST 24
Peak memory 283680 kb
Host smart-13001d00-6a0f-49fa-a2ce-379203336fdd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246939665 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3246939665
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.3260128271
Short name T969
Test name
Test status
Simulation time 29975200 ps
CPU time 13.57 seconds
Started Feb 18 02:53:04 PM PST 24
Finished Feb 18 02:53:19 PM PST 24
Peak memory 264292 kb
Host smart-6e4ebb4f-c733-40f1-a548-2a2de889a758
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260128271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.3260128271
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.301698313
Short name T755
Test name
Test status
Simulation time 332041300 ps
CPU time 30.78 seconds
Started Feb 18 02:53:06 PM PST 24
Finished Feb 18 02:53:39 PM PST 24
Peak memory 265488 kb
Host smart-fc73b2c5-1454-409c-961e-dc48028c9d12
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301698313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_rw_evict.301698313
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.278283452
Short name T794
Test name
Test status
Simulation time 114309700 ps
CPU time 31.81 seconds
Started Feb 18 02:53:02 PM PST 24
Finished Feb 18 02:53:36 PM PST 24
Peak memory 271576 kb
Host smart-dbf5808f-01d6-4509-a0af-51b9cb05c519
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278283452 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.278283452
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.830791710
Short name T860
Test name
Test status
Simulation time 3876245600 ps
CPU time 65.83 seconds
Started Feb 18 02:53:05 PM PST 24
Finished Feb 18 02:54:12 PM PST 24
Peak memory 263272 kb
Host smart-b077e6bf-fb5d-457c-90fb-a1b15d89dc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830791710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.830791710
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.3403730841
Short name T376
Test name
Test status
Simulation time 308033500 ps
CPU time 192.76 seconds
Started Feb 18 02:52:58 PM PST 24
Finished Feb 18 02:56:12 PM PST 24
Peak memory 275620 kb
Host smart-2ba87f23-6b43-4063-bd5e-c9002ac31de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403730841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3403730841
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.4070577447
Short name T1031
Test name
Test status
Simulation time 91643900 ps
CPU time 14.43 seconds
Started Feb 18 02:53:10 PM PST 24
Finished Feb 18 02:53:26 PM PST 24
Peak memory 264208 kb
Host smart-e5d71c08-e598-4318-8c59-b39a4b004acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070577447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
4070577447
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.816680381
Short name T379
Test name
Test status
Simulation time 15250300 ps
CPU time 16.08 seconds
Started Feb 18 02:53:09 PM PST 24
Finished Feb 18 02:53:27 PM PST 24
Peak memory 283108 kb
Host smart-7edae77a-f95c-4658-8d04-afe39f37e95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816680381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.816680381
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.403041014
Short name T580
Test name
Test status
Simulation time 7521696300 ps
CPU time 84.94 seconds
Started Feb 18 02:53:09 PM PST 24
Finished Feb 18 02:54:36 PM PST 24
Peak memory 261344 kb
Host smart-f94d895b-8eed-46e3-91a4-8db11e3d1787
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403041014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_h
w_sec_otp.403041014
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.471791797
Short name T688
Test name
Test status
Simulation time 2337248200 ps
CPU time 186.66 seconds
Started Feb 18 02:53:08 PM PST 24
Finished Feb 18 02:56:17 PM PST 24
Peak memory 289056 kb
Host smart-21c18533-38b2-48d8-8213-990b622802a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471791797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flas
h_ctrl_intr_rd.471791797
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1937253305
Short name T568
Test name
Test status
Simulation time 8453327200 ps
CPU time 213.96 seconds
Started Feb 18 02:53:09 PM PST 24
Finished Feb 18 02:56:45 PM PST 24
Peak memory 283876 kb
Host smart-07dfa196-f24a-4b2c-b6b4-a0d6a48e2c14
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937253305 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.1937253305
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1035589634
Short name T631
Test name
Test status
Simulation time 41700400 ps
CPU time 114.54 seconds
Started Feb 18 02:53:07 PM PST 24
Finished Feb 18 02:55:04 PM PST 24
Peak memory 259864 kb
Host smart-0cb6833c-31ee-4bab-bca8-1d8f8b408270
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035589634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1035589634
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.3204285682
Short name T832
Test name
Test status
Simulation time 22580300 ps
CPU time 14.15 seconds
Started Feb 18 02:53:16 PM PST 24
Finished Feb 18 02:53:32 PM PST 24
Peak memory 264340 kb
Host smart-4ea71e30-cba5-493b-a157-0c55cd3f5052
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204285682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.3204285682
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.2779485102
Short name T888
Test name
Test status
Simulation time 30578900 ps
CPU time 31.54 seconds
Started Feb 18 02:53:10 PM PST 24
Finished Feb 18 02:53:43 PM PST 24
Peak memory 272716 kb
Host smart-7846e2b0-eac4-425c-b333-379a59208860
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779485102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.2779485102
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2262589090
Short name T1010
Test name
Test status
Simulation time 74112200 ps
CPU time 29.19 seconds
Started Feb 18 02:53:10 PM PST 24
Finished Feb 18 02:53:41 PM PST 24
Peak memory 265464 kb
Host smart-0adba1a0-70e8-4223-a5df-4d9732411750
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262589090 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2262589090
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.886396142
Short name T918
Test name
Test status
Simulation time 1516340000 ps
CPU time 57.39 seconds
Started Feb 18 02:53:09 PM PST 24
Finished Feb 18 02:54:08 PM PST 24
Peak memory 258688 kb
Host smart-a7328f70-2071-4782-a7a9-427ea09c00dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886396142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.886396142
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.666547540
Short name T808
Test name
Test status
Simulation time 155333700 ps
CPU time 145.25 seconds
Started Feb 18 02:53:16 PM PST 24
Finished Feb 18 02:55:44 PM PST 24
Peak memory 275132 kb
Host smart-2c2bcd52-f3d1-42bb-ab6c-b16be71bd59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666547540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.666547540
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.341469897
Short name T818
Test name
Test status
Simulation time 75333700 ps
CPU time 13.96 seconds
Started Feb 18 02:53:23 PM PST 24
Finished Feb 18 02:53:42 PM PST 24
Peak memory 263836 kb
Host smart-d9d730cd-945f-4cff-b5f4-03abe750ff7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341469897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.341469897
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.1981058345
Short name T663
Test name
Test status
Simulation time 16664200 ps
CPU time 15.97 seconds
Started Feb 18 02:53:22 PM PST 24
Finished Feb 18 02:53:41 PM PST 24
Peak memory 274592 kb
Host smart-0c1c47d7-0430-4cf9-bfb4-f55ce644bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981058345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1981058345
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.2489569506
Short name T32
Test name
Test status
Simulation time 36752200 ps
CPU time 21.75 seconds
Started Feb 18 02:53:18 PM PST 24
Finished Feb 18 02:53:44 PM PST 24
Peak memory 272716 kb
Host smart-518c8c22-b8b1-48c2-80ea-6c114af765a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489569506 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.2489569506
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.3601396120
Short name T947
Test name
Test status
Simulation time 1310918200 ps
CPU time 171.22 seconds
Started Feb 18 02:53:10 PM PST 24
Finished Feb 18 02:56:03 PM PST 24
Peak memory 293972 kb
Host smart-c19010dd-6569-4141-8d0e-8dc13aea9eed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601396120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.3601396120
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2036204549
Short name T712
Test name
Test status
Simulation time 40464493000 ps
CPU time 215.52 seconds
Started Feb 18 02:53:25 PM PST 24
Finished Feb 18 02:57:05 PM PST 24
Peak memory 283928 kb
Host smart-6534dd8b-3f92-4ba1-8369-637fd6e54474
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036204549 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.2036204549
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.3491393440
Short name T1043
Test name
Test status
Simulation time 85896900 ps
CPU time 135.38 seconds
Started Feb 18 02:53:12 PM PST 24
Finished Feb 18 02:55:31 PM PST 24
Peak memory 258844 kb
Host smart-3946c9ce-048a-40fa-93ae-ffda4d55e788
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491393440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.3491393440
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2896701919
Short name T65
Test name
Test status
Simulation time 62568700 ps
CPU time 13.98 seconds
Started Feb 18 02:53:20 PM PST 24
Finished Feb 18 02:53:38 PM PST 24
Peak memory 264288 kb
Host smart-c5142b02-bf7c-44d2-8fbc-ff952c6a1bb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896701919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.2896701919
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.1262284812
Short name T761
Test name
Test status
Simulation time 213717600 ps
CPU time 29.31 seconds
Started Feb 18 02:53:22 PM PST 24
Finished Feb 18 02:53:55 PM PST 24
Peak memory 273732 kb
Host smart-9d1343dd-5086-4b32-a8e8-0f874bd9937e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262284812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.1262284812
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3423508606
Short name T709
Test name
Test status
Simulation time 36699100 ps
CPU time 30.71 seconds
Started Feb 18 02:53:19 PM PST 24
Finished Feb 18 02:53:53 PM PST 24
Peak memory 277160 kb
Host smart-49151594-4f2c-4707-ae82-e054c99a9b17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423508606 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3423508606
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.1605716592
Short name T349
Test name
Test status
Simulation time 1955538900 ps
CPU time 64.03 seconds
Started Feb 18 02:53:16 PM PST 24
Finished Feb 18 02:54:23 PM PST 24
Peak memory 258676 kb
Host smart-1e9508dc-c297-4bd9-93a8-ca3b7cf43edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605716592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.1605716592
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.4033695362
Short name T337
Test name
Test status
Simulation time 192358300 ps
CPU time 119.76 seconds
Started Feb 18 02:53:09 PM PST 24
Finished Feb 18 02:55:11 PM PST 24
Peak memory 277756 kb
Host smart-e7a6e718-4469-455c-b858-4b96576578f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033695362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.4033695362
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.2682726555
Short name T687
Test name
Test status
Simulation time 141237500 ps
CPU time 14.19 seconds
Started Feb 18 02:53:31 PM PST 24
Finished Feb 18 02:53:49 PM PST 24
Peak memory 263856 kb
Host smart-cdce62ab-4118-4fe6-9d57-0ba7bbf5fa9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682726555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
2682726555
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.206860706
Short name T547
Test name
Test status
Simulation time 47262600 ps
CPU time 13.54 seconds
Started Feb 18 02:53:32 PM PST 24
Finished Feb 18 02:53:49 PM PST 24
Peak memory 273692 kb
Host smart-35a72877-fe8f-410e-8c86-c385cc2303e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206860706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.206860706
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.197530859
Short name T701
Test name
Test status
Simulation time 10668500 ps
CPU time 22.01 seconds
Started Feb 18 02:53:31 PM PST 24
Finished Feb 18 02:53:56 PM PST 24
Peak memory 272676 kb
Host smart-a86c53cc-52e9-46c7-b0a4-3b5427d510ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197530859 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.197530859
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.109677221
Short name T645
Test name
Test status
Simulation time 9893539000 ps
CPU time 245.06 seconds
Started Feb 18 02:53:22 PM PST 24
Finished Feb 18 02:57:31 PM PST 24
Peak memory 261004 kb
Host smart-235fff57-07e3-4557-9834-490b86e3ed04
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109677221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h
w_sec_otp.109677221
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.3741054482
Short name T1020
Test name
Test status
Simulation time 2093546100 ps
CPU time 161 seconds
Started Feb 18 02:53:28 PM PST 24
Finished Feb 18 02:56:13 PM PST 24
Peak memory 293116 kb
Host smart-4ef65390-96fa-4b63-9ba2-de674783ce2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741054482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.3741054482
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3230042350
Short name T436
Test name
Test status
Simulation time 8230791300 ps
CPU time 214.66 seconds
Started Feb 18 02:53:30 PM PST 24
Finished Feb 18 02:57:08 PM PST 24
Peak memory 291528 kb
Host smart-dcc2950f-fd4a-4f91-a564-0a52a51ea510
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230042350 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.3230042350
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.2243877900
Short name T532
Test name
Test status
Simulation time 38544000 ps
CPU time 135.36 seconds
Started Feb 18 02:53:30 PM PST 24
Finished Feb 18 02:55:49 PM PST 24
Peak memory 258932 kb
Host smart-62e6ba60-1ec3-4409-9aaa-908aca4090a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243877900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.2243877900
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.1772870914
Short name T591
Test name
Test status
Simulation time 39151400 ps
CPU time 13.69 seconds
Started Feb 18 02:53:31 PM PST 24
Finished Feb 18 02:53:47 PM PST 24
Peak memory 264364 kb
Host smart-f1cdd2cc-dbe6-4ebd-b424-8e74fec6ccb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772870914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.1772870914
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.3173260953
Short name T727
Test name
Test status
Simulation time 100412200 ps
CPU time 31.52 seconds
Started Feb 18 02:53:24 PM PST 24
Finished Feb 18 02:54:00 PM PST 24
Peak memory 265544 kb
Host smart-a3cbc55c-cc41-44f6-95a9-33486a808141
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173260953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.3173260953
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.2402273759
Short name T816
Test name
Test status
Simulation time 42702200 ps
CPU time 32.75 seconds
Started Feb 18 02:53:29 PM PST 24
Finished Feb 18 02:54:05 PM PST 24
Peak memory 271604 kb
Host smart-d508fc7b-8c19-4bb2-85cd-7e31721291f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402273759 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.2402273759
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.3218090160
Short name T354
Test name
Test status
Simulation time 417612400 ps
CPU time 60.54 seconds
Started Feb 18 02:53:31 PM PST 24
Finished Feb 18 02:54:35 PM PST 24
Peak memory 262004 kb
Host smart-68c06c0c-d81b-4763-b90b-6c8f11e09e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218090160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.3218090160
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.2099316042
Short name T668
Test name
Test status
Simulation time 101188400 ps
CPU time 146.44 seconds
Started Feb 18 02:53:23 PM PST 24
Finished Feb 18 02:55:53 PM PST 24
Peak memory 275196 kb
Host smart-f8f7cfc1-31af-4502-8d84-d34d5706282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099316042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.2099316042
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.1527870630
Short name T152
Test name
Test status
Simulation time 74873100 ps
CPU time 13.91 seconds
Started Feb 18 02:53:35 PM PST 24
Finished Feb 18 02:53:52 PM PST 24
Peak memory 263876 kb
Host smart-99af71d4-a20e-4d97-84f3-d42303488194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527870630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
1527870630
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.568047845
Short name T677
Test name
Test status
Simulation time 161633700 ps
CPU time 15.96 seconds
Started Feb 18 02:53:29 PM PST 24
Finished Feb 18 02:53:48 PM PST 24
Peak memory 274612 kb
Host smart-574fdca0-6630-408f-8540-2dff8e777c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568047845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.568047845
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.719369867
Short name T388
Test name
Test status
Simulation time 7429217900 ps
CPU time 55.79 seconds
Started Feb 18 02:53:30 PM PST 24
Finished Feb 18 02:54:29 PM PST 24
Peak memory 261420 kb
Host smart-4429a05e-cf4d-4565-a918-6aec76cca1c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719369867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_h
w_sec_otp.719369867
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.4016263082
Short name T876
Test name
Test status
Simulation time 7784804200 ps
CPU time 198.15 seconds
Started Feb 18 02:53:30 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 291448 kb
Host smart-7a172abc-38e4-4ae3-a510-b568d4cb5ceb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016263082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.4016263082
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1198370093
Short name T511
Test name
Test status
Simulation time 15527420300 ps
CPU time 213.61 seconds
Started Feb 18 02:53:30 PM PST 24
Finished Feb 18 02:57:07 PM PST 24
Peak memory 283528 kb
Host smart-8e37bbed-99fd-4027-ab9d-845f25a43f1c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198370093 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.1198370093
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.3246545412
Short name T80
Test name
Test status
Simulation time 36728900 ps
CPU time 133.87 seconds
Started Feb 18 02:53:31 PM PST 24
Finished Feb 18 02:55:48 PM PST 24
Peak memory 258828 kb
Host smart-298eb739-8876-452e-bdd4-7ac25892ab72
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246545412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.3246545412
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.2991861798
Short name T372
Test name
Test status
Simulation time 194382000 ps
CPU time 13.98 seconds
Started Feb 18 02:53:32 PM PST 24
Finished Feb 18 02:53:50 PM PST 24
Peak memory 264340 kb
Host smart-23da3457-40e5-4b0e-9bae-e6fb6864866e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991861798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.2991861798
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.74132371
Short name T786
Test name
Test status
Simulation time 118268000 ps
CPU time 30.93 seconds
Started Feb 18 02:53:30 PM PST 24
Finished Feb 18 02:54:04 PM PST 24
Peak memory 272692 kb
Host smart-3fcba5be-b3ec-4e15-a47c-4f97eb0b1f72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74132371 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.74132371
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.3245413558
Short name T159
Test name
Test status
Simulation time 375643100 ps
CPU time 57.53 seconds
Started Feb 18 02:53:30 PM PST 24
Finished Feb 18 02:54:31 PM PST 24
Peak memory 258688 kb
Host smart-a371f07d-0870-408f-80f5-71e84c8ba09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245413558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3245413558
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.3838459152
Short name T1033
Test name
Test status
Simulation time 27619000 ps
CPU time 122.12 seconds
Started Feb 18 02:53:24 PM PST 24
Finished Feb 18 02:55:31 PM PST 24
Peak memory 274456 kb
Host smart-5166aac5-968e-43bb-8697-d9431622cdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838459152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.3838459152
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.4003364641
Short name T780
Test name
Test status
Simulation time 42722300 ps
CPU time 13.54 seconds
Started Feb 18 02:53:40 PM PST 24
Finished Feb 18 02:53:58 PM PST 24
Peak memory 263844 kb
Host smart-cc45aee1-3823-40e8-82c7-151d72a52b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003364641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
4003364641
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.811022041
Short name T422
Test name
Test status
Simulation time 187041500 ps
CPU time 16.98 seconds
Started Feb 18 02:53:40 PM PST 24
Finished Feb 18 02:54:01 PM PST 24
Peak memory 273676 kb
Host smart-91fec061-70b2-4050-8b6c-9725b4d9e699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811022041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.811022041
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.706967258
Short name T48
Test name
Test status
Simulation time 8571005600 ps
CPU time 156.78 seconds
Started Feb 18 02:53:35 PM PST 24
Finished Feb 18 02:56:15 PM PST 24
Peak memory 261152 kb
Host smart-670ad84e-17fe-446a-b3ec-d27d55cda92d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706967258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_h
w_sec_otp.706967258
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.3731247551
Short name T186
Test name
Test status
Simulation time 5504557700 ps
CPU time 177 seconds
Started Feb 18 02:53:37 PM PST 24
Finished Feb 18 02:56:38 PM PST 24
Peak memory 292912 kb
Host smart-855647ca-489a-4db7-b62e-a015a69ec533
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731247551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.3731247551
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1089184862
Short name T472
Test name
Test status
Simulation time 9192278300 ps
CPU time 186.32 seconds
Started Feb 18 02:53:42 PM PST 24
Finished Feb 18 02:56:53 PM PST 24
Peak memory 283620 kb
Host smart-6379db0f-add9-4c4b-ab30-2808ce14769d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089184862 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.1089184862
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.3459709908
Short name T475
Test name
Test status
Simulation time 21082300 ps
CPU time 13.72 seconds
Started Feb 18 02:53:38 PM PST 24
Finished Feb 18 02:53:57 PM PST 24
Peak memory 264416 kb
Host smart-d50c18cb-727f-45d7-898b-71f3ec5cd476
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459709908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.3459709908
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.3930324918
Short name T435
Test name
Test status
Simulation time 124354500 ps
CPU time 38.18 seconds
Started Feb 18 02:53:42 PM PST 24
Finished Feb 18 02:54:25 PM PST 24
Peak memory 272644 kb
Host smart-374112a6-5f6e-4461-9a8a-56c8f3a7a3a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930324918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.3930324918
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3052542806
Short name T937
Test name
Test status
Simulation time 67398600 ps
CPU time 31.3 seconds
Started Feb 18 02:53:37 PM PST 24
Finished Feb 18 02:54:12 PM PST 24
Peak memory 273664 kb
Host smart-83f59f67-640e-4cab-baab-c80f60b3070c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052542806 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3052542806
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.521282931
Short name T496
Test name
Test status
Simulation time 545230400 ps
CPU time 66.15 seconds
Started Feb 18 02:53:40 PM PST 24
Finished Feb 18 02:54:51 PM PST 24
Peak memory 258676 kb
Host smart-4e9c566e-750f-420b-893f-ebffadbf84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521282931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.521282931
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.3834573000
Short name T581
Test name
Test status
Simulation time 36209000 ps
CPU time 75 seconds
Started Feb 18 02:53:42 PM PST 24
Finished Feb 18 02:55:02 PM PST 24
Peak memory 273324 kb
Host smart-d0dd646b-d5df-4335-8df4-69c2d2f833cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834573000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3834573000
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.4028028171
Short name T1019
Test name
Test status
Simulation time 41952900 ps
CPU time 14.39 seconds
Started Feb 18 02:46:30 PM PST 24
Finished Feb 18 02:46:47 PM PST 24
Peak memory 263296 kb
Host smart-3c836d18-851e-4944-81f0-f0276079a241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028028171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.4
028028171
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.3440840125
Short name T231
Test name
Test status
Simulation time 21040900 ps
CPU time 14.31 seconds
Started Feb 18 02:46:29 PM PST 24
Finished Feb 18 02:46:46 PM PST 24
Peak memory 264264 kb
Host smart-edac5c11-8386-421d-89eb-023e92e0e08f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440840125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.3440840125
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.2891844634
Short name T666
Test name
Test status
Simulation time 41561100 ps
CPU time 13.41 seconds
Started Feb 18 02:46:15 PM PST 24
Finished Feb 18 02:46:30 PM PST 24
Peak memory 274864 kb
Host smart-0902590a-6fb9-4617-9d9c-d03a95f40b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891844634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2891844634
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.1549028614
Short name T717
Test name
Test status
Simulation time 129179600 ps
CPU time 106.79 seconds
Started Feb 18 02:45:58 PM PST 24
Finished Feb 18 02:47:46 PM PST 24
Peak memory 272104 kb
Host smart-98c4886c-2ce4-43b0-a1c3-cf4737d0576e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549028614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.1549028614
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.2686673736
Short name T428
Test name
Test status
Simulation time 34776200 ps
CPU time 22.51 seconds
Started Feb 18 02:46:23 PM PST 24
Finished Feb 18 02:46:48 PM PST 24
Peak memory 264460 kb
Host smart-b26839ba-aed5-47dd-8356-58509762ea03
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686673736 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.2686673736
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.3838920411
Short name T603
Test name
Test status
Simulation time 1483675800 ps
CPU time 298.14 seconds
Started Feb 18 02:45:40 PM PST 24
Finished Feb 18 02:50:40 PM PST 24
Peak memory 261880 kb
Host smart-3a266176-867b-4326-b9ec-6484a3695a13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3838920411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.3838920411
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.4062282561
Short name T741
Test name
Test status
Simulation time 71362645300 ps
CPU time 2462.36 seconds
Started Feb 18 02:45:46 PM PST 24
Finished Feb 18 03:26:51 PM PST 24
Peak memory 264316 kb
Host smart-a061f91c-89a6-4881-ad24-2ae72e617ebe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062282561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.4062282561
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.1158103741
Short name T941
Test name
Test status
Simulation time 9683733600 ps
CPU time 3003.5 seconds
Started Feb 18 02:45:45 PM PST 24
Finished Feb 18 03:35:50 PM PST 24
Peak memory 264036 kb
Host smart-30e2b2a9-8efa-4da2-97f8-602fc8b6caf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158103741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.1158103741
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.3957607313
Short name T510
Test name
Test status
Simulation time 6954353800 ps
CPU time 794.3 seconds
Started Feb 18 02:45:46 PM PST 24
Finished Feb 18 02:59:02 PM PST 24
Peak memory 264280 kb
Host smart-ee3a5d25-4396-468c-b85a-e45b80de8f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957607313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3957607313
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.2117526461
Short name T582
Test name
Test status
Simulation time 1589557000 ps
CPU time 24.97 seconds
Started Feb 18 02:45:39 PM PST 24
Finished Feb 18 02:46:06 PM PST 24
Peak memory 264316 kb
Host smart-10f844ee-09d7-4908-b167-d03c4b47f7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117526461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.2117526461
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.260542070
Short name T19
Test name
Test status
Simulation time 590415100 ps
CPU time 35.38 seconds
Started Feb 18 02:46:20 PM PST 24
Finished Feb 18 02:46:59 PM PST 24
Peak memory 275268 kb
Host smart-fd9ae12a-6a62-4aa6-a5aa-3cb58369302a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260542070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_fs_sup.260542070
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1882808154
Short name T982
Test name
Test status
Simulation time 297843450300 ps
CPU time 1756.03 seconds
Started Feb 18 02:45:40 PM PST 24
Finished Feb 18 03:15:00 PM PST 24
Peak memory 264036 kb
Host smart-e78c4ccc-d537-40f0-9c08-0a5620482327
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882808154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.1882808154
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.601279518
Short name T243
Test name
Test status
Simulation time 660391900 ps
CPU time 116.43 seconds
Started Feb 18 02:45:40 PM PST 24
Finished Feb 18 02:47:39 PM PST 24
Peak memory 261416 kb
Host smart-7e29aa48-94be-45c3-b088-ddc7b5a0c5e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601279518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.601279518
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1671148402
Short name T95
Test name
Test status
Simulation time 10012285100 ps
CPU time 302.78 seconds
Started Feb 18 02:46:29 PM PST 24
Finished Feb 18 02:51:34 PM PST 24
Peak memory 306384 kb
Host smart-f4ba3f9f-cea4-4af6-ae10-5ad6d9ee39a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671148402 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1671148402
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.1854510473
Short name T242
Test name
Test status
Simulation time 25445200 ps
CPU time 13.74 seconds
Started Feb 18 02:46:30 PM PST 24
Finished Feb 18 02:46:46 PM PST 24
Peak memory 263620 kb
Host smart-f571509c-68b6-4175-8470-2130093176bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854510473 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.1854510473
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.3866996055
Short name T862
Test name
Test status
Simulation time 18975274700 ps
CPU time 143.02 seconds
Started Feb 18 02:45:38 PM PST 24
Finished Feb 18 02:48:03 PM PST 24
Peak memory 261376 kb
Host smart-67f53d2c-3d24-487d-b0fb-c75e9c60f00e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866996055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.3866996055
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.262554332
Short name T227
Test name
Test status
Simulation time 16888362800 ps
CPU time 606.91 seconds
Started Feb 18 02:46:10 PM PST 24
Finished Feb 18 02:56:18 PM PST 24
Peak memory 332212 kb
Host smart-e3cd93b9-9042-4764-b5d7-38665c1f55e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262554332 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.flash_ctrl_integrity.262554332
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.2536568406
Short name T970
Test name
Test status
Simulation time 1258407700 ps
CPU time 174.78 seconds
Started Feb 18 02:46:08 PM PST 24
Finished Feb 18 02:49:06 PM PST 24
Peak memory 289056 kb
Host smart-9590b46e-7815-477f-a175-5bdce2859542
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536568406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.2536568406
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3420135113
Short name T370
Test name
Test status
Simulation time 19045990100 ps
CPU time 215.55 seconds
Started Feb 18 02:46:08 PM PST 24
Finished Feb 18 02:49:46 PM PST 24
Peak memory 290060 kb
Host smart-00fe198e-a361-467d-9aba-ad51e4f799bb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420135113 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3420135113
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.1099785008
Short name T806
Test name
Test status
Simulation time 5161408500 ps
CPU time 126.26 seconds
Started Feb 18 02:46:07 PM PST 24
Finished Feb 18 02:48:15 PM PST 24
Peak memory 264332 kb
Host smart-b559184a-333f-470b-87b3-52fcd15dbf5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099785008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.1099785008
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1112785702
Short name T451
Test name
Test status
Simulation time 52304542200 ps
CPU time 377.99 seconds
Started Feb 18 02:46:08 PM PST 24
Finished Feb 18 02:52:29 PM PST 24
Peak memory 264380 kb
Host smart-82a9a3b9-ac18-4531-bbaa-f81ea7157d73
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111
2785702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1112785702
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2945238216
Short name T1000
Test name
Test status
Simulation time 3245001000 ps
CPU time 69.91 seconds
Started Feb 18 02:45:49 PM PST 24
Finished Feb 18 02:47:01 PM PST 24
Peak memory 259520 kb
Host smart-314376a2-61bf-4396-b1f7-905783e9e4c3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945238216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2945238216
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.4098314184
Short name T260
Test name
Test status
Simulation time 15747400 ps
CPU time 13.52 seconds
Started Feb 18 02:46:28 PM PST 24
Finished Feb 18 02:46:43 PM PST 24
Peak memory 264292 kb
Host smart-030aca84-d4ec-45c6-9635-178b41bbe44b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098314184 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.4098314184
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.1756459640
Short name T57
Test name
Test status
Simulation time 2348660700 ps
CPU time 68.93 seconds
Started Feb 18 02:45:45 PM PST 24
Finished Feb 18 02:46:56 PM PST 24
Peak memory 259680 kb
Host smart-acfd20ea-8cc9-4c01-86cc-1fc2fd96c7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756459640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.1756459640
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.2786753189
Short name T790
Test name
Test status
Simulation time 10301794600 ps
CPU time 165.41 seconds
Started Feb 18 02:46:10 PM PST 24
Finished Feb 18 02:48:57 PM PST 24
Peak memory 280900 kb
Host smart-9a4f6907-9bcc-4816-99bc-d905b9556581
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786753189 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.2786753189
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.64838433
Short name T132
Test name
Test status
Simulation time 15442300 ps
CPU time 14.01 seconds
Started Feb 18 02:46:29 PM PST 24
Finished Feb 18 02:46:45 PM PST 24
Peak memory 277040 kb
Host smart-8a950544-8832-4d9c-9a66-9662e247717d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=64838433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.64838433
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.810217289
Short name T855
Test name
Test status
Simulation time 144560200 ps
CPU time 399.3 seconds
Started Feb 18 02:45:38 PM PST 24
Finished Feb 18 02:52:18 PM PST 24
Peak memory 260632 kb
Host smart-062b7f6b-3b92-4725-ae8a-a8f8cf697765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810217289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.810217289
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.4259332889
Short name T1005
Test name
Test status
Simulation time 755220200 ps
CPU time 45.78 seconds
Started Feb 18 02:46:28 PM PST 24
Finished Feb 18 02:47:15 PM PST 24
Peak memory 263364 kb
Host smart-88066fd7-8212-4b67-9274-772cb6ae1c38
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259332889 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.4259332889
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.889160834
Short name T715
Test name
Test status
Simulation time 14721400 ps
CPU time 14.78 seconds
Started Feb 18 02:46:23 PM PST 24
Finished Feb 18 02:46:40 PM PST 24
Peak memory 264556 kb
Host smart-ff44028d-44ac-4fad-87a7-cfd24de56fe4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889160834 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.889160834
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.93924595
Short name T795
Test name
Test status
Simulation time 77505300 ps
CPU time 13.7 seconds
Started Feb 18 02:46:08 PM PST 24
Finished Feb 18 02:46:24 PM PST 24
Peak memory 264348 kb
Host smart-ea8fdd22-7224-4e48-b710-555cfdc3b671
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93924595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset
.93924595
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.3964512270
Short name T944
Test name
Test status
Simulation time 108371100 ps
CPU time 396.91 seconds
Started Feb 18 02:45:38 PM PST 24
Finished Feb 18 02:52:16 PM PST 24
Peak memory 280636 kb
Host smart-065efc14-173e-47fb-bdea-e202339fd98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964512270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.3964512270
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.2279562972
Short name T886
Test name
Test status
Simulation time 734842500 ps
CPU time 152.45 seconds
Started Feb 18 02:45:39 PM PST 24
Finished Feb 18 02:48:12 PM PST 24
Peak memory 264312 kb
Host smart-2e5b0a23-ec2e-431f-b7b7-253464e46769
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2279562972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.2279562972
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.2019653351
Short name T612
Test name
Test status
Simulation time 74034200 ps
CPU time 32.76 seconds
Started Feb 18 02:46:22 PM PST 24
Finished Feb 18 02:46:58 PM PST 24
Peak memory 273644 kb
Host smart-fd1816ca-3a10-4afb-9834-5d7c19997ae7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019653351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.2019653351
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3799742652
Short name T730
Test name
Test status
Simulation time 31480500 ps
CPU time 23.11 seconds
Started Feb 18 02:45:57 PM PST 24
Finished Feb 18 02:46:22 PM PST 24
Peak memory 264404 kb
Host smart-2f2b5bd6-ccf4-4618-b2d4-f7dd3f4bc828
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799742652 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3799742652
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2541591516
Short name T542
Test name
Test status
Simulation time 45679500 ps
CPU time 21.65 seconds
Started Feb 18 02:45:54 PM PST 24
Finished Feb 18 02:46:17 PM PST 24
Peak memory 264476 kb
Host smart-51ba3f28-72d1-408f-a2be-c6d45cab0f78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541591516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.2541591516
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.4015994976
Short name T562
Test name
Test status
Simulation time 1796312700 ps
CPU time 134.32 seconds
Started Feb 18 02:45:52 PM PST 24
Finished Feb 18 02:48:08 PM PST 24
Peak memory 280820 kb
Host smart-7761beba-920f-4cdf-96c2-239854cfd5bd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015994976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_ro.4015994976
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.108665028
Short name T586
Test name
Test status
Simulation time 1887252400 ps
CPU time 140.64 seconds
Started Feb 18 02:45:57 PM PST 24
Finished Feb 18 02:48:20 PM PST 24
Peak memory 280932 kb
Host smart-9a3b5ced-d1cb-4354-99e7-6d72ace4558f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
108665028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.108665028
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.1925879225
Short name T481
Test name
Test status
Simulation time 574612400 ps
CPU time 131.94 seconds
Started Feb 18 02:45:51 PM PST 24
Finished Feb 18 02:48:05 PM PST 24
Peak memory 280880 kb
Host smart-ab700af8-e10c-47bd-9b52-447693481b74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925879225 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.1925879225
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.2289020888
Short name T760
Test name
Test status
Simulation time 5423422100 ps
CPU time 428.61 seconds
Started Feb 18 02:45:55 PM PST 24
Finished Feb 18 02:53:05 PM PST 24
Peak memory 308344 kb
Host smart-f6e864cf-3ccb-4751-9c2d-89da43dcada5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289020888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw.2289020888
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.3918115846
Short name T523
Test name
Test status
Simulation time 24793286600 ps
CPU time 649.18 seconds
Started Feb 18 02:45:57 PM PST 24
Finished Feb 18 02:56:49 PM PST 24
Peak memory 336412 kb
Host smart-12b15865-e57b-43b2-8168-b69462574904
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918115846 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.3918115846
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.2807802200
Short name T488
Test name
Test status
Simulation time 112697300 ps
CPU time 31.9 seconds
Started Feb 18 02:46:20 PM PST 24
Finished Feb 18 02:46:56 PM PST 24
Peak memory 272732 kb
Host smart-a97415e9-79f8-416b-a2cd-dc57ca9e434b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807802200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.2807802200
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.147845148
Short name T301
Test name
Test status
Simulation time 274620900 ps
CPU time 37.2 seconds
Started Feb 18 02:46:12 PM PST 24
Finished Feb 18 02:46:50 PM PST 24
Peak memory 273748 kb
Host smart-7d788fcb-f16d-4729-8a59-4b1975657870
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147845148 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.147845148
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.36290839
Short name T404
Test name
Test status
Simulation time 6978607100 ps
CPU time 622.16 seconds
Started Feb 18 02:45:54 PM PST 24
Finished Feb 18 02:56:18 PM PST 24
Peak memory 310988 kb
Host smart-f45d670b-774a-4076-af1c-bc7c63874927
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36290839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash
_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_ser
r.36290839
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.2584113406
Short name T16
Test name
Test status
Simulation time 2578504400 ps
CPU time 4867.89 seconds
Started Feb 18 02:46:21 PM PST 24
Finished Feb 18 04:07:33 PM PST 24
Peak memory 285196 kb
Host smart-b1221ec1-366e-4d89-9637-bee413aa7864
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584113406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2584113406
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.1833236875
Short name T343
Test name
Test status
Simulation time 4860741700 ps
CPU time 69.21 seconds
Started Feb 18 02:46:15 PM PST 24
Finished Feb 18 02:47:25 PM PST 24
Peak memory 264228 kb
Host smart-7a8226f8-4684-4447-b06c-79e0f13431c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833236875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1833236875
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.939590075
Short name T879
Test name
Test status
Simulation time 414547900 ps
CPU time 60.22 seconds
Started Feb 18 02:45:51 PM PST 24
Finished Feb 18 02:46:53 PM PST 24
Peak memory 272652 kb
Host smart-fb37939c-da4a-4cd9-81d3-5303486b320a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939590075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_serr_address.939590075
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.409136576
Short name T515
Test name
Test status
Simulation time 2489700000 ps
CPU time 73.91 seconds
Started Feb 18 02:45:53 PM PST 24
Finished Feb 18 02:47:08 PM PST 24
Peak memory 274376 kb
Host smart-a11b41bb-cb38-43d6-8cd4-043af1da5e70
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409136576 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_counter.409136576
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.2979819604
Short name T490
Test name
Test status
Simulation time 588911700 ps
CPU time 146.58 seconds
Started Feb 18 02:45:40 PM PST 24
Finished Feb 18 02:48:10 PM PST 24
Peak memory 274928 kb
Host smart-b46eb29a-0837-4ff8-9622-e429eaedef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979819604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.2979819604
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.380338443
Short name T21
Test name
Test status
Simulation time 28757300 ps
CPU time 24.34 seconds
Started Feb 18 02:45:39 PM PST 24
Finished Feb 18 02:46:05 PM PST 24
Peak memory 258208 kb
Host smart-d323ae55-cd43-46ba-8ff0-6727f3fa8c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380338443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.380338443
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.695016166
Short name T719
Test name
Test status
Simulation time 1032951200 ps
CPU time 1285.03 seconds
Started Feb 18 02:46:17 PM PST 24
Finished Feb 18 03:07:47 PM PST 24
Peak memory 287044 kb
Host smart-6656583b-b407-4934-975d-a301aef109c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695016166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress
_all.695016166
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3161025945
Short name T469
Test name
Test status
Simulation time 286212500 ps
CPU time 26.68 seconds
Started Feb 18 02:45:38 PM PST 24
Finished Feb 18 02:46:06 PM PST 24
Peak memory 258536 kb
Host smart-9a59db12-afa9-4a1b-8d1e-aa69a41afe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161025945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3161025945
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.657858703
Short name T142
Test name
Test status
Simulation time 3435106200 ps
CPU time 159.94 seconds
Started Feb 18 02:45:48 PM PST 24
Finished Feb 18 02:48:30 PM PST 24
Peak memory 264300 kb
Host smart-ac67680c-f8e5-4938-b6a3-3a805a1f6b11
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657858703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_wo.657858703
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.69863869
Short name T477
Test name
Test status
Simulation time 19944300 ps
CPU time 13.59 seconds
Started Feb 18 02:53:48 PM PST 24
Finished Feb 18 02:54:05 PM PST 24
Peak memory 264144 kb
Host smart-a83ef24a-55f4-4107-ba38-2b44a1a63686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69863869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.69863869
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.1375576172
Short name T996
Test name
Test status
Simulation time 49261600 ps
CPU time 16.15 seconds
Started Feb 18 02:53:46 PM PST 24
Finished Feb 18 02:54:06 PM PST 24
Peak memory 273804 kb
Host smart-b0ccdd49-d4d7-45e0-856e-909c23dab8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375576172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1375576172
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.2966952200
Short name T758
Test name
Test status
Simulation time 2544488500 ps
CPU time 71.96 seconds
Started Feb 18 02:53:43 PM PST 24
Finished Feb 18 02:54:59 PM PST 24
Peak memory 258148 kb
Host smart-7b616689-abe8-4eba-abcd-7de4b80358c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966952200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.2966952200
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.3510739482
Short name T834
Test name
Test status
Simulation time 1195095000 ps
CPU time 177.6 seconds
Started Feb 18 02:53:42 PM PST 24
Finished Feb 18 02:56:44 PM PST 24
Peak memory 293188 kb
Host smart-62ca45f1-102d-46da-a579-0c4cd42ee509
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510739482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.3510739482
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.198028731
Short name T445
Test name
Test status
Simulation time 34416333000 ps
CPU time 237.84 seconds
Started Feb 18 02:53:43 PM PST 24
Finished Feb 18 02:57:45 PM PST 24
Peak memory 292608 kb
Host smart-86f4dd6e-2936-4c88-b355-b725b1eefa3f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198028731 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.198028731
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.3483170756
Short name T251
Test name
Test status
Simulation time 41323300 ps
CPU time 31.39 seconds
Started Feb 18 02:53:40 PM PST 24
Finished Feb 18 02:54:16 PM PST 24
Peak memory 273736 kb
Host smart-8d67d3c8-24f3-47b2-bb85-050f8a6c0cdc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483170756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.3483170756
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.186213800
Short name T1014
Test name
Test status
Simulation time 3922331800 ps
CPU time 64.76 seconds
Started Feb 18 02:53:49 PM PST 24
Finished Feb 18 02:54:56 PM PST 24
Peak memory 263220 kb
Host smart-42254059-c335-44b7-b108-ee6d95e4dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186213800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.186213800
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.4281296368
Short name T29
Test name
Test status
Simulation time 20633700 ps
CPU time 99.75 seconds
Started Feb 18 02:53:41 PM PST 24
Finished Feb 18 02:55:25 PM PST 24
Peak memory 275100 kb
Host smart-5aa5cb2f-2dfb-4e6d-8ea4-e83028dfb2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281296368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.4281296368
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.957670449
Short name T928
Test name
Test status
Simulation time 47979800 ps
CPU time 14.14 seconds
Started Feb 18 02:53:48 PM PST 24
Finished Feb 18 02:54:05 PM PST 24
Peak memory 264000 kb
Host smart-ed699069-ae99-430b-add9-575ada73d55f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957670449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.957670449
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3513132617
Short name T177
Test name
Test status
Simulation time 47271900 ps
CPU time 13.39 seconds
Started Feb 18 02:53:46 PM PST 24
Finished Feb 18 02:54:03 PM PST 24
Peak memory 274036 kb
Host smart-72a4b37f-a26d-4e6e-9386-a15230b6c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513132617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3513132617
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.1526226991
Short name T107
Test name
Test status
Simulation time 57354400 ps
CPU time 22.18 seconds
Started Feb 18 02:53:46 PM PST 24
Finished Feb 18 02:54:11 PM PST 24
Peak memory 272668 kb
Host smart-5369eb77-42ce-4a13-8f56-a6484554129b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526226991 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.1526226991
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.1047784511
Short name T381
Test name
Test status
Simulation time 6680161500 ps
CPU time 103.41 seconds
Started Feb 18 02:53:50 PM PST 24
Finished Feb 18 02:55:35 PM PST 24
Peak memory 261432 kb
Host smart-c5658f81-ffe3-43f4-bffc-a4ffdf8adbde
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047784511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.1047784511
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2026967425
Short name T61
Test name
Test status
Simulation time 8379812700 ps
CPU time 195.04 seconds
Started Feb 18 02:53:44 PM PST 24
Finished Feb 18 02:57:03 PM PST 24
Peak memory 283864 kb
Host smart-df0d85c4-630c-42cf-9a83-c5b56427cffd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026967425 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.2026967425
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.1398420608
Short name T482
Test name
Test status
Simulation time 89362000 ps
CPU time 31.48 seconds
Started Feb 18 02:53:45 PM PST 24
Finished Feb 18 02:54:20 PM PST 24
Peak memory 273740 kb
Host smart-1d8f110e-df67-4a82-9070-9e31dafb0b36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398420608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.1398420608
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2833224782
Short name T40
Test name
Test status
Simulation time 70065300 ps
CPU time 31.17 seconds
Started Feb 18 02:53:47 PM PST 24
Finished Feb 18 02:54:21 PM PST 24
Peak memory 271644 kb
Host smart-93b2884d-fbdc-4e62-8144-07a7d6839aa0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833224782 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.2833224782
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.2256808185
Short name T1016
Test name
Test status
Simulation time 30310148400 ps
CPU time 92.45 seconds
Started Feb 18 02:53:48 PM PST 24
Finished Feb 18 02:55:23 PM PST 24
Peak memory 263412 kb
Host smart-1606181e-9623-4d5b-a883-8082be82f7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256808185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2256808185
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1390203051
Short name T796
Test name
Test status
Simulation time 76887600 ps
CPU time 123.5 seconds
Started Feb 18 02:53:45 PM PST 24
Finished Feb 18 02:55:52 PM PST 24
Peak memory 274584 kb
Host smart-99864f28-d39e-4e81-a747-ec8b31ca52a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390203051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1390203051
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.3840466935
Short name T902
Test name
Test status
Simulation time 63528800 ps
CPU time 13.71 seconds
Started Feb 18 02:53:51 PM PST 24
Finished Feb 18 02:54:07 PM PST 24
Peak memory 263656 kb
Host smart-4e236b94-6a6d-4b4f-83c2-4467519a7d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840466935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
3840466935
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.3431748951
Short name T837
Test name
Test status
Simulation time 43178200 ps
CPU time 16.01 seconds
Started Feb 18 02:53:52 PM PST 24
Finished Feb 18 02:54:10 PM PST 24
Peak memory 283136 kb
Host smart-9709f898-8fbc-45eb-ab20-7ef3069e5a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431748951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.3431748951
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.1845518781
Short name T992
Test name
Test status
Simulation time 21585500 ps
CPU time 22.04 seconds
Started Feb 18 02:53:53 PM PST 24
Finished Feb 18 02:54:17 PM PST 24
Peak memory 279808 kb
Host smart-56479feb-632c-42b5-8988-5c14fe41a461
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845518781 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.1845518781
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.268524614
Short name T374
Test name
Test status
Simulation time 10538215700 ps
CPU time 102.14 seconds
Started Feb 18 02:53:53 PM PST 24
Finished Feb 18 02:55:37 PM PST 24
Peak memory 261088 kb
Host smart-9979d0d6-0fac-4fa9-b7c9-31f7ee398147
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268524614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_h
w_sec_otp.268524614
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.2704004229
Short name T182
Test name
Test status
Simulation time 1128299200 ps
CPU time 155.97 seconds
Started Feb 18 02:53:52 PM PST 24
Finished Feb 18 02:56:30 PM PST 24
Peak memory 293200 kb
Host smart-aff54fe0-16c5-4092-ab60-ba9e331806b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704004229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.2704004229
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1686606658
Short name T455
Test name
Test status
Simulation time 109309425800 ps
CPU time 272.14 seconds
Started Feb 18 02:53:52 PM PST 24
Finished Feb 18 02:58:26 PM PST 24
Peak memory 283668 kb
Host smart-e8d78a39-d473-48a0-8b6a-8d0da45b87e9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686606658 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1686606658
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.2496755177
Short name T956
Test name
Test status
Simulation time 60465700 ps
CPU time 35.07 seconds
Started Feb 18 02:53:53 PM PST 24
Finished Feb 18 02:54:30 PM PST 24
Peak memory 265524 kb
Host smart-d9a13bb2-b38d-4897-bcfe-6e308892ef8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496755177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.2496755177
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.2841787160
Short name T675
Test name
Test status
Simulation time 51246700 ps
CPU time 31.85 seconds
Started Feb 18 02:53:50 PM PST 24
Finished Feb 18 02:54:24 PM PST 24
Peak memory 265504 kb
Host smart-674ec1fb-16fc-48dd-8369-6de4b83770df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841787160 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.2841787160
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.2418398579
Short name T467
Test name
Test status
Simulation time 62287400 ps
CPU time 122.16 seconds
Started Feb 18 02:53:50 PM PST 24
Finished Feb 18 02:55:54 PM PST 24
Peak memory 274292 kb
Host smart-6b0b9a78-76be-470d-aa94-68556330e129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418398579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.2418398579
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.1361268130
Short name T438
Test name
Test status
Simulation time 322524900 ps
CPU time 14.15 seconds
Started Feb 18 02:53:57 PM PST 24
Finished Feb 18 02:54:13 PM PST 24
Peak memory 263928 kb
Host smart-f700d4f8-a7bc-483d-b0ea-78dccf49f5e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361268130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
1361268130
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.1953554357
Short name T424
Test name
Test status
Simulation time 55196000 ps
CPU time 13.33 seconds
Started Feb 18 02:53:58 PM PST 24
Finished Feb 18 02:54:12 PM PST 24
Peak memory 274796 kb
Host smart-ce711683-64e1-45ea-bd5d-f25c8e90ae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953554357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1953554357
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.3630070413
Short name T773
Test name
Test status
Simulation time 2579189300 ps
CPU time 83.57 seconds
Started Feb 18 02:54:07 PM PST 24
Finished Feb 18 02:55:32 PM PST 24
Peak memory 261324 kb
Host smart-4ef4e656-b60a-4599-8000-193141aa127f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630070413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.3630070413
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.3901456820
Short name T657
Test name
Test status
Simulation time 4037755400 ps
CPU time 176.64 seconds
Started Feb 18 02:53:53 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 291612 kb
Host smart-d1d13fb4-7acb-472f-aee5-09d0c60c9d3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901456820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.3901456820
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.4147642663
Short name T870
Test name
Test status
Simulation time 8869234800 ps
CPU time 204.9 seconds
Started Feb 18 02:53:57 PM PST 24
Finished Feb 18 02:57:23 PM PST 24
Peak memory 292128 kb
Host smart-82c7fe5b-7326-4bee-af19-d66a3f224a71
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147642663 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.4147642663
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.2955448310
Short name T99
Test name
Test status
Simulation time 41372600 ps
CPU time 136.62 seconds
Started Feb 18 02:53:50 PM PST 24
Finished Feb 18 02:56:09 PM PST 24
Peak memory 258676 kb
Host smart-7696ef7f-4eb2-4073-9e84-bc384ba6f9e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955448310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.2955448310
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.3068306533
Short name T386
Test name
Test status
Simulation time 30798000 ps
CPU time 32.15 seconds
Started Feb 18 02:53:51 PM PST 24
Finished Feb 18 02:54:25 PM PST 24
Peak memory 274804 kb
Host smart-a624cc74-3a4b-4053-b659-52f801f8f32a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068306533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.3068306533
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.592111277
Short name T899
Test name
Test status
Simulation time 51333000 ps
CPU time 32.2 seconds
Started Feb 18 02:53:52 PM PST 24
Finished Feb 18 02:54:26 PM PST 24
Peak memory 272740 kb
Host smart-899a436b-35b1-4c71-85af-98c273628bef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592111277 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.592111277
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.2647776215
Short name T217
Test name
Test status
Simulation time 6462360000 ps
CPU time 88.46 seconds
Started Feb 18 02:54:01 PM PST 24
Finished Feb 18 02:55:31 PM PST 24
Peak memory 263732 kb
Host smart-01f76014-b530-4468-a13b-ffa65c728aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647776215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.2647776215
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.4171728087
Short name T798
Test name
Test status
Simulation time 25707200 ps
CPU time 170.47 seconds
Started Feb 18 02:53:53 PM PST 24
Finished Feb 18 02:56:45 PM PST 24
Peak memory 277476 kb
Host smart-c14202e6-159d-4100-950b-d3fedcf61626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171728087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.4171728087
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2024897714
Short name T684
Test name
Test status
Simulation time 53207700 ps
CPU time 13.76 seconds
Started Feb 18 02:54:07 PM PST 24
Finished Feb 18 02:54:22 PM PST 24
Peak memory 264228 kb
Host smart-fab6b06f-1836-467c-8f4f-f9800ddcf15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024897714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2024897714
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.591990706
Short name T910
Test name
Test status
Simulation time 14090800 ps
CPU time 16.04 seconds
Started Feb 18 02:54:16 PM PST 24
Finished Feb 18 02:54:32 PM PST 24
Peak memory 274124 kb
Host smart-2991cb2c-0c32-4c48-9604-554a5a77c8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591990706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.591990706
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.1259846631
Short name T199
Test name
Test status
Simulation time 56401300 ps
CPU time 22.17 seconds
Started Feb 18 02:54:06 PM PST 24
Finished Feb 18 02:54:30 PM PST 24
Peak memory 279676 kb
Host smart-1837f1a2-c58b-417f-99d2-740903f964bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259846631 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.1259846631
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3106194618
Short name T289
Test name
Test status
Simulation time 2365940200 ps
CPU time 167.05 seconds
Started Feb 18 02:54:01 PM PST 24
Finished Feb 18 02:56:50 PM PST 24
Peak memory 261352 kb
Host smart-a11809e7-8eed-43bb-8fa3-b450862eb9aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106194618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.3106194618
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.488892259
Short name T368
Test name
Test status
Simulation time 4950888300 ps
CPU time 157.31 seconds
Started Feb 18 02:53:57 PM PST 24
Finished Feb 18 02:56:36 PM PST 24
Peak memory 292916 kb
Host smart-e5686797-7423-4df7-9783-22471bffcd54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488892259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flas
h_ctrl_intr_rd.488892259
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1373819547
Short name T423
Test name
Test status
Simulation time 15746424500 ps
CPU time 223.4 seconds
Started Feb 18 02:53:58 PM PST 24
Finished Feb 18 02:57:43 PM PST 24
Peak memory 291728 kb
Host smart-861cd46b-fbba-4293-bbcd-c2b27736953e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373819547 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.1373819547
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.3063950316
Short name T90
Test name
Test status
Simulation time 58810000 ps
CPU time 114.01 seconds
Started Feb 18 02:53:58 PM PST 24
Finished Feb 18 02:55:53 PM PST 24
Peak memory 262800 kb
Host smart-82e28b62-4dae-4e2d-b228-a9af49e9f54f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063950316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.3063950316
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.1479882756
Short name T577
Test name
Test status
Simulation time 28075100 ps
CPU time 31.93 seconds
Started Feb 18 02:54:07 PM PST 24
Finished Feb 18 02:54:40 PM PST 24
Peak memory 271976 kb
Host smart-b58b2c45-2ea0-4020-bee6-73a6bf11484d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479882756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.1479882756
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.3678229840
Short name T1
Test name
Test status
Simulation time 33256300 ps
CPU time 32.4 seconds
Started Feb 18 02:54:03 PM PST 24
Finished Feb 18 02:54:37 PM PST 24
Peak memory 271672 kb
Host smart-7a97a73e-0af4-4030-be2f-eceabe3e5366
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678229840 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.3678229840
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.1696199412
Short name T906
Test name
Test status
Simulation time 2826513600 ps
CPU time 70.2 seconds
Started Feb 18 02:54:06 PM PST 24
Finished Feb 18 02:55:18 PM PST 24
Peak memory 258496 kb
Host smart-144e628a-165c-4f3b-b6b7-db6816e8a8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696199412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1696199412
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.3847981749
Short name T1055
Test name
Test status
Simulation time 96253400 ps
CPU time 74.23 seconds
Started Feb 18 02:53:59 PM PST 24
Finished Feb 18 02:55:14 PM PST 24
Peak memory 274876 kb
Host smart-e4c16f7d-774f-4671-9f7f-7d91b3fbba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847981749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3847981749
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.784917865
Short name T441
Test name
Test status
Simulation time 174762900 ps
CPU time 13.78 seconds
Started Feb 18 02:54:22 PM PST 24
Finished Feb 18 02:54:39 PM PST 24
Peak memory 263788 kb
Host smart-92f961f1-5f2f-425e-a970-e7ed2b74987a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784917865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.784917865
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.3757516321
Short name T726
Test name
Test status
Simulation time 16701600 ps
CPU time 16.19 seconds
Started Feb 18 02:54:13 PM PST 24
Finished Feb 18 02:54:31 PM PST 24
Peak memory 274052 kb
Host smart-61decd74-1350-4b71-b72e-9e4a729ee191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757516321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.3757516321
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2304121047
Short name T285
Test name
Test status
Simulation time 28671414200 ps
CPU time 117.05 seconds
Started Feb 18 02:54:05 PM PST 24
Finished Feb 18 02:56:03 PM PST 24
Peak memory 261340 kb
Host smart-355ec6fd-662c-4ca9-b4f5-b30693da0f0e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304121047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.2304121047
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.1093936186
Short name T245
Test name
Test status
Simulation time 1430751800 ps
CPU time 186.44 seconds
Started Feb 18 02:54:18 PM PST 24
Finished Feb 18 02:57:27 PM PST 24
Peak memory 292496 kb
Host smart-2b73a3c0-eb71-4d71-9c0c-25a939255588
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093936186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.1093936186
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.2128996415
Short name T922
Test name
Test status
Simulation time 89547837600 ps
CPU time 196.48 seconds
Started Feb 18 02:54:13 PM PST 24
Finished Feb 18 02:57:31 PM PST 24
Peak memory 289028 kb
Host smart-a1c6edf1-9799-4f2c-b3ad-a842a97f69ed
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128996415 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.2128996415
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.968481145
Short name T724
Test name
Test status
Simulation time 32127900 ps
CPU time 30.93 seconds
Started Feb 18 02:54:12 PM PST 24
Finished Feb 18 02:54:45 PM PST 24
Peak memory 272728 kb
Host smart-c45be7a2-bae1-4135-b2a6-6784a383698f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968481145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_rw_evict.968481145
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.2000493377
Short name T700
Test name
Test status
Simulation time 42127600 ps
CPU time 28.32 seconds
Started Feb 18 02:54:16 PM PST 24
Finished Feb 18 02:54:46 PM PST 24
Peak memory 265564 kb
Host smart-cab4ce48-3d72-4669-b18e-fc4de25922fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000493377 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.2000493377
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.3907542651
Short name T457
Test name
Test status
Simulation time 8539721700 ps
CPU time 82 seconds
Started Feb 18 02:54:13 PM PST 24
Finished Feb 18 02:55:36 PM PST 24
Peak memory 263720 kb
Host smart-22bf5dea-8733-4245-b46b-fa7e50276177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907542651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3907542651
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.3669174050
Short name T555
Test name
Test status
Simulation time 106881200 ps
CPU time 199.06 seconds
Started Feb 18 02:54:07 PM PST 24
Finished Feb 18 02:57:27 PM PST 24
Peak memory 275076 kb
Host smart-8dc5ce30-c3aa-4ec4-9ca4-32cd43d415b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669174050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3669174050
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.3489580620
Short name T556
Test name
Test status
Simulation time 44508300 ps
CPU time 13.62 seconds
Started Feb 18 02:54:22 PM PST 24
Finished Feb 18 02:54:38 PM PST 24
Peak memory 263268 kb
Host smart-72948692-dbc6-4cd5-91c4-faf1ddf9ad71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489580620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
3489580620
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.592265949
Short name T932
Test name
Test status
Simulation time 13556400 ps
CPU time 16.09 seconds
Started Feb 18 02:54:16 PM PST 24
Finished Feb 18 02:54:34 PM PST 24
Peak memory 274016 kb
Host smart-ba0413e6-0361-4637-bb4a-397062b4de60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592265949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.592265949
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.144070366
Short name T34
Test name
Test status
Simulation time 15439570100 ps
CPU time 148.53 seconds
Started Feb 18 02:54:17 PM PST 24
Finished Feb 18 02:56:47 PM PST 24
Peak memory 261032 kb
Host smart-ff61222e-42cd-4e33-8e6d-6a03d324e9bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144070366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_h
w_sec_otp.144070366
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.3633524915
Short name T365
Test name
Test status
Simulation time 2424943900 ps
CPU time 175.44 seconds
Started Feb 18 02:54:20 PM PST 24
Finished Feb 18 02:57:17 PM PST 24
Peak memory 292544 kb
Host smart-c7c221bf-9391-414a-b0ac-8bf3584f7d75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633524915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.3633524915
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.1431106330
Short name T224
Test name
Test status
Simulation time 29287400 ps
CPU time 31.54 seconds
Started Feb 18 02:54:19 PM PST 24
Finished Feb 18 02:54:53 PM PST 24
Peak memory 271684 kb
Host smart-82ca0392-d79f-4c1b-828a-5e34be93bd83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431106330 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.1431106330
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.2235190170
Short name T737
Test name
Test status
Simulation time 149353600 ps
CPU time 144.75 seconds
Started Feb 18 02:54:18 PM PST 24
Finished Feb 18 02:56:45 PM PST 24
Peak memory 275108 kb
Host smart-2923e290-5699-44a0-b388-975ece72beea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235190170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2235190170
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.2255856667
Short name T468
Test name
Test status
Simulation time 113299500 ps
CPU time 13.93 seconds
Started Feb 18 02:54:27 PM PST 24
Finished Feb 18 02:54:43 PM PST 24
Peak memory 263696 kb
Host smart-9d7f1658-321e-4b3f-82f5-0814c667f973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255856667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
2255856667
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.4240999907
Short name T130
Test name
Test status
Simulation time 16590000 ps
CPU time 15.85 seconds
Started Feb 18 02:54:22 PM PST 24
Finished Feb 18 02:54:40 PM PST 24
Peak memory 274668 kb
Host smart-08ced21b-3fbb-4f5c-a622-77e4b920f63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240999907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.4240999907
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.1101115652
Short name T108
Test name
Test status
Simulation time 27708300 ps
CPU time 20.94 seconds
Started Feb 18 02:54:26 PM PST 24
Finished Feb 18 02:54:49 PM PST 24
Peak memory 272736 kb
Host smart-474ecfae-a0e9-43fa-8227-9f4325bd761f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101115652 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.1101115652
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1420879744
Short name T995
Test name
Test status
Simulation time 9367007700 ps
CPU time 73.82 seconds
Started Feb 18 02:54:17 PM PST 24
Finished Feb 18 02:55:32 PM PST 24
Peak memory 258164 kb
Host smart-b68e9f33-38c0-4e9c-9d1b-21f3dec5eace
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420879744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.1420879744
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.775480460
Short name T875
Test name
Test status
Simulation time 15344473300 ps
CPU time 219.81 seconds
Started Feb 18 02:54:19 PM PST 24
Finished Feb 18 02:58:01 PM PST 24
Peak memory 292060 kb
Host smart-be67970b-5303-4ea9-92cc-be742fbd8da0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775480460 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.775480460
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2008774729
Short name T873
Test name
Test status
Simulation time 130990900 ps
CPU time 29.52 seconds
Started Feb 18 02:54:18 PM PST 24
Finished Feb 18 02:54:49 PM PST 24
Peak memory 272696 kb
Host smart-d0dd2d0e-3e9f-42ca-802d-c9203682710f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008774729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.2008774729
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3122430823
Short name T1011
Test name
Test status
Simulation time 51768800 ps
CPU time 31.67 seconds
Started Feb 18 02:54:19 PM PST 24
Finished Feb 18 02:54:53 PM PST 24
Peak memory 272716 kb
Host smart-e289b1ca-3662-4688-958d-5192c9436460
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122430823 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3122430823
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.3179297983
Short name T607
Test name
Test status
Simulation time 775996800 ps
CPU time 58.19 seconds
Started Feb 18 02:54:23 PM PST 24
Finished Feb 18 02:55:23 PM PST 24
Peak memory 258588 kb
Host smart-587e9786-4845-4555-b6ed-6070324fd82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179297983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3179297983
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.260311318
Short name T453
Test name
Test status
Simulation time 52630900 ps
CPU time 72.86 seconds
Started Feb 18 02:54:17 PM PST 24
Finished Feb 18 02:55:31 PM PST 24
Peak memory 273876 kb
Host smart-f05d7663-25ee-47f3-af29-0d6b3400a16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260311318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.260311318
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.3298318926
Short name T382
Test name
Test status
Simulation time 44501700 ps
CPU time 13.67 seconds
Started Feb 18 02:54:27 PM PST 24
Finished Feb 18 02:54:43 PM PST 24
Peak memory 264208 kb
Host smart-43cef6aa-7a75-45c2-b126-49457b7d5dac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298318926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
3298318926
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.3583819880
Short name T845
Test name
Test status
Simulation time 15628300 ps
CPU time 15.7 seconds
Started Feb 18 02:54:29 PM PST 24
Finished Feb 18 02:54:47 PM PST 24
Peak memory 274848 kb
Host smart-479c4920-0c26-48be-858c-2f57128b8a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583819880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3583819880
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.724096778
Short name T290
Test name
Test status
Simulation time 6440137800 ps
CPU time 136.36 seconds
Started Feb 18 02:54:22 PM PST 24
Finished Feb 18 02:56:40 PM PST 24
Peak memory 261336 kb
Host smart-e947a1e9-9dc3-4acd-8a05-7155877ae7b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724096778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_h
w_sec_otp.724096778
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.3642781591
Short name T776
Test name
Test status
Simulation time 1036050900 ps
CPU time 183.04 seconds
Started Feb 18 02:54:25 PM PST 24
Finished Feb 18 02:57:30 PM PST 24
Peak memory 291688 kb
Host smart-5e8fefdb-c0e8-4e66-bc5a-03dfa0625dc1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642781591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.3642781591
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1944696630
Short name T406
Test name
Test status
Simulation time 8581078300 ps
CPU time 248.42 seconds
Started Feb 18 02:54:24 PM PST 24
Finished Feb 18 02:58:34 PM PST 24
Peak memory 291520 kb
Host smart-902d80ad-4d21-45ad-aa96-8bf8796c0ec4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944696630 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.1944696630
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1423234295
Short name T778
Test name
Test status
Simulation time 62410400 ps
CPU time 32.18 seconds
Started Feb 18 02:54:28 PM PST 24
Finished Feb 18 02:55:03 PM PST 24
Peak memory 277028 kb
Host smart-2dfd6207-8a4b-4873-92f4-f2d05061b79b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423234295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1423234295
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.144406022
Short name T302
Test name
Test status
Simulation time 34604400 ps
CPU time 32.39 seconds
Started Feb 18 02:54:30 PM PST 24
Finished Feb 18 02:55:04 PM PST 24
Peak memory 273800 kb
Host smart-2dd82a6a-044c-40ff-9c3d-3d6da7984fa0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144406022 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.144406022
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.672594118
Short name T209
Test name
Test status
Simulation time 113794800 ps
CPU time 173.84 seconds
Started Feb 18 02:54:23 PM PST 24
Finished Feb 18 02:57:20 PM PST 24
Peak memory 278696 kb
Host smart-5da361a7-81ee-4b87-ade9-8e171587837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672594118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.672594118
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.3985668313
Short name T416
Test name
Test status
Simulation time 49727200 ps
CPU time 13.84 seconds
Started Feb 18 02:54:35 PM PST 24
Finished Feb 18 02:54:50 PM PST 24
Peak memory 263832 kb
Host smart-93589acf-9b8f-40aa-a685-4a921ab09d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985668313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
3985668313
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.17849912
Short name T811
Test name
Test status
Simulation time 41812200 ps
CPU time 15.72 seconds
Started Feb 18 02:54:36 PM PST 24
Finished Feb 18 02:54:52 PM PST 24
Peak memory 274632 kb
Host smart-1f1ab929-5ecd-415b-8100-02bbc1ffd3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17849912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.17849912
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.3688968882
Short name T333
Test name
Test status
Simulation time 19534100 ps
CPU time 21.57 seconds
Started Feb 18 02:54:36 PM PST 24
Finished Feb 18 02:54:59 PM PST 24
Peak memory 279644 kb
Host smart-590edeb9-90bc-424f-9831-7a75d3cd872a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688968882 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.3688968882
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1462043393
Short name T572
Test name
Test status
Simulation time 4119861500 ps
CPU time 79.14 seconds
Started Feb 18 02:54:30 PM PST 24
Finished Feb 18 02:55:51 PM PST 24
Peak memory 261492 kb
Host smart-a15054a9-cd29-47e7-819f-366a2e9dfd53
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462043393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.1462043393
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.1242285704
Short name T985
Test name
Test status
Simulation time 8124432900 ps
CPU time 154.02 seconds
Started Feb 18 02:54:30 PM PST 24
Finished Feb 18 02:57:06 PM PST 24
Peak memory 289084 kb
Host smart-1815ad9a-a520-4ae8-9b56-ad7509453bc7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242285704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.1242285704
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2516730529
Short name T369
Test name
Test status
Simulation time 8162854400 ps
CPU time 200.2 seconds
Started Feb 18 02:54:31 PM PST 24
Finished Feb 18 02:57:53 PM PST 24
Peak memory 288996 kb
Host smart-60885eb4-49d2-407f-9ca8-e9f53aea3d40
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516730529 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.2516730529
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.2688350576
Short name T858
Test name
Test status
Simulation time 74658700 ps
CPU time 133.57 seconds
Started Feb 18 02:54:29 PM PST 24
Finished Feb 18 02:56:45 PM PST 24
Peak memory 258956 kb
Host smart-b4cf9af1-9858-42c8-9fd0-34098d0258f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688350576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.2688350576
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.1676988292
Short name T754
Test name
Test status
Simulation time 164722100 ps
CPU time 36.45 seconds
Started Feb 18 02:54:29 PM PST 24
Finished Feb 18 02:55:08 PM PST 24
Peak memory 272740 kb
Host smart-c4894d9a-23d9-4368-8b9d-099fc1c7ade7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676988292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.1676988292
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.2602326538
Short name T131
Test name
Test status
Simulation time 147833000 ps
CPU time 28.91 seconds
Started Feb 18 02:54:35 PM PST 24
Finished Feb 18 02:55:04 PM PST 24
Peak memory 273708 kb
Host smart-6b42f431-845a-4f18-9266-1ae3890fe57e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602326538 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.2602326538
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.1417375081
Short name T353
Test name
Test status
Simulation time 18473653600 ps
CPU time 66.13 seconds
Started Feb 18 02:54:34 PM PST 24
Finished Feb 18 02:55:40 PM PST 24
Peak memory 264264 kb
Host smart-0d963c7d-f453-4893-816f-41bdc1ff855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417375081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1417375081
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1076141471
Short name T592
Test name
Test status
Simulation time 68750300 ps
CPU time 125.39 seconds
Started Feb 18 02:54:29 PM PST 24
Finished Feb 18 02:56:36 PM PST 24
Peak memory 275456 kb
Host smart-b4afc34a-ff53-4295-839e-7007cc706359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076141471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1076141471
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.793414565
Short name T485
Test name
Test status
Simulation time 95450900 ps
CPU time 13.97 seconds
Started Feb 18 02:47:14 PM PST 24
Finished Feb 18 02:47:30 PM PST 24
Peak memory 263980 kb
Host smart-01b22727-ae82-4654-b601-5dfdee4e9210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793414565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.793414565
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.797661331
Short name T877
Test name
Test status
Simulation time 72764400 ps
CPU time 13.8 seconds
Started Feb 18 02:47:15 PM PST 24
Finished Feb 18 02:47:31 PM PST 24
Peak memory 263696 kb
Host smart-8b95ce65-8fff-45f9-9d17-6fb1dfce1714
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797661331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_config_regwen.797661331
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.1963993041
Short name T748
Test name
Test status
Simulation time 20297200 ps
CPU time 13.26 seconds
Started Feb 18 02:47:14 PM PST 24
Finished Feb 18 02:47:30 PM PST 24
Peak memory 274572 kb
Host smart-dee7d127-7535-4104-b583-55cf74a8a380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963993041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1963993041
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.69901747
Short name T661
Test name
Test status
Simulation time 186388700 ps
CPU time 102.83 seconds
Started Feb 18 02:46:44 PM PST 24
Finished Feb 18 02:48:29 PM PST 24
Peak memory 270672 kb
Host smart-f5db7c15-dda1-4dba-862c-77d01599144a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69901747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_derr_detect.69901747
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.611056802
Short name T202
Test name
Test status
Simulation time 17308650100 ps
CPU time 2413.63 seconds
Started Feb 18 02:46:39 PM PST 24
Finished Feb 18 03:26:54 PM PST 24
Peak memory 262612 kb
Host smart-532e3ab4-2093-41c4-9305-5de2ccae0caa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611056802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erro
r_mp.611056802
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.1360764097
Short name T140
Test name
Test status
Simulation time 796340400 ps
CPU time 2323.66 seconds
Started Feb 18 02:46:42 PM PST 24
Finished Feb 18 03:25:28 PM PST 24
Peak memory 263392 kb
Host smart-a469172f-fddf-4d19-b349-9e1c71322af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360764097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1360764097
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.599055683
Short name T394
Test name
Test status
Simulation time 725657700 ps
CPU time 768.23 seconds
Started Feb 18 02:46:38 PM PST 24
Finished Feb 18 02:59:28 PM PST 24
Peak memory 264316 kb
Host smart-831d9cdb-330a-430a-ba98-c1fa4d139538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599055683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.599055683
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.1322594416
Short name T563
Test name
Test status
Simulation time 1471652600 ps
CPU time 30.88 seconds
Started Feb 18 02:46:42 PM PST 24
Finished Feb 18 02:47:15 PM PST 24
Peak memory 264300 kb
Host smart-8bb368fb-ec0d-47ad-a2c8-e0668d9f7015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322594416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.1322594416
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.1881188366
Short name T525
Test name
Test status
Simulation time 571688000 ps
CPU time 36.34 seconds
Started Feb 18 02:47:10 PM PST 24
Finished Feb 18 02:47:51 PM PST 24
Peak memory 276100 kb
Host smart-d57861d2-6570-4393-b65e-07117f587e3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881188366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.1881188366
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.4080799492
Short name T788
Test name
Test status
Simulation time 36961300 ps
CPU time 60.18 seconds
Started Feb 18 02:46:36 PM PST 24
Finished Feb 18 02:47:39 PM PST 24
Peak memory 264032 kb
Host smart-66a57b9f-43e4-4e60-8110-0f998db1c332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080799492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.4080799492
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1810654338
Short name T100
Test name
Test status
Simulation time 10033749800 ps
CPU time 56.15 seconds
Started Feb 18 02:47:16 PM PST 24
Finished Feb 18 02:48:14 PM PST 24
Peak memory 285116 kb
Host smart-37e85422-3ec4-4368-ba24-987ed7a01af3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810654338 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1810654338
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3220817936
Short name T695
Test name
Test status
Simulation time 84681400 ps
CPU time 13.75 seconds
Started Feb 18 02:47:07 PM PST 24
Finished Feb 18 02:47:27 PM PST 24
Peak memory 264452 kb
Host smart-22675922-8e59-4345-8a99-0aec346fb880
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220817936 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3220817936
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.250079455
Short name T116
Test name
Test status
Simulation time 760454571500 ps
CPU time 1292.68 seconds
Started Feb 18 02:46:35 PM PST 24
Finished Feb 18 03:08:11 PM PST 24
Peak memory 263068 kb
Host smart-52156558-048e-46a3-9f7a-d1ffcb229bc6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250079455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_hw_rma_reset.250079455
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.1762555514
Short name T412
Test name
Test status
Simulation time 1721382200 ps
CPU time 124.54 seconds
Started Feb 18 02:46:37 PM PST 24
Finished Feb 18 02:48:44 PM PST 24
Peak memory 261508 kb
Host smart-4f7f1653-bc15-4c0d-a5d8-9e52dba44639
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762555514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.1762555514
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.3617886510
Short name T225
Test name
Test status
Simulation time 28651233200 ps
CPU time 615.39 seconds
Started Feb 18 02:46:44 PM PST 24
Finished Feb 18 02:57:02 PM PST 24
Peak memory 329644 kb
Host smart-47f66cac-e668-4f31-b1a7-2979b9351b63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617886510 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.3617886510
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2669307115
Short name T839
Test name
Test status
Simulation time 34580114700 ps
CPU time 235.93 seconds
Started Feb 18 02:46:45 PM PST 24
Finished Feb 18 02:50:43 PM PST 24
Peak memory 283776 kb
Host smart-83b841e3-0412-4080-a93b-fd9d58dc4380
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669307115 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.2669307115
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.195761489
Short name T916
Test name
Test status
Simulation time 14494054400 ps
CPU time 115.75 seconds
Started Feb 18 02:46:45 PM PST 24
Finished Feb 18 02:48:43 PM PST 24
Peak memory 264392 kb
Host smart-e57ae040-e2ae-473b-a63e-b1d95c83763a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195761489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_intr_wr.195761489
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1916001415
Short name T446
Test name
Test status
Simulation time 141608153500 ps
CPU time 359.99 seconds
Started Feb 18 02:46:57 PM PST 24
Finished Feb 18 02:53:02 PM PST 24
Peak memory 264348 kb
Host smart-eca2cba2-d88d-4415-88b6-3e6f98fde066
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191
6001415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1916001415
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.2043910029
Short name T871
Test name
Test status
Simulation time 1011932600 ps
CPU time 76.48 seconds
Started Feb 18 02:46:43 PM PST 24
Finished Feb 18 02:48:01 PM PST 24
Peak memory 262080 kb
Host smart-1ce74567-1701-444a-9025-918c385fff0a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043910029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2043910029
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.1035204052
Short name T585
Test name
Test status
Simulation time 47401100 ps
CPU time 13.58 seconds
Started Feb 18 02:47:09 PM PST 24
Finished Feb 18 02:47:28 PM PST 24
Peak memory 264316 kb
Host smart-35bc791b-aa4d-4def-9176-2026d409f231
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035204052 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.1035204052
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.4145016043
Short name T893
Test name
Test status
Simulation time 13572773200 ps
CPU time 73.5 seconds
Started Feb 18 02:46:43 PM PST 24
Finished Feb 18 02:47:58 PM PST 24
Peak memory 258808 kb
Host smart-214a16ef-54f1-440d-bcd9-a13be1bd6c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145016043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.4145016043
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.2319586962
Short name T1037
Test name
Test status
Simulation time 5731003300 ps
CPU time 158.15 seconds
Started Feb 18 02:46:42 PM PST 24
Finished Feb 18 02:49:22 PM PST 24
Peak memory 260328 kb
Host smart-5c49e60f-dc63-4b13-8889-ada4d51adadc
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319586962 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.2319586962
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2712967994
Short name T198
Test name
Test status
Simulation time 44302300 ps
CPU time 14.1 seconds
Started Feb 18 02:47:10 PM PST 24
Finished Feb 18 02:47:29 PM PST 24
Peak memory 264568 kb
Host smart-0fcf657f-ed6d-4d55-8b60-f8cfb68c72ff
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2712967994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2712967994
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.990770045
Short name T579
Test name
Test status
Simulation time 10757329100 ps
CPU time 630.31 seconds
Started Feb 18 02:46:42 PM PST 24
Finished Feb 18 02:57:14 PM PST 24
Peak memory 261280 kb
Host smart-d1504ebd-b747-414a-9c86-2bd0c4ba8438
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990770045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.990770045
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.3776958890
Short name T501
Test name
Test status
Simulation time 864911100 ps
CPU time 80.84 seconds
Started Feb 18 02:47:03 PM PST 24
Finished Feb 18 02:48:29 PM PST 24
Peak memory 264568 kb
Host smart-b06cbdf5-314a-48af-8c7b-9c2c96bd2e5f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776958890 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.3776958890
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1924242391
Short name T184
Test name
Test status
Simulation time 71313900 ps
CPU time 14.25 seconds
Started Feb 18 02:47:09 PM PST 24
Finished Feb 18 02:47:28 PM PST 24
Peak memory 263740 kb
Host smart-a582a6fb-f37b-441d-83f4-80f9ebf932cc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924242391 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1924242391
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.1994807642
Short name T974
Test name
Test status
Simulation time 67402600 ps
CPU time 15.14 seconds
Started Feb 18 02:46:51 PM PST 24
Finished Feb 18 02:47:07 PM PST 24
Peak memory 264360 kb
Host smart-3a8f457f-b419-4865-8297-90f75339bbfa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994807642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.1994807642
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.2789582532
Short name T557
Test name
Test status
Simulation time 1041082300 ps
CPU time 899.83 seconds
Started Feb 18 02:46:27 PM PST 24
Finished Feb 18 03:01:29 PM PST 24
Peak memory 282296 kb
Host smart-42bca2e0-8567-4b8f-ab76-0ab96c01cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789582532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.2789582532
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.4210428825
Short name T250
Test name
Test status
Simulation time 1469726400 ps
CPU time 119.16 seconds
Started Feb 18 02:46:42 PM PST 24
Finished Feb 18 02:48:43 PM PST 24
Peak memory 264180 kb
Host smart-f4fdcf05-6d17-4c79-8a8b-5b5514d87b93
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4210428825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.4210428825
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.3594390383
Short name T903
Test name
Test status
Simulation time 150607000 ps
CPU time 31.85 seconds
Started Feb 18 02:47:13 PM PST 24
Finished Feb 18 02:47:48 PM PST 24
Peak memory 272676 kb
Host smart-ebeabd41-2e38-4bd1-b1ae-fa35236d9cf7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594390383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.3594390383
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.2042027066
Short name T628
Test name
Test status
Simulation time 61188700 ps
CPU time 22.97 seconds
Started Feb 18 02:46:45 PM PST 24
Finished Feb 18 02:47:10 PM PST 24
Peak memory 263752 kb
Host smart-a9cbb008-fe18-4be7-b62b-48be6b88cdbf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042027066 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.2042027066
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.4076500583
Short name T973
Test name
Test status
Simulation time 42145800 ps
CPU time 23.29 seconds
Started Feb 18 02:46:46 PM PST 24
Finished Feb 18 02:47:11 PM PST 24
Peak memory 264432 kb
Host smart-288e5564-843d-42c7-9872-750d4f201d82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076500583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.4076500583
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.3348008612
Short name T575
Test name
Test status
Simulation time 880628800 ps
CPU time 113.06 seconds
Started Feb 18 02:46:40 PM PST 24
Finished Feb 18 02:48:34 PM PST 24
Peak memory 280104 kb
Host smart-8797e28d-b1b4-4b28-a61d-5c9d7c3659aa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348008612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_ro.3348008612
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.3314550394
Short name T180
Test name
Test status
Simulation time 455555600 ps
CPU time 120.56 seconds
Started Feb 18 02:46:45 PM PST 24
Finished Feb 18 02:48:47 PM PST 24
Peak memory 280936 kb
Host smart-c1fe0920-5858-4eed-ba37-b717ce829226
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3314550394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.3314550394
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.942096291
Short name T8
Test name
Test status
Simulation time 540315200 ps
CPU time 102.21 seconds
Started Feb 18 02:46:43 PM PST 24
Finished Feb 18 02:48:27 PM PST 24
Peak memory 293132 kb
Host smart-69303993-f17b-4d79-9cea-eb99fa382905
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942096291 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.942096291
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.1937919048
Short name T429
Test name
Test status
Simulation time 4148175700 ps
CPU time 691.06 seconds
Started Feb 18 02:46:38 PM PST 24
Finished Feb 18 02:58:11 PM PST 24
Peak memory 313664 kb
Host smart-ad11d7ed-642e-44f4-83e1-c211d460176d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937919048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw.1937919048
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.2003239880
Short name T125
Test name
Test status
Simulation time 5281754000 ps
CPU time 572.82 seconds
Started Feb 18 02:46:43 PM PST 24
Finished Feb 18 02:56:19 PM PST 24
Peak memory 322512 kb
Host smart-3a050cbc-566a-49f6-8395-ab3dbe46dc15
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003239880 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.2003239880
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.3913338627
Short name T889
Test name
Test status
Simulation time 34749500 ps
CPU time 32 seconds
Started Feb 18 02:47:09 PM PST 24
Finished Feb 18 02:47:46 PM PST 24
Peak memory 272688 kb
Host smart-5dd23936-6003-4fd5-a7e3-f91693ce9885
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913338627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.3913338627
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.769872329
Short name T76
Test name
Test status
Simulation time 30691800 ps
CPU time 28.65 seconds
Started Feb 18 02:47:06 PM PST 24
Finished Feb 18 02:47:40 PM PST 24
Peak memory 273720 kb
Host smart-4aec156f-322b-4cb9-84c0-4cb52f97b9d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769872329 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.769872329
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.4222007672
Short name T175
Test name
Test status
Simulation time 3146385600 ps
CPU time 4840.35 seconds
Started Feb 18 02:47:14 PM PST 24
Finished Feb 18 04:07:58 PM PST 24
Peak memory 285940 kb
Host smart-852020ab-9aa2-4263-ad63-3bec28061d97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222007672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.4222007672
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.2269810687
Short name T819
Test name
Test status
Simulation time 2921772900 ps
CPU time 71.31 seconds
Started Feb 18 02:46:45 PM PST 24
Finished Feb 18 02:47:59 PM PST 24
Peak memory 264456 kb
Host smart-62025512-3c61-4946-9e12-fb361f28ded5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269810687 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.2269810687
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.819001565
Short name T736
Test name
Test status
Simulation time 2746475600 ps
CPU time 68.08 seconds
Started Feb 18 02:46:44 PM PST 24
Finished Feb 18 02:47:54 PM PST 24
Peak memory 264524 kb
Host smart-a678e1c1-09f2-4543-851c-8383cea5ac3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819001565 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_counter.819001565
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.1731905838
Short name T380
Test name
Test status
Simulation time 93294000 ps
CPU time 98.64 seconds
Started Feb 18 02:46:29 PM PST 24
Finished Feb 18 02:48:10 PM PST 24
Peak memory 273892 kb
Host smart-b75d925d-1a2e-41ce-b5f9-6bdb9600d95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731905838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1731905838
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.3542679652
Short name T390
Test name
Test status
Simulation time 30709600 ps
CPU time 24.11 seconds
Started Feb 18 02:46:28 PM PST 24
Finished Feb 18 02:46:55 PM PST 24
Peak memory 258096 kb
Host smart-fb39ee86-bc5e-4384-af8f-be3410c13fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542679652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3542679652
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.2262054339
Short name T25
Test name
Test status
Simulation time 4533693100 ps
CPU time 741.3 seconds
Started Feb 18 02:47:07 PM PST 24
Finished Feb 18 02:59:34 PM PST 24
Peak memory 282164 kb
Host smart-9ef8d1b8-7849-46fc-9d35-530f4f791bb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262054339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.2262054339
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.704126536
Short name T644
Test name
Test status
Simulation time 35947800 ps
CPU time 26.42 seconds
Started Feb 18 02:46:36 PM PST 24
Finished Feb 18 02:47:05 PM PST 24
Peak memory 258060 kb
Host smart-7a4775c9-5680-4b74-bf2c-fcd6b4d89f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704126536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.704126536
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.700951392
Short name T1058
Test name
Test status
Simulation time 18249560600 ps
CPU time 144.72 seconds
Started Feb 18 02:46:40 PM PST 24
Finished Feb 18 02:49:05 PM PST 24
Peak memory 264324 kb
Host smart-7672a775-05d3-4948-81b2-4a12bfeca9d0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700951392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_wo.700951392
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.2526954341
Short name T907
Test name
Test status
Simulation time 386404400 ps
CPU time 14.5 seconds
Started Feb 18 02:54:35 PM PST 24
Finished Feb 18 02:54:51 PM PST 24
Peak memory 263936 kb
Host smart-937e947f-7085-40d6-a24c-924ed4098da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526954341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
2526954341
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.3810264771
Short name T373
Test name
Test status
Simulation time 15144300 ps
CPU time 13.7 seconds
Started Feb 18 02:54:35 PM PST 24
Finished Feb 18 02:54:50 PM PST 24
Peak memory 274148 kb
Host smart-d3e4456d-7f9f-4faa-8c1a-99622721fa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810264771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3810264771
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.3163608579
Short name T821
Test name
Test status
Simulation time 6456328600 ps
CPU time 141.04 seconds
Started Feb 18 02:54:41 PM PST 24
Finished Feb 18 02:57:03 PM PST 24
Peak memory 260844 kb
Host smart-712ba626-0992-40a7-903e-84ae6721cede
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163608579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.3163608579
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.2606969987
Short name T122
Test name
Test status
Simulation time 2978222100 ps
CPU time 63.66 seconds
Started Feb 18 02:54:34 PM PST 24
Finished Feb 18 02:55:38 PM PST 24
Peak memory 258484 kb
Host smart-0584b8b6-f18d-44d7-a36d-a7aae363fb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606969987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2606969987
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2649713788
Short name T392
Test name
Test status
Simulation time 26375600 ps
CPU time 100.5 seconds
Started Feb 18 02:54:34 PM PST 24
Finished Feb 18 02:56:15 PM PST 24
Peak memory 274120 kb
Host smart-dca95bb3-1f8f-481c-8ee8-e5fb2e30c0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649713788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2649713788
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.2969982973
Short name T810
Test name
Test status
Simulation time 149653300 ps
CPU time 13.72 seconds
Started Feb 18 02:54:40 PM PST 24
Finished Feb 18 02:54:55 PM PST 24
Peak memory 263668 kb
Host smart-d75aa390-cdb6-491d-aaf4-647da7fa7b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969982973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
2969982973
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.538673445
Short name T640
Test name
Test status
Simulation time 62819700 ps
CPU time 13.69 seconds
Started Feb 18 02:54:42 PM PST 24
Finished Feb 18 02:54:57 PM PST 24
Peak memory 273672 kb
Host smart-38d697ef-70eb-4c63-9153-fb3bd9384345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538673445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.538673445
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.1829197478
Short name T815
Test name
Test status
Simulation time 2835823000 ps
CPU time 89.76 seconds
Started Feb 18 02:54:39 PM PST 24
Finished Feb 18 02:56:09 PM PST 24
Peak memory 261028 kb
Host smart-d798c83a-896a-4a0d-9758-7b1bf32f1387
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829197478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.1829197478
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.237409213
Short name T929
Test name
Test status
Simulation time 376686400 ps
CPU time 53.2 seconds
Started Feb 18 02:54:40 PM PST 24
Finished Feb 18 02:55:34 PM PST 24
Peak memory 258696 kb
Host smart-153cf484-0662-45e4-bb95-2b8e83729214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237409213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.237409213
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.1389221748
Short name T774
Test name
Test status
Simulation time 124471500 ps
CPU time 125.25 seconds
Started Feb 18 02:54:41 PM PST 24
Finished Feb 18 02:56:47 PM PST 24
Peak memory 274784 kb
Host smart-5b8f77b5-fd22-4ecb-822a-2a4ebd57dbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389221748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.1389221748
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.506985870
Short name T526
Test name
Test status
Simulation time 91636700 ps
CPU time 13.88 seconds
Started Feb 18 02:54:44 PM PST 24
Finished Feb 18 02:54:58 PM PST 24
Peak memory 264176 kb
Host smart-cec4cd31-22e1-4eb2-aa86-ada3877b3b3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506985870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.506985870
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.3031018149
Short name T988
Test name
Test status
Simulation time 99029200 ps
CPU time 15.92 seconds
Started Feb 18 02:54:40 PM PST 24
Finished Feb 18 02:54:57 PM PST 24
Peak memory 274500 kb
Host smart-2a490d76-b05d-4009-93f5-930a759a791c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031018149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.3031018149
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.3505017469
Short name T694
Test name
Test status
Simulation time 38548100 ps
CPU time 22.71 seconds
Started Feb 18 02:54:39 PM PST 24
Finished Feb 18 02:55:03 PM PST 24
Peak memory 279644 kb
Host smart-99b08e72-d591-4370-a11f-a71c952d6f4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505017469 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.3505017469
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.1326842154
Short name T615
Test name
Test status
Simulation time 3177264000 ps
CPU time 242.09 seconds
Started Feb 18 02:54:41 PM PST 24
Finished Feb 18 02:58:44 PM PST 24
Peak memory 261100 kb
Host smart-0d8ed796-5ffa-4ca4-97e0-bb691c79a556
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326842154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.1326842154
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.1658421162
Short name T965
Test name
Test status
Simulation time 66198800 ps
CPU time 132.32 seconds
Started Feb 18 02:54:40 PM PST 24
Finished Feb 18 02:56:53 PM PST 24
Peak memory 258884 kb
Host smart-75d63844-8c54-41ee-8255-f636f2f1fe29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658421162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.1658421162
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.446002353
Short name T341
Test name
Test status
Simulation time 2003658000 ps
CPU time 62.72 seconds
Started Feb 18 02:54:49 PM PST 24
Finished Feb 18 02:55:54 PM PST 24
Peak memory 258712 kb
Host smart-2648ad8e-a2d1-4620-b069-bf6dcfeb46b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446002353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.446002353
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.2442435411
Short name T880
Test name
Test status
Simulation time 21248200 ps
CPU time 52.69 seconds
Started Feb 18 02:54:39 PM PST 24
Finished Feb 18 02:55:33 PM PST 24
Peak memory 269444 kb
Host smart-0ee12d57-7a9b-442c-919c-dc96f10c36a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442435411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2442435411
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.575811007
Short name T633
Test name
Test status
Simulation time 39495500 ps
CPU time 14.73 seconds
Started Feb 18 02:54:50 PM PST 24
Finished Feb 18 02:55:07 PM PST 24
Peak memory 264264 kb
Host smart-325cbc38-51de-4d71-bcff-d76f7e98fd6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575811007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.575811007
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.1934131909
Short name T971
Test name
Test status
Simulation time 24678500 ps
CPU time 16.04 seconds
Started Feb 18 02:54:51 PM PST 24
Finished Feb 18 02:55:10 PM PST 24
Peak memory 274880 kb
Host smart-57078e41-6045-4f93-ab0c-aad4c6cc5677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934131909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.1934131909
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.3569531152
Short name T957
Test name
Test status
Simulation time 28742800 ps
CPU time 22.17 seconds
Started Feb 18 02:54:57 PM PST 24
Finished Feb 18 02:55:22 PM PST 24
Peak memory 279716 kb
Host smart-5678e614-346e-4ba9-b8bb-0ccc2b2e17a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569531152 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.3569531152
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.802477875
Short name T1065
Test name
Test status
Simulation time 3586879500 ps
CPU time 101.49 seconds
Started Feb 18 02:54:40 PM PST 24
Finished Feb 18 02:56:22 PM PST 24
Peak memory 258208 kb
Host smart-2b7d7faf-362f-4f07-8db8-349873419699
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802477875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_h
w_sec_otp.802477875
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.3333606465
Short name T81
Test name
Test status
Simulation time 98596200 ps
CPU time 135.95 seconds
Started Feb 18 02:54:43 PM PST 24
Finished Feb 18 02:57:00 PM PST 24
Peak memory 258932 kb
Host smart-d8397147-a600-477a-9f9d-115e0abaf24f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333606465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.3333606465
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.1417030588
Short name T499
Test name
Test status
Simulation time 1262780900 ps
CPU time 75.93 seconds
Started Feb 18 02:54:54 PM PST 24
Finished Feb 18 02:56:12 PM PST 24
Peak memory 258600 kb
Host smart-c40f240d-e10a-47b2-a1a1-27ebf5069115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417030588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1417030588
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.1433202916
Short name T878
Test name
Test status
Simulation time 18206000 ps
CPU time 49.33 seconds
Started Feb 18 02:54:41 PM PST 24
Finished Feb 18 02:55:32 PM PST 24
Peak memory 269492 kb
Host smart-6147d20f-f90b-471c-94b2-d830b9b45278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433202916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1433202916
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.1017755215
Short name T405
Test name
Test status
Simulation time 286481800 ps
CPU time 14.05 seconds
Started Feb 18 02:54:54 PM PST 24
Finished Feb 18 02:55:10 PM PST 24
Peak memory 264212 kb
Host smart-f24d9a62-05f4-41e5-b5b3-2c050599fb8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017755215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
1017755215
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.3881103753
Short name T946
Test name
Test status
Simulation time 44675400 ps
CPU time 15.87 seconds
Started Feb 18 02:54:59 PM PST 24
Finished Feb 18 02:55:17 PM PST 24
Peak memory 274848 kb
Host smart-e299ed95-5b7f-4004-ab96-c523fa51fb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881103753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3881103753
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1657300736
Short name T1032
Test name
Test status
Simulation time 2806013100 ps
CPU time 95.23 seconds
Started Feb 18 02:54:54 PM PST 24
Finished Feb 18 02:56:33 PM PST 24
Peak memory 258196 kb
Host smart-133b06c1-06a6-483b-87e2-fd06c5fba851
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657300736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.1657300736
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.331359938
Short name T620
Test name
Test status
Simulation time 212341200 ps
CPU time 136.69 seconds
Started Feb 18 02:54:54 PM PST 24
Finished Feb 18 02:57:14 PM PST 24
Peak memory 259044 kb
Host smart-81351197-5982-4ee3-b845-3f1635b38926
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331359938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot
p_reset.331359938
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.3288628164
Short name T866
Test name
Test status
Simulation time 2028104700 ps
CPU time 75.4 seconds
Started Feb 18 02:54:56 PM PST 24
Finished Feb 18 02:56:14 PM PST 24
Peak memory 264248 kb
Host smart-3a5dd5e0-6a82-4f46-85c1-9bc7336e7953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288628164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3288628164
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.3284708385
Short name T723
Test name
Test status
Simulation time 218919300 ps
CPU time 73.83 seconds
Started Feb 18 02:54:59 PM PST 24
Finished Feb 18 02:56:15 PM PST 24
Peak memory 275116 kb
Host smart-99343d5a-44c1-4902-b567-4e617c0ea198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284708385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3284708385
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.1194734733
Short name T1051
Test name
Test status
Simulation time 28224400 ps
CPU time 13.64 seconds
Started Feb 18 02:55:04 PM PST 24
Finished Feb 18 02:55:19 PM PST 24
Peak memory 263820 kb
Host smart-fcdd8f58-bef9-4781-a093-a0075dec6e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194734733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
1194734733
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2142958318
Short name T417
Test name
Test status
Simulation time 17387700 ps
CPU time 16.31 seconds
Started Feb 18 02:54:58 PM PST 24
Finished Feb 18 02:55:17 PM PST 24
Peak memory 273716 kb
Host smart-d294fc0b-09f8-43e6-93c6-94e73de17f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142958318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2142958318
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.3796095145
Short name T531
Test name
Test status
Simulation time 3024421400 ps
CPU time 266.62 seconds
Started Feb 18 02:54:51 PM PST 24
Finished Feb 18 02:59:20 PM PST 24
Peak memory 261236 kb
Host smart-400617e8-eaf1-4ee8-a2ff-e11c491f0c9d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796095145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.3796095145
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.895092248
Short name T344
Test name
Test status
Simulation time 1740370600 ps
CPU time 64.42 seconds
Started Feb 18 02:54:58 PM PST 24
Finished Feb 18 02:56:05 PM PST 24
Peak memory 261512 kb
Host smart-c691aac4-5ec2-43d8-bc52-7b4d20ae317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895092248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.895092248
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.3978988549
Short name T743
Test name
Test status
Simulation time 21725800 ps
CPU time 75.75 seconds
Started Feb 18 02:54:58 PM PST 24
Finished Feb 18 02:56:16 PM PST 24
Peak memory 273792 kb
Host smart-2cba789b-7f13-42b4-9dbd-62b96a20debc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978988549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.3978988549
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.3888525400
Short name T395
Test name
Test status
Simulation time 73850900 ps
CPU time 13.61 seconds
Started Feb 18 02:55:04 PM PST 24
Finished Feb 18 02:55:19 PM PST 24
Peak memory 264028 kb
Host smart-a0ab347c-a0fc-40f1-a33e-d7752da50755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888525400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
3888525400
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.111537859
Short name T595
Test name
Test status
Simulation time 57987400 ps
CPU time 15.73 seconds
Started Feb 18 02:54:59 PM PST 24
Finished Feb 18 02:55:18 PM PST 24
Peak memory 273652 kb
Host smart-97d612fb-2422-4957-8e77-38ef4e40e69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111537859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.111537859
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.3488765875
Short name T334
Test name
Test status
Simulation time 10670300 ps
CPU time 21.93 seconds
Started Feb 18 02:54:59 PM PST 24
Finished Feb 18 02:55:23 PM PST 24
Peak memory 279800 kb
Host smart-7157c361-de3b-4dcc-aa4f-faf6ba381017
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488765875 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.3488765875
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.1744845925
Short name T1045
Test name
Test status
Simulation time 608825700 ps
CPU time 33.43 seconds
Started Feb 18 02:54:59 PM PST 24
Finished Feb 18 02:55:34 PM PST 24
Peak memory 261264 kb
Host smart-124c5cef-1f91-492d-a86c-df888768a172
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744845925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.1744845925
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.887184587
Short name T658
Test name
Test status
Simulation time 103675800 ps
CPU time 134.01 seconds
Started Feb 18 02:54:57 PM PST 24
Finished Feb 18 02:57:14 PM PST 24
Peak memory 263484 kb
Host smart-7ae7f332-9c11-48a1-95d8-b9fe230c79cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887184587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ot
p_reset.887184587
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.1065398757
Short name T775
Test name
Test status
Simulation time 2900938500 ps
CPU time 75.26 seconds
Started Feb 18 02:54:53 PM PST 24
Finished Feb 18 02:56:11 PM PST 24
Peak memory 258572 kb
Host smart-d5b4390b-5cd0-49b5-b2c9-32386b29f2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065398757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1065398757
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.4204174514
Short name T549
Test name
Test status
Simulation time 93473000 ps
CPU time 125.61 seconds
Started Feb 18 02:55:00 PM PST 24
Finished Feb 18 02:57:07 PM PST 24
Peak memory 277660 kb
Host smart-c0ce6894-18ce-4d36-a7e5-0fe852e9d0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204174514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.4204174514
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.3754282059
Short name T950
Test name
Test status
Simulation time 154169000 ps
CPU time 13.95 seconds
Started Feb 18 02:55:03 PM PST 24
Finished Feb 18 02:55:18 PM PST 24
Peak memory 264224 kb
Host smart-ca3e5454-910b-40f6-9ceb-923ddeec676a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754282059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
3754282059
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.999012901
Short name T848
Test name
Test status
Simulation time 74829200 ps
CPU time 16.04 seconds
Started Feb 18 02:55:09 PM PST 24
Finished Feb 18 02:55:26 PM PST 24
Peak memory 274944 kb
Host smart-a45398a2-ec62-4bd2-978d-984b2bfa735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999012901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.999012901
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.2415408100
Short name T336
Test name
Test status
Simulation time 14011600 ps
CPU time 20.77 seconds
Started Feb 18 02:54:59 PM PST 24
Finished Feb 18 02:55:23 PM PST 24
Peak memory 272724 kb
Host smart-68c0ff12-a7a7-47ec-8a24-086c4f2afa56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415408100 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.2415408100
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.3974248857
Short name T448
Test name
Test status
Simulation time 2516653700 ps
CPU time 154.05 seconds
Started Feb 18 02:54:58 PM PST 24
Finished Feb 18 02:57:35 PM PST 24
Peak memory 258352 kb
Host smart-73397080-b315-40fb-9ef4-a368544428a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974248857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.3974248857
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.1801207251
Short name T479
Test name
Test status
Simulation time 142019600 ps
CPU time 113.67 seconds
Started Feb 18 02:55:00 PM PST 24
Finished Feb 18 02:56:56 PM PST 24
Peak memory 258756 kb
Host smart-988e44b1-ab20-4d16-947c-b74a08337fb1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801207251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.1801207251
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.2209549985
Short name T767
Test name
Test status
Simulation time 8403838300 ps
CPU time 84.08 seconds
Started Feb 18 02:54:59 PM PST 24
Finished Feb 18 02:56:26 PM PST 24
Peak memory 263220 kb
Host smart-dc54e1e1-dfe9-4ee9-bc33-ff7717e469c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209549985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2209549985
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.3223686583
Short name T807
Test name
Test status
Simulation time 61216100 ps
CPU time 77.41 seconds
Started Feb 18 02:54:59 PM PST 24
Finished Feb 18 02:56:19 PM PST 24
Peak memory 274776 kb
Host smart-b2b9b15c-1829-4057-a2bc-d0ee7b8e7473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223686583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3223686583
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.177150538
Short name T884
Test name
Test status
Simulation time 41127900 ps
CPU time 13.83 seconds
Started Feb 18 02:55:05 PM PST 24
Finished Feb 18 02:55:19 PM PST 24
Peak memory 264212 kb
Host smart-15cbf0b3-ac6f-4e9b-8c79-3ef318081e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177150538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.177150538
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.2330113599
Short name T686
Test name
Test status
Simulation time 47576000 ps
CPU time 16.18 seconds
Started Feb 18 02:55:12 PM PST 24
Finished Feb 18 02:55:30 PM PST 24
Peak memory 274032 kb
Host smart-ec6c18c4-ee8e-4ce5-b543-7b1336134307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330113599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2330113599
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.482992463
Short name T284
Test name
Test status
Simulation time 4883392300 ps
CPU time 89.68 seconds
Started Feb 18 02:55:05 PM PST 24
Finished Feb 18 02:56:35 PM PST 24
Peak memory 258296 kb
Host smart-3555ff87-6529-4c97-8cb9-3bff31907a5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482992463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h
w_sec_otp.482992463
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.611415866
Short name T976
Test name
Test status
Simulation time 156226000 ps
CPU time 117.45 seconds
Started Feb 18 02:55:08 PM PST 24
Finished Feb 18 02:57:07 PM PST 24
Peak memory 258736 kb
Host smart-f9335e72-c2f3-4264-aac0-e43a95604f23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611415866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ot
p_reset.611415866
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.1814585510
Short name T1021
Test name
Test status
Simulation time 2925244300 ps
CPU time 70.05 seconds
Started Feb 18 02:55:09 PM PST 24
Finished Feb 18 02:56:20 PM PST 24
Peak memory 263232 kb
Host smart-39602b11-e4d0-4faf-b3af-0a0623b19b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814585510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1814585510
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.4194907828
Short name T682
Test name
Test status
Simulation time 77312500 ps
CPU time 191.43 seconds
Started Feb 18 02:55:04 PM PST 24
Finished Feb 18 02:58:17 PM PST 24
Peak memory 276728 kb
Host smart-9661e577-6a55-4d81-992e-a8f7ed5429e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194907828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.4194907828
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.4179035600
Short name T426
Test name
Test status
Simulation time 79635500 ps
CPU time 13.51 seconds
Started Feb 18 02:55:12 PM PST 24
Finished Feb 18 02:55:26 PM PST 24
Peak memory 263704 kb
Host smart-2adde22a-0121-401e-b82c-9af64a9d5d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179035600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
4179035600
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.2079012706
Short name T747
Test name
Test status
Simulation time 16702200 ps
CPU time 13.36 seconds
Started Feb 18 02:55:09 PM PST 24
Finished Feb 18 02:55:24 PM PST 24
Peak memory 273652 kb
Host smart-6c44c57c-f344-4601-9dac-3ff8144dd3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079012706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2079012706
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2388690463
Short name T281
Test name
Test status
Simulation time 14762037500 ps
CPU time 105.52 seconds
Started Feb 18 02:55:13 PM PST 24
Finished Feb 18 02:57:00 PM PST 24
Peak memory 261408 kb
Host smart-68209075-b8d3-4466-95a4-bd05a152ad72
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388690463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.2388690463
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.4263425411
Short name T160
Test name
Test status
Simulation time 17355021200 ps
CPU time 76.19 seconds
Started Feb 18 02:55:10 PM PST 24
Finished Feb 18 02:56:27 PM PST 24
Peak memory 263308 kb
Host smart-b571cbc6-918e-47c7-82eb-5c9373b934a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263425411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.4263425411
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.4017184144
Short name T720
Test name
Test status
Simulation time 42010500 ps
CPU time 100.52 seconds
Started Feb 18 02:55:09 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 273912 kb
Host smart-06486971-dba5-40f9-bf19-2638b88ab228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017184144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.4017184144
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.3741804048
Short name T594
Test name
Test status
Simulation time 68888300 ps
CPU time 14.19 seconds
Started Feb 18 02:47:34 PM PST 24
Finished Feb 18 02:47:48 PM PST 24
Peak memory 263832 kb
Host smart-837a071c-b3e8-4055-8046-f4bf43254954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741804048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.3
741804048
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.2700516799
Short name T437
Test name
Test status
Simulation time 32361600 ps
CPU time 16.03 seconds
Started Feb 18 02:47:29 PM PST 24
Finished Feb 18 02:47:46 PM PST 24
Peak memory 273816 kb
Host smart-5a90fc9e-6397-4db9-a0a5-51ded3b36da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700516799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.2700516799
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.1387041466
Short name T693
Test name
Test status
Simulation time 37072200 ps
CPU time 22.07 seconds
Started Feb 18 02:47:27 PM PST 24
Finished Feb 18 02:47:50 PM PST 24
Peak memory 279796 kb
Host smart-e232f94a-50c6-44c5-a0fb-07c73f58e1ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387041466 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.1387041466
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.1469292944
Short name T763
Test name
Test status
Simulation time 43460239400 ps
CPU time 2290.28 seconds
Started Feb 18 02:47:15 PM PST 24
Finished Feb 18 03:25:28 PM PST 24
Peak memory 263852 kb
Host smart-e75a226d-f4e8-48b8-a011-9343f25e8819
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469292944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.1469292944
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.2196432293
Short name T162
Test name
Test status
Simulation time 1380672400 ps
CPU time 884.11 seconds
Started Feb 18 02:47:21 PM PST 24
Finished Feb 18 03:02:07 PM PST 24
Peak memory 272512 kb
Host smart-0784f1fe-7a9c-4243-85be-a79701233164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196432293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2196432293
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.4195361332
Short name T44
Test name
Test status
Simulation time 1537385000 ps
CPU time 27.39 seconds
Started Feb 18 02:47:21 PM PST 24
Finished Feb 18 02:47:50 PM PST 24
Peak memory 264316 kb
Host smart-e81ecebf-7262-46c4-8760-4b9186bfddae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195361332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.4195361332
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.312808134
Short name T92
Test name
Test status
Simulation time 10020013700 ps
CPU time 72.79 seconds
Started Feb 18 02:47:35 PM PST 24
Finished Feb 18 02:48:50 PM PST 24
Peak memory 283884 kb
Host smart-79a6c3d0-9dac-4528-9706-35f377ad2296
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312808134 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.312808134
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.2562831951
Short name T489
Test name
Test status
Simulation time 25785400 ps
CPU time 13.73 seconds
Started Feb 18 02:47:35 PM PST 24
Finished Feb 18 02:47:51 PM PST 24
Peak memory 264380 kb
Host smart-caac8f61-f267-4eef-92c5-cf19bb9e40c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562831951 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2562831951
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.1493444959
Short name T752
Test name
Test status
Simulation time 120140762100 ps
CPU time 813.36 seconds
Started Feb 18 02:47:14 PM PST 24
Finished Feb 18 03:00:50 PM PST 24
Peak memory 262024 kb
Host smart-6e27785e-8448-4256-936b-0908a5a74728
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493444959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.1493444959
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.3951999263
Short name T540
Test name
Test status
Simulation time 918890600 ps
CPU time 54.54 seconds
Started Feb 18 02:47:20 PM PST 24
Finished Feb 18 02:48:16 PM PST 24
Peak memory 261408 kb
Host smart-1e8e1690-867a-445a-a4cb-025c4da98be6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951999263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.3951999263
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.240811950
Short name T192
Test name
Test status
Simulation time 1959542700 ps
CPU time 137.46 seconds
Started Feb 18 02:47:26 PM PST 24
Finished Feb 18 02:49:45 PM PST 24
Peak memory 289040 kb
Host smart-0c360c91-5426-4963-9d22-efc2ab5ee5fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240811950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_intr_rd.240811950
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.424836698
Short name T779
Test name
Test status
Simulation time 34006497500 ps
CPU time 233.12 seconds
Started Feb 18 02:47:30 PM PST 24
Finished Feb 18 02:51:24 PM PST 24
Peak memory 283532 kb
Host smart-40ce711b-9ae1-4f3d-8247-650fba8ae94f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424836698 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.424836698
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.766205024
Short name T363
Test name
Test status
Simulation time 5026198700 ps
CPU time 122.88 seconds
Started Feb 18 02:47:22 PM PST 24
Finished Feb 18 02:49:26 PM PST 24
Peak memory 264376 kb
Host smart-393f0a0d-bdc6-465f-a1a6-0ee60f00be2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766205024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.flash_ctrl_intr_wr.766205024
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.369463951
Short name T784
Test name
Test status
Simulation time 221914390400 ps
CPU time 795.89 seconds
Started Feb 18 02:47:22 PM PST 24
Finished Feb 18 03:00:40 PM PST 24
Peak memory 264504 kb
Host smart-8c913c0e-a347-41da-8d48-16806b89b1db
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369
463951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.369463951
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.3939965082
Short name T647
Test name
Test status
Simulation time 1977379400 ps
CPU time 65.4 seconds
Started Feb 18 02:47:27 PM PST 24
Finished Feb 18 02:48:33 PM PST 24
Peak memory 259344 kb
Host smart-c576f899-0bbc-4438-9a56-0bf3fbb3b4ab
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939965082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3939965082
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3352267821
Short name T835
Test name
Test status
Simulation time 28197200 ps
CPU time 13.36 seconds
Started Feb 18 02:47:35 PM PST 24
Finished Feb 18 02:47:49 PM PST 24
Peak memory 264288 kb
Host smart-47ae6b40-6bb6-4b4e-98d8-63f017766803
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352267821 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.3352267821
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.1966567689
Short name T1067
Test name
Test status
Simulation time 31412673200 ps
CPU time 249.76 seconds
Started Feb 18 02:47:22 PM PST 24
Finished Feb 18 02:51:33 PM PST 24
Peak memory 272752 kb
Host smart-d1a953c9-5d41-4a9c-914f-1005af3d3557
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966567689 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.1966567689
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.4137190345
Short name T123
Test name
Test status
Simulation time 55201200 ps
CPU time 238.43 seconds
Started Feb 18 02:47:15 PM PST 24
Finished Feb 18 02:51:16 PM PST 24
Peak memory 261304 kb
Host smart-0273ea3d-28be-4621-bc03-8a5e8258d041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137190345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.4137190345
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.2701278282
Short name T897
Test name
Test status
Simulation time 147631100 ps
CPU time 22.71 seconds
Started Feb 18 02:47:29 PM PST 24
Finished Feb 18 02:47:53 PM PST 24
Peak memory 264356 kb
Host smart-2e11576d-c876-49a6-a5f1-3dfcd2b72414
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701278282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.2701278282
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.633487196
Short name T757
Test name
Test status
Simulation time 829552800 ps
CPU time 877.78 seconds
Started Feb 18 02:47:08 PM PST 24
Finished Feb 18 03:01:51 PM PST 24
Peak memory 284280 kb
Host smart-937cd62f-5863-40d8-ad94-e2adb7ac8ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633487196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.633487196
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.3437565824
Short name T47
Test name
Test status
Simulation time 101525600 ps
CPU time 34.15 seconds
Started Feb 18 02:47:29 PM PST 24
Finished Feb 18 02:48:04 PM PST 24
Peak memory 272724 kb
Host smart-0ea95868-1f23-492b-b57c-c60906ee04db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437565824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.3437565824
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.3094213008
Short name T185
Test name
Test status
Simulation time 437715500 ps
CPU time 126.04 seconds
Started Feb 18 02:47:24 PM PST 24
Finished Feb 18 02:49:33 PM PST 24
Peak memory 280944 kb
Host smart-cd25426b-467e-43ae-bed4-2039421eaa0d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094213008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_ro.3094213008
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.3431154901
Short name T1064
Test name
Test status
Simulation time 541911200 ps
CPU time 132.26 seconds
Started Feb 18 02:47:28 PM PST 24
Finished Feb 18 02:49:41 PM PST 24
Peak memory 280964 kb
Host smart-26642a72-f403-4740-9812-67b203e8c13c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3431154901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.3431154901
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.2236779688
Short name T904
Test name
Test status
Simulation time 1398830700 ps
CPU time 137.36 seconds
Started Feb 18 02:47:23 PM PST 24
Finished Feb 18 02:49:43 PM PST 24
Peak memory 293216 kb
Host smart-c59e5dda-20f6-409d-858c-eff6f419038e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236779688 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2236779688
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.3474413951
Short name T574
Test name
Test status
Simulation time 11270321000 ps
CPU time 545.4 seconds
Started Feb 18 02:47:24 PM PST 24
Finished Feb 18 02:56:32 PM PST 24
Peak memory 313496 kb
Host smart-0a24c30f-ddb0-4d9f-8cdd-3ef9e4551d5d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474413951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_rw.3474413951
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.1465763243
Short name T73
Test name
Test status
Simulation time 30748100 ps
CPU time 28.63 seconds
Started Feb 18 02:47:23 PM PST 24
Finished Feb 18 02:47:54 PM PST 24
Peak memory 274756 kb
Host smart-9ec6f634-9abb-4abe-a24e-7a95e47bdc31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465763243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.1465763243
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.1993744528
Short name T190
Test name
Test status
Simulation time 44614800 ps
CPU time 31.2 seconds
Started Feb 18 02:47:29 PM PST 24
Finished Feb 18 02:48:01 PM PST 24
Peak memory 273768 kb
Host smart-16402c7f-8fa2-4738-be94-b4abd020bef2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993744528 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.1993744528
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.2504989457
Short name T249
Test name
Test status
Simulation time 4079195800 ps
CPU time 643.05 seconds
Started Feb 18 02:47:30 PM PST 24
Finished Feb 18 02:58:14 PM PST 24
Peak memory 313624 kb
Host smart-10e43cf5-9fed-48aa-b8c5-5c3039b45719
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504989457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.2504989457
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.581145420
Short name T338
Test name
Test status
Simulation time 2509279100 ps
CPU time 68.5 seconds
Started Feb 18 02:47:28 PM PST 24
Finished Feb 18 02:48:37 PM PST 24
Peak memory 263288 kb
Host smart-dd034ed5-77ea-41b3-a3ad-aebd0cc49417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581145420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.581145420
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.1309077820
Short name T1054
Test name
Test status
Simulation time 63126000 ps
CPU time 146.74 seconds
Started Feb 18 02:47:16 PM PST 24
Finished Feb 18 02:49:45 PM PST 24
Peak memory 276000 kb
Host smart-bda17dcf-6826-41a7-9b8d-46eede461c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309077820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.1309077820
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.3781960089
Short name T622
Test name
Test status
Simulation time 10414653100 ps
CPU time 219.21 seconds
Started Feb 18 02:47:22 PM PST 24
Finished Feb 18 02:51:03 PM PST 24
Peak memory 264348 kb
Host smart-22011e07-ef15-479e-a19b-0c7224d1385d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781960089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.flash_ctrl_wo.3781960089
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.3329193496
Short name T669
Test name
Test status
Simulation time 24823400 ps
CPU time 15.62 seconds
Started Feb 18 02:55:10 PM PST 24
Finished Feb 18 02:55:27 PM PST 24
Peak memory 274624 kb
Host smart-ecf59fe2-e148-4d5f-a5a2-905f11b4875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329193496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3329193496
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.2667233780
Short name T589
Test name
Test status
Simulation time 22043500 ps
CPU time 13.65 seconds
Started Feb 18 02:55:11 PM PST 24
Finished Feb 18 02:55:25 PM PST 24
Peak memory 274500 kb
Host smart-1ab8b36d-85fd-4aa7-8868-40097dd63149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667233780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.2667233780
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.4041295222
Short name T89
Test name
Test status
Simulation time 72766700 ps
CPU time 134.88 seconds
Started Feb 18 02:55:15 PM PST 24
Finished Feb 18 02:57:30 PM PST 24
Peak memory 262612 kb
Host smart-7c4bdca7-83ca-4653-84cf-0157726dea09
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041295222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.4041295222
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.339461791
Short name T853
Test name
Test status
Simulation time 16225300 ps
CPU time 16.25 seconds
Started Feb 18 02:55:16 PM PST 24
Finished Feb 18 02:55:33 PM PST 24
Peak memory 273624 kb
Host smart-810210ba-7ccb-4950-976f-2eeed24504c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339461791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.339461791
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.1358400003
Short name T522
Test name
Test status
Simulation time 37846400 ps
CPU time 132.65 seconds
Started Feb 18 02:55:10 PM PST 24
Finished Feb 18 02:57:23 PM PST 24
Peak memory 263076 kb
Host smart-09826787-dc36-456d-bae9-dc6302a258c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358400003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.1358400003
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.1472271325
Short name T552
Test name
Test status
Simulation time 25599700 ps
CPU time 13.65 seconds
Started Feb 18 02:55:16 PM PST 24
Finished Feb 18 02:55:30 PM PST 24
Peak memory 273632 kb
Host smart-854108ca-58c3-43e8-b71f-d617dd726fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472271325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1472271325
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.663841269
Short name T854
Test name
Test status
Simulation time 431599300 ps
CPU time 134.96 seconds
Started Feb 18 02:55:17 PM PST 24
Finished Feb 18 02:57:34 PM PST 24
Peak memory 258800 kb
Host smart-f7c23c95-0e2a-4f92-9383-d79733e9e9f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663841269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot
p_reset.663841269
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1759170984
Short name T1049
Test name
Test status
Simulation time 50978400 ps
CPU time 16.09 seconds
Started Feb 18 02:55:17 PM PST 24
Finished Feb 18 02:55:34 PM PST 24
Peak memory 273796 kb
Host smart-940e7291-63f6-46f5-8b6d-51c23457e5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759170984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1759170984
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.1966323096
Short name T1015
Test name
Test status
Simulation time 77434900 ps
CPU time 139.17 seconds
Started Feb 18 02:55:15 PM PST 24
Finished Feb 18 02:57:35 PM PST 24
Peak memory 259884 kb
Host smart-48f70241-a418-435e-a0ad-d91f4a8ed80d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966323096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.1966323096
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.4012855590
Short name T883
Test name
Test status
Simulation time 26913000 ps
CPU time 13.23 seconds
Started Feb 18 02:55:18 PM PST 24
Finished Feb 18 02:55:32 PM PST 24
Peak memory 274824 kb
Host smart-eb48d848-04b1-40ee-b8d2-47ac0c2dadbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012855590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.4012855590
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.1627652090
Short name T1018
Test name
Test status
Simulation time 42151800 ps
CPU time 133.5 seconds
Started Feb 18 02:55:16 PM PST 24
Finished Feb 18 02:57:30 PM PST 24
Peak memory 259800 kb
Host smart-4b98239a-e360-4788-9f16-461ea661845c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627652090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.1627652090
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.4078155049
Short name T827
Test name
Test status
Simulation time 107626200 ps
CPU time 13.6 seconds
Started Feb 18 02:55:18 PM PST 24
Finished Feb 18 02:55:33 PM PST 24
Peak memory 273628 kb
Host smart-4958a383-9af3-4e66-984c-a8b141f8d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078155049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.4078155049
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.4044254351
Short name T803
Test name
Test status
Simulation time 39067100 ps
CPU time 13.3 seconds
Started Feb 18 02:55:24 PM PST 24
Finished Feb 18 02:55:38 PM PST 24
Peak memory 274604 kb
Host smart-765f332f-ba65-43c7-87ac-992d63a0f28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044254351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.4044254351
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.2475767590
Short name T96
Test name
Test status
Simulation time 73347800 ps
CPU time 135.31 seconds
Started Feb 18 02:55:18 PM PST 24
Finished Feb 18 02:57:35 PM PST 24
Peak memory 258672 kb
Host smart-5c98b076-51aa-4899-af1d-c5c392ddef19
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475767590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.2475767590
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.1783807351
Short name T174
Test name
Test status
Simulation time 39726900 ps
CPU time 13.42 seconds
Started Feb 18 02:55:24 PM PST 24
Finished Feb 18 02:55:38 PM PST 24
Peak memory 274596 kb
Host smart-6ec213b0-b490-48b4-a729-80e00508e6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783807351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1783807351
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.655061758
Short name T964
Test name
Test status
Simulation time 75118000 ps
CPU time 133.46 seconds
Started Feb 18 02:55:20 PM PST 24
Finished Feb 18 02:57:35 PM PST 24
Peak memory 258664 kb
Host smart-3caa8a03-1755-4b9e-9389-e8efc3d4b439
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655061758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_ot
p_reset.655061758
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.3774758801
Short name T223
Test name
Test status
Simulation time 16092600 ps
CPU time 15.98 seconds
Started Feb 18 02:55:21 PM PST 24
Finished Feb 18 02:55:38 PM PST 24
Peak memory 273800 kb
Host smart-e99012ce-0ea4-4657-97e5-b1e66ff9998d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774758801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3774758801
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.4054615764
Short name T651
Test name
Test status
Simulation time 70354900 ps
CPU time 13.96 seconds
Started Feb 18 02:48:03 PM PST 24
Finished Feb 18 02:48:18 PM PST 24
Peak memory 263868 kb
Host smart-fd596e42-efde-4216-b76b-0b0254317635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054615764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.4
054615764
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.4242626601
Short name T418
Test name
Test status
Simulation time 13812600 ps
CPU time 15.75 seconds
Started Feb 18 02:48:04 PM PST 24
Finished Feb 18 02:48:21 PM PST 24
Peak memory 273800 kb
Host smart-54e98b28-037f-4ed9-a8cb-fb69277f9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242626601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.4242626601
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.358997561
Short name T1034
Test name
Test status
Simulation time 9856184200 ps
CPU time 2190.01 seconds
Started Feb 18 02:47:53 PM PST 24
Finished Feb 18 03:24:26 PM PST 24
Peak memory 263284 kb
Host smart-28072c18-abbc-4f88-80b7-eeea83945430
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358997561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_erro
r_mp.358997561
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.2217325594
Short name T716
Test name
Test status
Simulation time 1391886900 ps
CPU time 893.77 seconds
Started Feb 18 02:47:54 PM PST 24
Finished Feb 18 03:02:51 PM PST 24
Peak memory 272524 kb
Host smart-d3293d8c-b477-4caa-83aa-0128e24202a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217325594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.2217325594
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.4263639372
Short name T258
Test name
Test status
Simulation time 10011726800 ps
CPU time 132.25 seconds
Started Feb 18 02:48:04 PM PST 24
Finished Feb 18 02:50:17 PM PST 24
Peak memory 319564 kb
Host smart-c867d7d8-6d1c-41d4-a302-3ca1e7db921e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263639372 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.4263639372
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.650388317
Short name T255
Test name
Test status
Simulation time 177298900 ps
CPU time 13.88 seconds
Started Feb 18 02:48:04 PM PST 24
Finished Feb 18 02:48:19 PM PST 24
Peak memory 264412 kb
Host smart-d45cebe4-e399-4442-be5b-224e8f6504a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650388317 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.650388317
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.487011610
Short name T915
Test name
Test status
Simulation time 1884459300 ps
CPU time 63.6 seconds
Started Feb 18 02:47:34 PM PST 24
Finished Feb 18 02:48:39 PM PST 24
Peak memory 261000 kb
Host smart-cd4a9f32-9a9f-45cc-99bb-c6a7bdf287b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487011610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw
_sec_otp.487011610
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.1232515536
Short name T248
Test name
Test status
Simulation time 2866158200 ps
CPU time 189.24 seconds
Started Feb 18 02:47:56 PM PST 24
Finished Feb 18 02:51:09 PM PST 24
Peak memory 289060 kb
Host smart-9fa0a4d9-7368-4189-aa69-4f9f9034f425
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232515536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.1232515536
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2762181263
Short name T692
Test name
Test status
Simulation time 8336415700 ps
CPU time 204.99 seconds
Started Feb 18 02:47:58 PM PST 24
Finished Feb 18 02:51:26 PM PST 24
Peak memory 283852 kb
Host smart-7d093a55-796b-4164-a194-be906fc1c848
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762181263 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.2762181263
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.2670028393
Short name T998
Test name
Test status
Simulation time 15260851700 ps
CPU time 109.38 seconds
Started Feb 18 02:47:58 PM PST 24
Finished Feb 18 02:49:51 PM PST 24
Peak memory 264340 kb
Host smart-9a326c9d-18b8-456d-b57d-bd813bc33f20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670028393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.2670028393
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2278818726
Short name T942
Test name
Test status
Simulation time 101271675900 ps
CPU time 396.06 seconds
Started Feb 18 02:47:55 PM PST 24
Finished Feb 18 02:54:35 PM PST 24
Peak memory 264372 kb
Host smart-7f4b7fbd-5a49-4b74-bcac-cf302091f73e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227
8818726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2278818726
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.2258921046
Short name T359
Test name
Test status
Simulation time 990681100 ps
CPU time 93.38 seconds
Started Feb 18 02:47:46 PM PST 24
Finished Feb 18 02:49:21 PM PST 24
Peak memory 258748 kb
Host smart-e154a734-7312-4a26-bf47-9b21b76e88c0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258921046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2258921046
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.3748339419
Short name T414
Test name
Test status
Simulation time 67009900 ps
CPU time 14.18 seconds
Started Feb 18 02:48:08 PM PST 24
Finished Feb 18 02:48:23 PM PST 24
Peak memory 264224 kb
Host smart-56bf8f41-0926-4893-8fbc-0fc7a08b5605
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748339419 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.3748339419
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3879510821
Short name T1030
Test name
Test status
Simulation time 25899489600 ps
CPU time 376.39 seconds
Started Feb 18 02:47:53 PM PST 24
Finished Feb 18 02:54:12 PM PST 24
Peak memory 272784 kb
Host smart-0b37ea3d-5d64-497e-8a63-c47e19b7a339
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879510821 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.3879510821
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.2716904336
Short name T792
Test name
Test status
Simulation time 20983666300 ps
CPU time 721.71 seconds
Started Feb 18 02:47:35 PM PST 24
Finished Feb 18 02:59:38 PM PST 24
Peak memory 260636 kb
Host smart-887af4ff-b6ce-40e9-8a30-dad31cf06b00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716904336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2716904336
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.1134612819
Short name T785
Test name
Test status
Simulation time 84121200 ps
CPU time 13.68 seconds
Started Feb 18 02:47:56 PM PST 24
Finished Feb 18 02:48:14 PM PST 24
Peak memory 264392 kb
Host smart-6fb5ecc1-6723-4f45-a2af-1845ed497c5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134612819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.1134612819
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.983326143
Short name T35
Test name
Test status
Simulation time 68435000 ps
CPU time 253.27 seconds
Started Feb 18 02:47:35 PM PST 24
Finished Feb 18 02:51:50 PM PST 24
Peak memory 273076 kb
Host smart-3fa88c20-8e37-410d-9c3c-1123462b47e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983326143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.983326143
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.1291552550
Short name T678
Test name
Test status
Simulation time 73906400 ps
CPU time 33.07 seconds
Started Feb 18 02:47:57 PM PST 24
Finished Feb 18 02:48:34 PM PST 24
Peak memory 276924 kb
Host smart-d684496e-cc63-4177-89e7-78cf600a61da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291552550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.1291552550
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.3538540053
Short name T401
Test name
Test status
Simulation time 1503527500 ps
CPU time 92.29 seconds
Started Feb 18 02:47:49 PM PST 24
Finished Feb 18 02:49:22 PM PST 24
Peak memory 280848 kb
Host smart-ccd5e197-845e-4ca9-b71e-7e2e46884175
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538540053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_ro.3538540053
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.346635042
Short name T632
Test name
Test status
Simulation time 1671681700 ps
CPU time 154.65 seconds
Started Feb 18 02:47:50 PM PST 24
Finished Feb 18 02:50:26 PM PST 24
Peak memory 280884 kb
Host smart-0670390e-dd5d-45cc-aa9b-9fd3b69a6334
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
346635042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.346635042
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.1307620775
Short name T1053
Test name
Test status
Simulation time 2030561500 ps
CPU time 154.19 seconds
Started Feb 18 02:47:54 PM PST 24
Finished Feb 18 02:50:31 PM PST 24
Peak memory 293216 kb
Host smart-3e011a42-44e9-4f1f-a7bf-f3cac6f19e1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307620775 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1307620775
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.3585389686
Short name T1012
Test name
Test status
Simulation time 42852134400 ps
CPU time 537.93 seconds
Started Feb 18 02:47:53 PM PST 24
Finished Feb 18 02:56:54 PM PST 24
Peak memory 313524 kb
Host smart-1b94fe96-856d-42aa-bdfc-f290d80c2997
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585389686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct
rl_rw.3585389686
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.701789785
Short name T1044
Test name
Test status
Simulation time 30479595300 ps
CPU time 696.92 seconds
Started Feb 18 02:47:56 PM PST 24
Finished Feb 18 02:59:37 PM PST 24
Peak memory 332700 kb
Host smart-8972e75f-11f8-463b-ad03-bf2181198b00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701789785 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_rw_derr.701789785
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.548946447
Short name T766
Test name
Test status
Simulation time 34838000 ps
CPU time 31.16 seconds
Started Feb 18 02:47:54 PM PST 24
Finished Feb 18 02:48:29 PM PST 24
Peak memory 273736 kb
Host smart-bb73473c-c40a-4b36-b031-d12e0bc979e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548946447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_rw_evict.548946447
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.762875073
Short name T356
Test name
Test status
Simulation time 15907581700 ps
CPU time 673.76 seconds
Started Feb 18 02:47:52 PM PST 24
Finished Feb 18 02:59:08 PM PST 24
Peak memory 324904 kb
Host smart-a947eb8d-ce5d-411b-84a7-36d87eef2608
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762875073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_se
rr.762875073
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.1031405638
Short name T345
Test name
Test status
Simulation time 1888332500 ps
CPU time 74.14 seconds
Started Feb 18 02:48:01 PM PST 24
Finished Feb 18 02:49:17 PM PST 24
Peak memory 263808 kb
Host smart-6ab376e0-e9b5-46e6-97fb-9dc40217288c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031405638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.1031405638
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.2130057657
Short name T283
Test name
Test status
Simulation time 39213900 ps
CPU time 124.12 seconds
Started Feb 18 02:47:36 PM PST 24
Finished Feb 18 02:49:42 PM PST 24
Peak memory 275656 kb
Host smart-639e885b-6f7d-4b4b-b2c5-dcb6f2bcac3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130057657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2130057657
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.4040315715
Short name T6
Test name
Test status
Simulation time 7267760700 ps
CPU time 151.97 seconds
Started Feb 18 02:47:49 PM PST 24
Finished Feb 18 02:50:22 PM PST 24
Peak memory 264356 kb
Host smart-6f7bcf1b-2865-45c1-9f4b-d485b4988604
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040315715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.flash_ctrl_wo.4040315715
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.2800649143
Short name T397
Test name
Test status
Simulation time 49817500 ps
CPU time 15.69 seconds
Started Feb 18 02:55:20 PM PST 24
Finished Feb 18 02:55:37 PM PST 24
Peak memory 274032 kb
Host smart-bee862f4-7eb6-4c8e-94d8-f3c6e8be0e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800649143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.2800649143
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.3959630407
Short name T419
Test name
Test status
Simulation time 44743800 ps
CPU time 13.46 seconds
Started Feb 18 02:55:23 PM PST 24
Finished Feb 18 02:55:38 PM PST 24
Peak memory 283064 kb
Host smart-c3e5c2e1-eb39-46cd-90e0-10093b957b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959630407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3959630407
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.2158367900
Short name T141
Test name
Test status
Simulation time 41526700 ps
CPU time 15.84 seconds
Started Feb 18 02:55:33 PM PST 24
Finished Feb 18 02:55:50 PM PST 24
Peak memory 274864 kb
Host smart-c450f8cf-d2de-4378-b01f-a89934f97639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158367900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2158367900
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.534305972
Short name T890
Test name
Test status
Simulation time 92036700 ps
CPU time 135.33 seconds
Started Feb 18 02:55:26 PM PST 24
Finished Feb 18 02:57:45 PM PST 24
Peak memory 258772 kb
Host smart-e54767e5-a043-4a0c-8d43-481bbd2ed757
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534305972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_ot
p_reset.534305972
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.2816671280
Short name T691
Test name
Test status
Simulation time 72437700 ps
CPU time 15.79 seconds
Started Feb 18 02:55:35 PM PST 24
Finished Feb 18 02:55:52 PM PST 24
Peak memory 273964 kb
Host smart-3fe77d4f-5594-448d-8f12-0b5989bcbb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816671280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2816671280
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.640712754
Short name T1035
Test name
Test status
Simulation time 45590900 ps
CPU time 135.89 seconds
Started Feb 18 02:55:33 PM PST 24
Finished Feb 18 02:57:50 PM PST 24
Peak memory 262448 kb
Host smart-3aaa9057-3cfb-40cb-9f14-5c1233b56e24
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640712754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.640712754
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.4103245080
Short name T704
Test name
Test status
Simulation time 17237100 ps
CPU time 13.79 seconds
Started Feb 18 02:55:36 PM PST 24
Finished Feb 18 02:55:51 PM PST 24
Peak memory 273644 kb
Host smart-ae9e9f6d-f9b7-4f4b-9982-78aca93e03f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103245080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.4103245080
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.3462139839
Short name T670
Test name
Test status
Simulation time 76632000 ps
CPU time 16.03 seconds
Started Feb 18 02:55:33 PM PST 24
Finished Feb 18 02:55:51 PM PST 24
Peak memory 273540 kb
Host smart-df1d4941-a436-4a91-ab3f-263e275052ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462139839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3462139839
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.1671569027
Short name T86
Test name
Test status
Simulation time 65901300 ps
CPU time 116.47 seconds
Started Feb 18 02:55:34 PM PST 24
Finished Feb 18 02:57:32 PM PST 24
Peak memory 258652 kb
Host smart-1e67749b-c9fc-45ab-8f1b-b034f5231118
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671569027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.1671569027
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.453414049
Short name T63
Test name
Test status
Simulation time 43726100 ps
CPU time 140.71 seconds
Started Feb 18 02:55:32 PM PST 24
Finished Feb 18 02:57:54 PM PST 24
Peak memory 258740 kb
Host smart-e1572f08-e09e-47ab-a9ad-004e29d43762
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453414049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_ot
p_reset.453414049
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1509543968
Short name T614
Test name
Test status
Simulation time 17917600 ps
CPU time 13.53 seconds
Started Feb 18 02:55:29 PM PST 24
Finished Feb 18 02:55:46 PM PST 24
Peak memory 273988 kb
Host smart-d0d48957-9836-43a1-ba75-21973f10787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509543968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1509543968
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.77643112
Short name T291
Test name
Test status
Simulation time 37983500 ps
CPU time 138.18 seconds
Started Feb 18 02:55:28 PM PST 24
Finished Feb 18 02:57:50 PM PST 24
Peak memory 258996 kb
Host smart-e36a9737-d7b7-4bc5-a391-109c8f104ed6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77643112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp
_reset.77643112
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.804059320
Short name T703
Test name
Test status
Simulation time 50695200 ps
CPU time 13.58 seconds
Started Feb 18 02:55:33 PM PST 24
Finished Feb 18 02:55:48 PM PST 24
Peak memory 274868 kb
Host smart-50ced729-df0d-47ba-86c9-beceda396c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804059320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.804059320
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.799079642
Short name T1047
Test name
Test status
Simulation time 23775400 ps
CPU time 16.01 seconds
Started Feb 18 02:55:38 PM PST 24
Finished Feb 18 02:55:55 PM PST 24
Peak memory 273836 kb
Host smart-3a55819c-86e8-4b94-ae6a-01c7ea26a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799079642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.799079642
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.2905323185
Short name T653
Test name
Test status
Simulation time 51971200 ps
CPU time 132.85 seconds
Started Feb 18 02:55:37 PM PST 24
Finished Feb 18 02:57:51 PM PST 24
Peak memory 258556 kb
Host smart-7f7c8479-4be6-4b00-a9e0-19bda33a3afd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905323185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.2905323185
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.3985819231
Short name T385
Test name
Test status
Simulation time 39149000 ps
CPU time 13.58 seconds
Started Feb 18 02:48:37 PM PST 24
Finished Feb 18 02:48:51 PM PST 24
Peak memory 263756 kb
Host smart-25bc4f3b-6c9b-4929-a827-ef5667a14ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985819231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.3
985819231
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.1979514140
Short name T173
Test name
Test status
Simulation time 146895300 ps
CPU time 13.55 seconds
Started Feb 18 02:48:28 PM PST 24
Finished Feb 18 02:48:44 PM PST 24
Peak memory 273644 kb
Host smart-c06c45c3-14aa-4654-af15-8abd947fedef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979514140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1979514140
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.4287743475
Short name T833
Test name
Test status
Simulation time 6914966700 ps
CPU time 2242.8 seconds
Started Feb 18 02:48:12 PM PST 24
Finished Feb 18 03:25:36 PM PST 24
Peak memory 263000 kb
Host smart-722b37be-82d4-4b57-a5ce-d37758522117
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287743475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.4287743475
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.4234123674
Short name T751
Test name
Test status
Simulation time 751774600 ps
CPU time 883.44 seconds
Started Feb 18 02:48:14 PM PST 24
Finished Feb 18 03:02:58 PM PST 24
Peak memory 272368 kb
Host smart-6d4760d1-47e5-404e-9a29-c7ae25fcc83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234123674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.4234123674
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.1347533366
Short name T43
Test name
Test status
Simulation time 1391252700 ps
CPU time 24.5 seconds
Started Feb 18 02:48:12 PM PST 24
Finished Feb 18 02:48:37 PM PST 24
Peak memory 264344 kb
Host smart-d543fb66-76fc-48d7-a70c-de5d373b0544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347533366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.1347533366
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.1540334015
Short name T101
Test name
Test status
Simulation time 10034362300 ps
CPU time 53.37 seconds
Started Feb 18 02:48:27 PM PST 24
Finished Feb 18 02:49:23 PM PST 24
Peak memory 280608 kb
Host smart-104c8a15-ab0e-46df-8ae0-21f9606e99b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540334015 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.1540334015
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.752757551
Short name T887
Test name
Test status
Simulation time 48325800 ps
CPU time 13.36 seconds
Started Feb 18 02:48:29 PM PST 24
Finished Feb 18 02:48:45 PM PST 24
Peak memory 264332 kb
Host smart-ef118f90-f222-4f64-8c9f-244d656610cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752757551 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.752757551
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1428773999
Short name T931
Test name
Test status
Simulation time 2162902700 ps
CPU time 170.72 seconds
Started Feb 18 02:48:07 PM PST 24
Finished Feb 18 02:50:59 PM PST 24
Peak memory 261472 kb
Host smart-daa515e4-627e-4cb1-a1e5-4c65883c4a25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428773999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1428773999
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.678890316
Short name T154
Test name
Test status
Simulation time 1363413200 ps
CPU time 150.77 seconds
Started Feb 18 02:48:30 PM PST 24
Finished Feb 18 02:51:03 PM PST 24
Peak memory 292780 kb
Host smart-28e7c7aa-8dd6-4a5c-86d9-717b26ac63a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678890316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_intr_rd.678890316
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.757697353
Short name T772
Test name
Test status
Simulation time 50715842800 ps
CPU time 212.2 seconds
Started Feb 18 02:48:31 PM PST 24
Finished Feb 18 02:52:05 PM PST 24
Peak memory 292800 kb
Host smart-c1be6cd0-588b-4718-b8ac-f0160b1f9d85
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757697353 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.757697353
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3552436479
Short name T364
Test name
Test status
Simulation time 3566629100 ps
CPU time 105.71 seconds
Started Feb 18 02:48:28 PM PST 24
Finished Feb 18 02:50:15 PM PST 24
Peak memory 264232 kb
Host smart-739904d3-475e-4425-a580-42ccf72dff4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552436479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3552436479
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1793106523
Short name T696
Test name
Test status
Simulation time 326656635000 ps
CPU time 653.44 seconds
Started Feb 18 02:48:29 PM PST 24
Finished Feb 18 02:59:25 PM PST 24
Peak memory 264432 kb
Host smart-36e3efe6-d141-448c-848d-bc170a076c1c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179
3106523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1793106523
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.316686579
Short name T740
Test name
Test status
Simulation time 9491588900 ps
CPU time 65.87 seconds
Started Feb 18 02:48:12 PM PST 24
Finished Feb 18 02:49:18 PM PST 24
Peak memory 259644 kb
Host smart-fb9163c4-d9e8-4c0c-b398-a5357ebd2cee
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316686579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.316686579
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1875331159
Short name T894
Test name
Test status
Simulation time 23228100 ps
CPU time 13.44 seconds
Started Feb 18 02:48:27 PM PST 24
Finished Feb 18 02:48:43 PM PST 24
Peak memory 264380 kb
Host smart-b211d269-9091-4b7d-bf26-427def030460
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875331159 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.1875331159
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.3089221768
Short name T74
Test name
Test status
Simulation time 9348866400 ps
CPU time 637.78 seconds
Started Feb 18 02:48:13 PM PST 24
Finished Feb 18 02:58:51 PM PST 24
Peak memory 272468 kb
Host smart-19f8c1d4-25c6-4c75-95bc-a53b8041700b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089221768 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.3089221768
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.1076994633
Short name T85
Test name
Test status
Simulation time 140102400 ps
CPU time 132.59 seconds
Started Feb 18 02:48:14 PM PST 24
Finished Feb 18 02:50:28 PM PST 24
Peak memory 258776 kb
Host smart-9a1e1327-2b47-4d77-8cb5-61257510591d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076994633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.1076994633
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.3854006854
Short name T977
Test name
Test status
Simulation time 11976632500 ps
CPU time 593.07 seconds
Started Feb 18 02:48:10 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 264340 kb
Host smart-87a20474-86c1-4d28-9808-1789326f5d56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854006854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.3854006854
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.1582833103
Short name T371
Test name
Test status
Simulation time 22138700 ps
CPU time 13.71 seconds
Started Feb 18 02:48:30 PM PST 24
Finished Feb 18 02:48:45 PM PST 24
Peak memory 264336 kb
Host smart-b9c0fde5-ff5e-4fc3-a26f-0c5dd1a5bdbd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582833103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.1582833103
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.3221205203
Short name T598
Test name
Test status
Simulation time 155432300 ps
CPU time 606.04 seconds
Started Feb 18 02:48:08 PM PST 24
Finished Feb 18 02:58:15 PM PST 24
Peak memory 282784 kb
Host smart-855011d4-3271-4556-a74e-4642f8c0da3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221205203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3221205203
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.3706786377
Short name T868
Test name
Test status
Simulation time 549119000 ps
CPU time 40.36 seconds
Started Feb 18 02:48:29 PM PST 24
Finished Feb 18 02:49:12 PM PST 24
Peak memory 276988 kb
Host smart-74530643-593e-4dc0-a208-18622d7c1533
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706786377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.3706786377
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.990377326
Short name T652
Test name
Test status
Simulation time 606969900 ps
CPU time 99.83 seconds
Started Feb 18 02:48:22 PM PST 24
Finished Feb 18 02:50:03 PM PST 24
Peak memory 280856 kb
Host smart-a868f921-8d12-444a-87d1-4111e568be77
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990377326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_ro.990377326
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.3144004298
Short name T921
Test name
Test status
Simulation time 1080140800 ps
CPU time 128.23 seconds
Started Feb 18 02:48:31 PM PST 24
Finished Feb 18 02:50:41 PM PST 24
Peak memory 280968 kb
Host smart-e0c3ff46-38c1-4a98-9534-22f1124741fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3144004298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.3144004298
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.27082137
Short name T399
Test name
Test status
Simulation time 1179490200 ps
CPU time 132.57 seconds
Started Feb 18 02:48:19 PM PST 24
Finished Feb 18 02:50:33 PM PST 24
Peak memory 293256 kb
Host smart-286f2dd1-f2df-45d5-9875-de402813eaf6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27082137 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.27082137
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.3962550764
Short name T725
Test name
Test status
Simulation time 32948891300 ps
CPU time 550.51 seconds
Started Feb 18 02:48:21 PM PST 24
Finished Feb 18 02:57:33 PM PST 24
Peak memory 313588 kb
Host smart-4c1cf7cf-89ce-43df-a1ad-7106984bfbde
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962550764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw.3962550764
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.3951889473
Short name T802
Test name
Test status
Simulation time 7276492200 ps
CPU time 529.4 seconds
Started Feb 18 02:48:28 PM PST 24
Finished Feb 18 02:57:20 PM PST 24
Peak memory 329448 kb
Host smart-ad291093-bdcf-4f70-ae1f-01714b089595
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951889473 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.3951889473
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.1788372959
Short name T299
Test name
Test status
Simulation time 79096700 ps
CPU time 28.99 seconds
Started Feb 18 02:48:29 PM PST 24
Finished Feb 18 02:49:00 PM PST 24
Peak memory 272668 kb
Host smart-b9c4a413-2804-404d-ab59-44b51c274bec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788372959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.1788372959
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1184254393
Short name T654
Test name
Test status
Simulation time 228257800 ps
CPU time 39.34 seconds
Started Feb 18 02:48:31 PM PST 24
Finished Feb 18 02:49:12 PM PST 24
Peak memory 272608 kb
Host smart-e5001302-3d45-42ae-b5ba-794d0b1d1091
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184254393 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.1184254393
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.2830701860
Short name T825
Test name
Test status
Simulation time 3219203700 ps
CPU time 572.25 seconds
Started Feb 18 02:48:19 PM PST 24
Finished Feb 18 02:57:53 PM PST 24
Peak memory 319204 kb
Host smart-8ecf8004-11e7-4e40-a5b9-739194b14e52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830701860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.2830701860
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.2790475326
Short name T352
Test name
Test status
Simulation time 1320295700 ps
CPU time 66.5 seconds
Started Feb 18 02:48:28 PM PST 24
Finished Feb 18 02:49:37 PM PST 24
Peak memory 263824 kb
Host smart-8609303c-827d-48b5-80e3-4668c2dc0adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790475326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2790475326
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.1661343324
Short name T813
Test name
Test status
Simulation time 40251600 ps
CPU time 171 seconds
Started Feb 18 02:48:11 PM PST 24
Finished Feb 18 02:51:02 PM PST 24
Peak memory 274932 kb
Host smart-4ec1472b-22dc-471c-a9af-f1442f3d09ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661343324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.1661343324
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.1228355569
Short name T958
Test name
Test status
Simulation time 8689576100 ps
CPU time 156.86 seconds
Started Feb 18 02:48:11 PM PST 24
Finished Feb 18 02:50:49 PM PST 24
Peak memory 264384 kb
Host smart-35f463b0-6938-4c84-8e75-6f6710060231
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228355569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.flash_ctrl_wo.1228355569
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.2381664932
Short name T409
Test name
Test status
Simulation time 14457400 ps
CPU time 16 seconds
Started Feb 18 02:55:35 PM PST 24
Finished Feb 18 02:55:52 PM PST 24
Peak memory 274752 kb
Host smart-ae840546-d5c9-4573-a86d-0ba874328582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381664932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.2381664932
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.1542942133
Short name T480
Test name
Test status
Simulation time 20188400 ps
CPU time 15.99 seconds
Started Feb 18 02:55:35 PM PST 24
Finished Feb 18 02:55:52 PM PST 24
Peak memory 273808 kb
Host smart-74db2b0d-7a2e-43b5-bad9-247071652e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542942133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.1542942133
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.1923565972
Short name T867
Test name
Test status
Simulation time 24571600 ps
CPU time 15.98 seconds
Started Feb 18 02:55:40 PM PST 24
Finished Feb 18 02:55:57 PM PST 24
Peak memory 274856 kb
Host smart-f0410f2d-a02d-4bff-8a29-82fedad2f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923565972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1923565972
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.2634767576
Short name T208
Test name
Test status
Simulation time 15863800 ps
CPU time 13.79 seconds
Started Feb 18 02:55:36 PM PST 24
Finished Feb 18 02:55:51 PM PST 24
Peak memory 273624 kb
Host smart-a19eb513-0720-45c7-ac6e-fcc1386df951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634767576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.2634767576
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3377721724
Short name T804
Test name
Test status
Simulation time 196098700 ps
CPU time 136.8 seconds
Started Feb 18 02:55:34 PM PST 24
Finished Feb 18 02:57:52 PM PST 24
Peak memory 258748 kb
Host smart-84862606-831d-42a2-9763-0f6f6b97fc61
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377721724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3377721724
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.4032028544
Short name T850
Test name
Test status
Simulation time 130488000 ps
CPU time 13.34 seconds
Started Feb 18 02:55:42 PM PST 24
Finished Feb 18 02:55:56 PM PST 24
Peak memory 273592 kb
Host smart-8f07d50a-c392-4a87-8308-463edd79c593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032028544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.4032028544
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.4209662657
Short name T656
Test name
Test status
Simulation time 67934500 ps
CPU time 132.36 seconds
Started Feb 18 02:55:44 PM PST 24
Finished Feb 18 02:57:57 PM PST 24
Peak memory 263440 kb
Host smart-40e3a047-0c47-43f3-aa00-aac6876fa7e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209662657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.4209662657
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.1823126113
Short name T470
Test name
Test status
Simulation time 15671200 ps
CPU time 16.12 seconds
Started Feb 18 02:55:48 PM PST 24
Finished Feb 18 02:56:06 PM PST 24
Peak memory 273696 kb
Host smart-989a1438-804e-41ad-b41a-f9dfb0b17bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823126113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1823126113
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.204090860
Short name T859
Test name
Test status
Simulation time 46868100 ps
CPU time 115.17 seconds
Started Feb 18 02:55:49 PM PST 24
Finished Feb 18 02:57:46 PM PST 24
Peak memory 258956 kb
Host smart-77043a8b-8d14-4100-9714-67cec3863bf6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204090860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_ot
p_reset.204090860
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.3459658059
Short name T999
Test name
Test status
Simulation time 71845000 ps
CPU time 16.08 seconds
Started Feb 18 02:55:42 PM PST 24
Finished Feb 18 02:55:59 PM PST 24
Peak memory 274824 kb
Host smart-1fd921f4-cbbd-4c99-8e7e-0b05521c412a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459658059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3459658059
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.2929764245
Short name T702
Test name
Test status
Simulation time 51182100 ps
CPU time 15.98 seconds
Started Feb 18 02:55:47 PM PST 24
Finished Feb 18 02:56:05 PM PST 24
Peak memory 273676 kb
Host smart-e15b88b3-4e88-4cb4-84c4-802e258ba356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929764245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2929764245
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.2098219849
Short name T512
Test name
Test status
Simulation time 42749000 ps
CPU time 16.25 seconds
Started Feb 18 02:55:44 PM PST 24
Finished Feb 18 02:56:01 PM PST 24
Peak memory 273644 kb
Host smart-27923061-f3c5-4488-95cd-213022012845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098219849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2098219849
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.1343367308
Short name T783
Test name
Test status
Simulation time 254779300 ps
CPU time 115.55 seconds
Started Feb 18 02:55:49 PM PST 24
Finished Feb 18 02:57:46 PM PST 24
Peak memory 258876 kb
Host smart-9dfd8210-6c63-4fb6-b8cb-4a2475c2f238
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343367308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.1343367308
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.205795988
Short name T718
Test name
Test status
Simulation time 54996500 ps
CPU time 16.33 seconds
Started Feb 18 02:55:53 PM PST 24
Finished Feb 18 02:56:10 PM PST 24
Peak memory 273828 kb
Host smart-372f8fa8-d347-462a-8d5e-514cfad0d2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205795988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.205795988
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.795323816
Short name T434
Test name
Test status
Simulation time 90858800 ps
CPU time 13.87 seconds
Started Feb 18 02:48:53 PM PST 24
Finished Feb 18 02:49:08 PM PST 24
Peak memory 263928 kb
Host smart-06d85464-a323-4369-af8d-43ce3c6de801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795323816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.795323816
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.2377797731
Short name T1027
Test name
Test status
Simulation time 62686800 ps
CPU time 15.91 seconds
Started Feb 18 02:48:52 PM PST 24
Finished Feb 18 02:49:09 PM PST 24
Peak memory 274056 kb
Host smart-76f6d57b-4eb4-472d-b686-ad13dd66937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377797731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2377797731
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.3237299217
Short name T111
Test name
Test status
Simulation time 12613100 ps
CPU time 22.07 seconds
Started Feb 18 02:48:57 PM PST 24
Finished Feb 18 02:49:26 PM PST 24
Peak memory 264396 kb
Host smart-8b0e778d-c851-41e4-82a3-701cedead22c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237299217 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.3237299217
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.3116355549
Short name T203
Test name
Test status
Simulation time 7066679500 ps
CPU time 2191.18 seconds
Started Feb 18 02:48:43 PM PST 24
Finished Feb 18 03:25:16 PM PST 24
Peak memory 263088 kb
Host smart-f4a214c1-90e2-4c5b-849a-f20547c455dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116355549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.3116355549
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.1494754122
Short name T163
Test name
Test status
Simulation time 871049800 ps
CPU time 927.23 seconds
Started Feb 18 02:48:50 PM PST 24
Finished Feb 18 03:04:18 PM PST 24
Peak memory 272508 kb
Host smart-2538dce5-fd21-43f3-bf30-a5546e286bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494754122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.1494754122
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.3299751656
Short name T938
Test name
Test status
Simulation time 707380600 ps
CPU time 24.3 seconds
Started Feb 18 02:48:49 PM PST 24
Finished Feb 18 02:49:15 PM PST 24
Peak memory 264260 kb
Host smart-2f577650-120f-443d-bb8d-f59b72ac07dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299751656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.3299751656
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2213181469
Short name T79
Test name
Test status
Simulation time 10012510500 ps
CPU time 303.46 seconds
Started Feb 18 02:48:57 PM PST 24
Finished Feb 18 02:54:08 PM PST 24
Peak memory 274132 kb
Host smart-79e1eed8-e5dd-4a5f-9fec-440bc838938f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213181469 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.2213181469
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.4187128606
Short name T257
Test name
Test status
Simulation time 89201000 ps
CPU time 14.05 seconds
Started Feb 18 02:48:57 PM PST 24
Finished Feb 18 02:49:18 PM PST 24
Peak memory 264292 kb
Host smart-77549e9d-01cb-4688-be29-6c633c63cb43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187128606 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.4187128606
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.112076818
Short name T731
Test name
Test status
Simulation time 160165224600 ps
CPU time 694.74 seconds
Started Feb 18 02:48:32 PM PST 24
Finished Feb 18 03:00:08 PM PST 24
Peak memory 258264 kb
Host smart-849981b5-886f-4532-98c1-fe3fbae89f9b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112076818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.flash_ctrl_hw_rma_reset.112076818
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2460731368
Short name T930
Test name
Test status
Simulation time 4655211000 ps
CPU time 47.11 seconds
Started Feb 18 02:48:43 PM PST 24
Finished Feb 18 02:49:32 PM PST 24
Peak memory 258180 kb
Host smart-636e83db-155f-469f-820b-f440e9c01375
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460731368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.2460731368
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.612466653
Short name T253
Test name
Test status
Simulation time 6421812900 ps
CPU time 170.95 seconds
Started Feb 18 02:48:49 PM PST 24
Finished Feb 18 02:51:41 PM PST 24
Peak memory 293140 kb
Host smart-d8176f18-83e0-4ebc-bf9d-ee754ca95265
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612466653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_intr_rd.612466653
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2702807368
Short name T502
Test name
Test status
Simulation time 54920039100 ps
CPU time 261.22 seconds
Started Feb 18 02:48:50 PM PST 24
Finished Feb 18 02:53:12 PM PST 24
Peak memory 290008 kb
Host smart-4e83d795-3f64-4a6e-ac93-5e36ef48398a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702807368 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.2702807368
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.1126618080
Short name T168
Test name
Test status
Simulation time 17335137900 ps
CPU time 100.57 seconds
Started Feb 18 02:48:52 PM PST 24
Finished Feb 18 02:50:34 PM PST 24
Peak memory 264300 kb
Host smart-4be96ded-1242-4b6b-9028-3e614cefd368
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126618080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.1126618080
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.2083441119
Short name T764
Test name
Test status
Simulation time 2110110700 ps
CPU time 96.72 seconds
Started Feb 18 02:48:50 PM PST 24
Finished Feb 18 02:50:28 PM PST 24
Peak memory 258736 kb
Host smart-a8145a72-e6be-4187-be3f-2c06c37b6b17
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083441119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.2083441119
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.4243490379
Short name T82
Test name
Test status
Simulation time 19556400 ps
CPU time 13.97 seconds
Started Feb 18 02:48:51 PM PST 24
Finished Feb 18 02:49:06 PM PST 24
Peak memory 264288 kb
Host smart-b84dd291-342e-4419-be52-9203c6c74607
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243490379 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.4243490379
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.1750486466
Short name T473
Test name
Test status
Simulation time 629834200 ps
CPU time 157.18 seconds
Started Feb 18 02:48:44 PM PST 24
Finished Feb 18 02:51:23 PM PST 24
Peak memory 261120 kb
Host smart-320af02c-965a-4f2a-aebc-1ddb28f2a20d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750486466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1750486466
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.2783864092
Short name T708
Test name
Test status
Simulation time 34351700 ps
CPU time 14 seconds
Started Feb 18 02:48:53 PM PST 24
Finished Feb 18 02:49:08 PM PST 24
Peak memory 264332 kb
Host smart-8a44fe94-0ba9-447f-b6b9-f9a42cc383aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783864092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.2783864092
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.189090659
Short name T713
Test name
Test status
Simulation time 15498500 ps
CPU time 18.62 seconds
Started Feb 18 02:48:37 PM PST 24
Finished Feb 18 02:48:56 PM PST 24
Peak memory 261224 kb
Host smart-7b54902b-15d9-4a48-8937-3c3dc2a022b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189090659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.189090659
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1132409799
Short name T1002
Test name
Test status
Simulation time 511908000 ps
CPU time 40.92 seconds
Started Feb 18 02:48:52 PM PST 24
Finished Feb 18 02:49:35 PM PST 24
Peak memory 265528 kb
Host smart-e1d03469-a75f-45ef-befb-71019bd0970c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132409799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1132409799
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.566840547
Short name T420
Test name
Test status
Simulation time 641728600 ps
CPU time 107.37 seconds
Started Feb 18 02:48:51 PM PST 24
Finished Feb 18 02:50:39 PM PST 24
Peak memory 280920 kb
Host smart-200e3a9d-48c9-42d3-bcef-67e6c3283e4f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566840547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_ro.566840547
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.569149963
Short name T583
Test name
Test status
Simulation time 697805200 ps
CPU time 163.87 seconds
Started Feb 18 02:48:50 PM PST 24
Finished Feb 18 02:51:35 PM PST 24
Peak memory 280932 kb
Host smart-b56a75c6-14fc-41a3-bd72-d2b8404c4105
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
569149963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.569149963
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.417825811
Short name T1026
Test name
Test status
Simulation time 1861667500 ps
CPU time 141.99 seconds
Started Feb 18 02:48:50 PM PST 24
Finished Feb 18 02:51:13 PM PST 24
Peak memory 295148 kb
Host smart-6b9e71ec-e194-4aac-a236-bb049a03f2d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417825811 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.417825811
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.251556941
Short name T443
Test name
Test status
Simulation time 6285380400 ps
CPU time 473.4 seconds
Started Feb 18 02:48:52 PM PST 24
Finished Feb 18 02:56:47 PM PST 24
Peak memory 317608 kb
Host smart-2fab1c20-c2bd-4d47-918c-e225db44d623
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251556941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctr
l_rw.251556941
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.1394683050
Short name T432
Test name
Test status
Simulation time 10914484100 ps
CPU time 554.24 seconds
Started Feb 18 02:48:50 PM PST 24
Finished Feb 18 02:58:05 PM PST 24
Peak memory 326816 kb
Host smart-bdd881cd-fc3e-41b1-895d-8cc163b8a029
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394683050 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.1394683050
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.3122187491
Short name T885
Test name
Test status
Simulation time 259714500 ps
CPU time 31.37 seconds
Started Feb 18 02:48:52 PM PST 24
Finished Feb 18 02:49:25 PM PST 24
Peak memory 271528 kb
Host smart-b5284895-5ed9-4b57-afc5-62c6b693e1a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122187491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.3122187491
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.3117346810
Short name T642
Test name
Test status
Simulation time 14029590300 ps
CPU time 724.55 seconds
Started Feb 18 02:48:49 PM PST 24
Finished Feb 18 03:00:55 PM PST 24
Peak memory 319176 kb
Host smart-e0ae2430-6e48-471c-941a-83180b066386
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117346810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.3117346810
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.1412258700
Short name T905
Test name
Test status
Simulation time 934656500 ps
CPU time 59.92 seconds
Started Feb 18 02:48:53 PM PST 24
Finished Feb 18 02:49:54 PM PST 24
Peak memory 258700 kb
Host smart-37821b88-c912-47c7-943c-7493fb74d27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412258700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1412258700
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.1704273171
Short name T519
Test name
Test status
Simulation time 45781000 ps
CPU time 101.29 seconds
Started Feb 18 02:48:37 PM PST 24
Finished Feb 18 02:50:20 PM PST 24
Peak memory 275676 kb
Host smart-bfdc9ed9-d35e-488e-822f-489165fc37b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704273171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1704273171
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.49262700
Short name T567
Test name
Test status
Simulation time 10795370200 ps
CPU time 226.28 seconds
Started Feb 18 02:48:44 PM PST 24
Finished Feb 18 02:52:32 PM PST 24
Peak memory 264372 kb
Host smart-77f4b9c9-357a-4b4c-b185-70c11ef42295
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49262700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.flash_ctrl_wo.49262700
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2296486197
Short name T1063
Test name
Test status
Simulation time 41431500 ps
CPU time 13.83 seconds
Started Feb 18 02:49:26 PM PST 24
Finished Feb 18 02:49:41 PM PST 24
Peak memory 263956 kb
Host smart-78b43e3a-d009-49c2-b5a2-bf5452c08c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296486197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
296486197
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.1180275255
Short name T559
Test name
Test status
Simulation time 38497000 ps
CPU time 15.91 seconds
Started Feb 18 02:49:34 PM PST 24
Finished Feb 18 02:49:52 PM PST 24
Peak memory 274584 kb
Host smart-3f7329af-5802-4100-8507-addeb93daafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180275255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1180275255
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.1956174019
Short name T960
Test name
Test status
Simulation time 16593300 ps
CPU time 21.73 seconds
Started Feb 18 02:49:24 PM PST 24
Finished Feb 18 02:49:47 PM PST 24
Peak memory 272708 kb
Host smart-4dc533ce-d670-4de5-92e0-87bb974f558f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956174019 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.1956174019
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.2075144661
Short name T791
Test name
Test status
Simulation time 23156011600 ps
CPU time 2173.08 seconds
Started Feb 18 02:49:03 PM PST 24
Finished Feb 18 03:25:19 PM PST 24
Peak memory 264188 kb
Host smart-25c5b11e-0203-4fde-aefa-085c8cb7d4e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075144661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.2075144661
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.3049175120
Short name T520
Test name
Test status
Simulation time 1436958400 ps
CPU time 891.86 seconds
Started Feb 18 02:49:05 PM PST 24
Finished Feb 18 03:03:59 PM PST 24
Peak memory 272424 kb
Host smart-e3cb3b19-ded3-48c4-87bb-948112646881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049175120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3049175120
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.3193751805
Short name T959
Test name
Test status
Simulation time 603738500 ps
CPU time 25.63 seconds
Started Feb 18 02:49:07 PM PST 24
Finished Feb 18 02:49:34 PM PST 24
Peak memory 264296 kb
Host smart-a281603a-7886-4502-b5ce-96b0cf000e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193751805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.3193751805
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1380041624
Short name T787
Test name
Test status
Simulation time 10019403000 ps
CPU time 86.09 seconds
Started Feb 18 02:49:25 PM PST 24
Finished Feb 18 02:50:53 PM PST 24
Peak memory 314044 kb
Host smart-c797f2b7-e95a-4fd2-af24-3d1d8dae2f78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380041624 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.1380041624
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2394148396
Short name T307
Test name
Test status
Simulation time 117717400 ps
CPU time 13.63 seconds
Started Feb 18 02:49:26 PM PST 24
Finished Feb 18 02:49:41 PM PST 24
Peak memory 264208 kb
Host smart-6b92ea66-4036-4403-acbf-842c2932f5ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394148396 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.2394148396
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2753262792
Short name T115
Test name
Test status
Simulation time 180189125800 ps
CPU time 783.35 seconds
Started Feb 18 02:48:58 PM PST 24
Finished Feb 18 03:02:08 PM PST 24
Peak memory 258196 kb
Host smart-28386262-e32a-4d5c-8760-af84ba938fd7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753262792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.2753262792
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1828783138
Short name T452
Test name
Test status
Simulation time 61253503800 ps
CPU time 191.64 seconds
Started Feb 18 02:48:56 PM PST 24
Finished Feb 18 02:52:12 PM PST 24
Peak memory 258156 kb
Host smart-b9a81b32-d676-4295-8f86-898dd6d3b688
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828783138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.1828783138
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.1775359222
Short name T843
Test name
Test status
Simulation time 14999490400 ps
CPU time 178.66 seconds
Started Feb 18 02:49:09 PM PST 24
Finished Feb 18 02:52:09 PM PST 24
Peak memory 292724 kb
Host smart-7d9502a0-9ef3-4c70-8e79-9ff5e236f997
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775359222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.1775359222
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2794920480
Short name T849
Test name
Test status
Simulation time 30729452900 ps
CPU time 263.7 seconds
Started Feb 18 02:49:09 PM PST 24
Finished Feb 18 02:53:35 PM PST 24
Peak memory 290748 kb
Host smart-f8071218-3d9f-4911-9177-41fd37397fae
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794920480 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.2794920480
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.2511496876
Short name T120
Test name
Test status
Simulation time 8191620400 ps
CPU time 111.05 seconds
Started Feb 18 02:49:10 PM PST 24
Finished Feb 18 02:51:03 PM PST 24
Peak memory 264300 kb
Host smart-20c8f3e9-f756-4bd2-a3b2-26ca6467fd6d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511496876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.2511496876
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3549003746
Short name T461
Test name
Test status
Simulation time 225804949500 ps
CPU time 359.31 seconds
Started Feb 18 02:49:17 PM PST 24
Finished Feb 18 02:55:18 PM PST 24
Peak memory 264392 kb
Host smart-6ec25fe8-2eb1-4de1-a1c7-1b3336fb31b7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354
9003746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3549003746
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.1447942701
Short name T358
Test name
Test status
Simulation time 4065567800 ps
CPU time 89.23 seconds
Started Feb 18 02:49:06 PM PST 24
Finished Feb 18 02:50:37 PM PST 24
Peak memory 259520 kb
Host smart-0916225a-0eda-4272-9d75-8630b040b186
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447942701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.1447942701
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1877534522
Short name T641
Test name
Test status
Simulation time 15460700 ps
CPU time 13.93 seconds
Started Feb 18 02:49:31 PM PST 24
Finished Feb 18 02:49:46 PM PST 24
Peak memory 264332 kb
Host smart-c8154774-f29b-4263-b8d0-ad5de0648871
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877534522 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1877534522
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.3162932005
Short name T135
Test name
Test status
Simulation time 39298746400 ps
CPU time 776.33 seconds
Started Feb 18 02:48:56 PM PST 24
Finished Feb 18 03:02:00 PM PST 24
Peak memory 272380 kb
Host smart-e77143a7-a12a-4d51-8944-7887f5a1bb78
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162932005 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.3162932005
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.4066334881
Short name T12
Test name
Test status
Simulation time 74379900 ps
CPU time 136.62 seconds
Started Feb 18 02:48:55 PM PST 24
Finished Feb 18 02:51:14 PM PST 24
Peak memory 258776 kb
Host smart-8cfa6c52-cf82-48bb-8066-c0fd2e54feb0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066334881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.4066334881
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.3858901365
Short name T494
Test name
Test status
Simulation time 259564400 ps
CPU time 326.12 seconds
Started Feb 18 02:48:55 PM PST 24
Finished Feb 18 02:54:25 PM PST 24
Peak memory 260636 kb
Host smart-ffe04b9f-f531-4362-a5e4-ff2032d4b2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3858901365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.3858901365
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.3928636194
Short name T599
Test name
Test status
Simulation time 69274600 ps
CPU time 13.66 seconds
Started Feb 18 02:49:16 PM PST 24
Finished Feb 18 02:49:30 PM PST 24
Peak memory 264356 kb
Host smart-a85ec5e4-7fc9-4a93-ad65-00a0a305ae14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928636194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.3928636194
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.3494697928
Short name T146
Test name
Test status
Simulation time 41761400 ps
CPU time 131.09 seconds
Started Feb 18 02:48:57 PM PST 24
Finished Feb 18 02:51:15 PM PST 24
Peak memory 280664 kb
Host smart-12cedb5e-6c31-4326-a22f-80b6264bc220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494697928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3494697928
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.562851846
Short name T729
Test name
Test status
Simulation time 45662700 ps
CPU time 32.89 seconds
Started Feb 18 02:49:31 PM PST 24
Finished Feb 18 02:50:05 PM PST 24
Peak memory 272700 kb
Host smart-91eef562-bcb5-4aed-97ed-de2a04b73fdd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562851846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_re_evict.562851846
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.3344474955
Short name T770
Test name
Test status
Simulation time 2008923000 ps
CPU time 102.59 seconds
Started Feb 18 02:49:06 PM PST 24
Finished Feb 18 02:50:50 PM PST 24
Peak memory 280848 kb
Host smart-f700bb8a-39b0-4718-87fc-ea7f9a4b5a2b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344474955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_ro.3344474955
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.1661380380
Short name T923
Test name
Test status
Simulation time 2192404700 ps
CPU time 151.26 seconds
Started Feb 18 02:49:10 PM PST 24
Finished Feb 18 02:51:43 PM PST 24
Peak memory 280824 kb
Host smart-99e70825-5449-47a7-9b75-6cd674ecf297
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1661380380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.1661380380
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1543676029
Short name T753
Test name
Test status
Simulation time 5332698900 ps
CPU time 171.13 seconds
Started Feb 18 02:49:05 PM PST 24
Finished Feb 18 02:51:58 PM PST 24
Peak memory 293236 kb
Host smart-d48ad758-1033-48fd-9687-b264f27cf354
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543676029 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1543676029
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.1224382939
Short name T39
Test name
Test status
Simulation time 13191020900 ps
CPU time 614.51 seconds
Started Feb 18 02:49:02 PM PST 24
Finished Feb 18 02:59:20 PM PST 24
Peak memory 312964 kb
Host smart-a6215bf0-1a17-4591-9f54-076a97220c02
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224382939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw.1224382939
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.1469742854
Short name T228
Test name
Test status
Simulation time 8408997800 ps
CPU time 464.03 seconds
Started Feb 18 02:49:09 PM PST 24
Finished Feb 18 02:56:54 PM PST 24
Peak memory 319276 kb
Host smart-613bc6b3-6273-442c-9af1-13fff2e23112
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469742854 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.1469742854
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.176289641
Short name T560
Test name
Test status
Simulation time 29089400 ps
CPU time 30.78 seconds
Started Feb 18 02:49:19 PM PST 24
Finished Feb 18 02:49:52 PM PST 24
Peak memory 273696 kb
Host smart-5c92c952-7cec-4a81-b2d4-7aec12cbfe42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176289641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_rw_evict.176289641
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.1107377753
Short name T75
Test name
Test status
Simulation time 50122500 ps
CPU time 31.91 seconds
Started Feb 18 02:49:19 PM PST 24
Finished Feb 18 02:49:52 PM PST 24
Peak memory 276224 kb
Host smart-2be57177-4ec9-439f-bea3-6356edc3e75d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107377753 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.1107377753
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.1884607269
Short name T673
Test name
Test status
Simulation time 2673527800 ps
CPU time 549.01 seconds
Started Feb 18 02:49:07 PM PST 24
Finished Feb 18 02:58:18 PM PST 24
Peak memory 310916 kb
Host smart-56afe1c6-7fb8-4a5c-a3ce-75800b881160
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884607269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.1884607269
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.2998646400
Short name T348
Test name
Test status
Simulation time 796423900 ps
CPU time 72.94 seconds
Started Feb 18 02:49:31 PM PST 24
Finished Feb 18 02:50:45 PM PST 24
Peak memory 264260 kb
Host smart-143f49f7-f732-4bf8-bcdc-e7537a5fc831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998646400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2998646400
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.200832862
Short name T573
Test name
Test status
Simulation time 154369000 ps
CPU time 194.52 seconds
Started Feb 18 02:48:56 PM PST 24
Finished Feb 18 02:52:18 PM PST 24
Peak memory 275684 kb
Host smart-361ca543-32bc-4e24-8006-0055863ddb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200832862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.200832862
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.1486905812
Short name T610
Test name
Test status
Simulation time 1928808900 ps
CPU time 159.45 seconds
Started Feb 18 02:49:03 PM PST 24
Finished Feb 18 02:51:45 PM PST 24
Peak memory 264392 kb
Host smart-106493e3-baac-454a-a1dc-097f2a3e0e0a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486905812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.flash_ctrl_wo.1486905812
Directory /workspace/9.flash_ctrl_wo/latest
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