Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	332222	1		T1	1		T2	1		T3	2
all_values[1]	332222	1		T1	1		T2	1		T3	2
all_values[2]	332222	1		T1	1		T2	1		T3	2
all_values[3]	332222	1		T1	1		T2	1		T3	2
all_values[4]	332222	1		T1	1		T2	1		T3	2
all_values[5]	332222	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10206	1		T1	6		T2	6		T3	12
auto[1]	1983126	1		T41	15168		T17	17454		T57	18936

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1616587	1		T1	6		T2	6		T3	11
auto[1]	376745	1		T3	1		T4	2		T5	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1273	1		T1	1		T2	1		T3	2
all_values[0]	auto[0]	auto[1]	423	1		T4	1		T5	1		T6	1
all_values[0]	auto[1]	auto[0]	266714	1		T41	2528		T17	2909		T57	3156
all_values[0]	auto[1]	auto[1]	63812	1		T49	2240		T50	2523		T94	4296
all_values[1]	auto[0]	auto[0]	1615	1		T1	1		T2	1		T3	2
all_values[1]	auto[0]	auto[1]	74	1		T257	4		T348	1		T349	2
all_values[1]	auto[1]	auto[0]	267297	1		T41	2528		T17	2909		T57	3156
all_values[1]	auto[1]	auto[1]	63236	1		T49	5819		T50	4867		T51	3024
all_values[2]	auto[0]	auto[0]	1572	1		T1	1		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	153	1		T6	1		T52	1		T53	1
all_values[2]	auto[1]	auto[0]	324864	1		T41	2528		T17	2909		T57	3156
all_values[2]	auto[1]	auto[1]	5633	1		T54	70		T55	813		T56	614
all_values[3]	auto[0]	auto[0]	1554	1		T1	1		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	142	1		T6	1		T52	1		T53	1
all_values[3]	auto[1]	auto[0]	185743	1		T41	967		T17	854		T129	721
all_values[3]	auto[1]	auto[1]	144783	1		T41	1561		T17	2055		T57	3156
all_values[4]	auto[0]	auto[0]	1177	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	537	1		T3	1		T4	1		T5	1
all_values[4]	auto[1]	auto[0]	232780	1		T41	1528		T17	1799		T57	2367
all_values[4]	auto[1]	auto[1]	97728	1		T41	1000		T17	1110		T57	789
all_values[5]	auto[0]	auto[0]	1539	1		T1	1		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	147	1		T38	1		T32	3		T58	1
all_values[5]	auto[1]	auto[0]	330459	1		T41	2528		T17	2909		T57	3156
all_values[5]	auto[1]	auto[1]	77	1		T348	1		T349	2		T350	3