Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T15 |
1 |
|
T38 |
1 |
|
T52 |
14 |
| others[1] |
230 |
1 |
|
T42 |
1 |
|
T58 |
1 |
|
T52 |
6 |
| others[2] |
225 |
1 |
|
T2 |
1 |
|
T32 |
1 |
|
T47 |
1 |
| others[3] |
388 |
1 |
|
T5 |
1 |
|
T32 |
1 |
|
T52 |
16 |
| false |
127 |
1 |
|
T41 |
1 |
|
T52 |
7 |
|
T53 |
5 |
| true |
12663 |
1 |
|
T1 |
129 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T52 |
12 |
| others[1] |
237 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T32 |
1 |
| others[2] |
224 |
1 |
|
T47 |
1 |
|
T48 |
1 |
|
T52 |
11 |
| others[3] |
353 |
1 |
|
T58 |
1 |
|
T52 |
14 |
|
T53 |
24 |
| false |
101 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
4 |
| true |
12722 |
1 |
|
T1 |
129 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8235 |
1 |
|
T1 |
129 |
|
T4 |
1 |
|
T15 |
1 |
| others[1] |
1210 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T40 |
15 |
| others[2] |
1218 |
1 |
|
T4 |
2 |
|
T40 |
12 |
|
T19 |
1 |
| others[3] |
2072 |
1 |
|
T3 |
1 |
|
T4 |
7 |
|
T40 |
23 |
| false |
663 |
1 |
|
T15 |
1 |
|
T11 |
1 |
|
T37 |
1 |
| true |
451 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8258 |
1 |
|
T1 |
129 |
|
T4 |
3 |
|
T15 |
1 |
| others[1] |
1242 |
1 |
|
T4 |
5 |
|
T20 |
1 |
|
T40 |
15 |
| others[2] |
1270 |
1 |
|
T40 |
18 |
|
T19 |
1 |
|
T52 |
22 |
| others[3] |
2025 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T40 |
20 |
| false |
622 |
1 |
|
T15 |
1 |
|
T40 |
6 |
|
T52 |
9 |
| true |
432 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T15 |
2 |
|
T52 |
7 |
|
T53 |
5 |
| others[1] |
113 |
1 |
|
T52 |
2 |
|
T53 |
7 |
|
T387 |
1 |
| others[2] |
105 |
1 |
|
T19 |
1 |
|
T52 |
3 |
|
T53 |
5 |
| others[3] |
173 |
1 |
|
T37 |
1 |
|
T19 |
1 |
|
T52 |
9 |
| false |
43 |
1 |
|
T52 |
2 |
|
T53 |
4 |
|
T79 |
1 |
| true |
13308 |
1 |
|
T1 |
129 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T38 |
1 |
|
T32 |
1 |
|
T47 |
1 |
| others[1] |
243 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T52 |
9 |
| others[2] |
217 |
1 |
|
T52 |
13 |
|
T53 |
13 |
|
T79 |
10 |
| others[3] |
394 |
1 |
|
T37 |
1 |
|
T43 |
1 |
|
T58 |
1 |
| false |
123 |
1 |
|
T32 |
1 |
|
T52 |
4 |
|
T53 |
10 |
| true |
12636 |
1 |
|
T1 |
129 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8030 |
1 |
|
T1 |
129 |
|
T4 |
2 |
|
T11 |
1 |
| others[1] |
1051 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1055 |
1 |
|
T15 |
1 |
|
T40 |
14 |
|
T32 |
2 |
| others[3] |
1780 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T40 |
23 |
| false |
519 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
4 |
| true |
1414 |
1 |
|
T16 |
1 |
|
T39 |
1 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T32 |
2 |
|
T47 |
1 |
|
T52 |
9 |
| others[1] |
219 |
1 |
|
T42 |
1 |
|
T52 |
16 |
|
T53 |
5 |
| others[2] |
240 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T32 |
1 |
| others[3] |
360 |
1 |
|
T52 |
19 |
|
T53 |
14 |
|
T386 |
1 |
| false |
124 |
1 |
|
T39 |
1 |
|
T19 |
1 |
|
T32 |
1 |
| true |
12679 |
1 |
|
T1 |
129 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T52 |
9 |
|
T53 |
10 |
|
T34 |
1 |
| others[1] |
234 |
1 |
|
T48 |
1 |
|
T52 |
16 |
|
T53 |
11 |
| others[2] |
239 |
1 |
|
T52 |
11 |
|
T53 |
14 |
|
T186 |
1 |
| others[3] |
332 |
1 |
|
T47 |
1 |
|
T52 |
13 |
|
T53 |
12 |
| false |
107 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T38 |
1 |
| true |
12725 |
1 |
|
T1 |
129 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8201 |
1 |
|
T1 |
129 |
|
T4 |
2 |
|
T37 |
1 |
| others[1] |
1224 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
12 |
| others[2] |
1198 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T11 |
1 |
| others[3] |
2130 |
1 |
|
T4 |
7 |
|
T15 |
1 |
|
T20 |
1 |
| false |
656 |
1 |
|
T40 |
7 |
|
T12 |
1 |
|
T52 |
14 |
| true |
440 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T4 |
2 |
|
T37 |
1 |
|
T40 |
8 |
| others[1] |
1292 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
13 |
| others[2] |
1240 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T40 |
12 |
| others[3] |
2051 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T20 |
1 |
| false |
629 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T40 |
10 |
| true |
429 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T19 |
1 |
|
T52 |
5 |
|
T53 |
1 |
| others[1] |
116 |
1 |
|
T52 |
5 |
|
T53 |
8 |
|
T79 |
6 |
| others[2] |
107 |
1 |
|
T15 |
2 |
|
T19 |
1 |
|
T47 |
1 |
| others[3] |
188 |
1 |
|
T37 |
1 |
|
T52 |
6 |
|
T53 |
5 |
| false |
55 |
1 |
|
T52 |
3 |
|
T53 |
2 |
|
T221 |
1 |
| true |
6333 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T41 |
1 |
| others[1] |
244 |
1 |
|
T15 |
1 |
|
T32 |
2 |
|
T52 |
8 |
| others[2] |
224 |
1 |
|
T16 |
1 |
|
T39 |
1 |
|
T52 |
7 |
| others[3] |
387 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T32 |
1 |
| false |
119 |
1 |
|
T52 |
6 |
|
T53 |
7 |
|
T79 |
5 |
| true |
5685 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1050 |
1 |
|
T40 |
15 |
|
T12 |
1 |
|
T78 |
1 |
| others[1] |
1065 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T40 |
16 |
| others[2] |
1097 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T15 |
1 |
| others[3] |
1779 |
1 |
|
T4 |
6 |
|
T37 |
1 |
|
T39 |
1 |
| false |
547 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T40 |
6 |
| true |
1355 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T15 |
1 |
|
T38 |
1 |
|
T52 |
16 |
| others[1] |
253 |
1 |
|
T32 |
1 |
|
T52 |
12 |
|
T53 |
10 |
| others[2] |
224 |
1 |
|
T2 |
1 |
|
T32 |
1 |
|
T52 |
8 |
| others[3] |
416 |
1 |
|
T5 |
1 |
|
T42 |
1 |
|
T52 |
12 |
| false |
138 |
1 |
|
T52 |
5 |
|
T53 |
6 |
|
T91 |
1 |
| true |
5628 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T32 |
1 |
|
T58 |
1 |
|
T52 |
13 |
| others[1] |
215 |
1 |
|
T32 |
2 |
|
T52 |
8 |
|
T53 |
11 |
| others[2] |
256 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T52 |
10 |
| others[3] |
388 |
1 |
|
T48 |
1 |
|
T52 |
20 |
|
T53 |
19 |
| false |
126 |
1 |
|
T52 |
4 |
|
T53 |
5 |
|
T387 |
1 |
| true |
5684 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T40 |
11 |
| others[1] |
1278 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T40 |
16 |
| others[2] |
1181 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
12 |
| others[3] |
2087 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T37 |
1 |
| false |
667 |
1 |
|
T4 |
2 |
|
T40 |
9 |
|
T19 |
1 |
| true |
454 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T20 |
1 |
| others[1] |
1255 |
1 |
|
T4 |
2 |
|
T40 |
17 |
|
T19 |
1 |
| others[2] |
1247 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
12 |
| others[3] |
2095 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T40 |
21 |
| false |
651 |
1 |
|
T4 |
2 |
|
T40 |
9 |
|
T52 |
12 |
| true |
427 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T19 |
1 |
|
T48 |
1 |
|
T53 |
4 |
| others[1] |
102 |
1 |
|
T52 |
4 |
|
T53 |
5 |
|
T388 |
1 |
| others[2] |
112 |
1 |
|
T15 |
1 |
|
T52 |
5 |
|
T53 |
3 |
| others[3] |
169 |
1 |
|
T37 |
1 |
|
T19 |
1 |
|
T47 |
1 |
| false |
58 |
1 |
|
T15 |
1 |
|
T52 |
3 |
|
T53 |
2 |
| true |
6347 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T15 |
1 |
|
T41 |
1 |
|
T52 |
10 |
| others[1] |
270 |
1 |
|
T38 |
1 |
|
T52 |
8 |
|
T53 |
15 |
| others[2] |
220 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T52 |
9 |
| others[3] |
391 |
1 |
|
T37 |
1 |
|
T39 |
1 |
|
T32 |
1 |
| false |
139 |
1 |
|
T15 |
1 |
|
T43 |
1 |
|
T52 |
4 |
| true |
5644 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1071 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T11 |
1 |
| others[1] |
1115 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T38 |
1 |
| others[2] |
1052 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T15 |
1 |
| others[3] |
1747 |
1 |
|
T4 |
3 |
|
T37 |
1 |
|
T40 |
22 |
| false |
539 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T40 |
6 |
| true |
1369 |
1 |
|
T2 |
1 |
|
T42 |
1 |
|
T43 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T5 |
1 |
|
T52 |
8 |
|
T53 |
7 |
| others[1] |
239 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
9 |
| others[2] |
247 |
1 |
|
T39 |
1 |
|
T32 |
1 |
|
T58 |
1 |
| others[3] |
402 |
1 |
|
T37 |
1 |
|
T38 |
1 |
|
T19 |
1 |
| false |
106 |
1 |
|
T52 |
4 |
|
T53 |
5 |
|
T34 |
1 |
| true |
5675 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T48 |
1 |
|
T52 |
14 |
|
T53 |
8 |
| others[1] |
207 |
1 |
|
T52 |
11 |
|
T53 |
4 |
|
T220 |
1 |
| others[2] |
223 |
1 |
|
T52 |
13 |
|
T53 |
12 |
|
T50 |
1 |
| others[3] |
379 |
1 |
|
T15 |
1 |
|
T38 |
1 |
|
T32 |
2 |
| false |
101 |
1 |
|
T5 |
1 |
|
T52 |
4 |
|
T53 |
3 |
| true |
5765 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1297 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
11 |
| others[1] |
1231 |
1 |
|
T40 |
16 |
|
T32 |
1 |
|
T52 |
17 |
| others[2] |
1241 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T40 |
14 |
| others[3] |
2067 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T20 |
1 |
| false |
615 |
1 |
|
T4 |
1 |
|
T40 |
10 |
|
T52 |
8 |
| true |
442 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T40 |
16 |
| others[1] |
1248 |
1 |
|
T4 |
1 |
|
T40 |
17 |
|
T19 |
1 |
| others[2] |
1189 |
1 |
|
T4 |
4 |
|
T40 |
8 |
|
T19 |
1 |
| others[3] |
2094 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T20 |
1 |
| false |
673 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
11 |
| true |
422 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T47 |
1 |
|
T52 |
5 |
|
T53 |
5 |
| others[1] |
111 |
1 |
|
T15 |
1 |
|
T38 |
1 |
|
T19 |
1 |
| others[2] |
108 |
1 |
|
T37 |
1 |
|
T19 |
1 |
|
T52 |
2 |
| others[3] |
178 |
1 |
|
T15 |
1 |
|
T52 |
6 |
|
T53 |
5 |
| false |
54 |
1 |
|
T32 |
1 |
|
T53 |
3 |
|
T79 |
1 |
| true |
6342 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T2 |
1 |
|
T38 |
1 |
|
T52 |
9 |
| others[1] |
242 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T32 |
2 |
| others[2] |
238 |
1 |
|
T16 |
1 |
|
T37 |
1 |
|
T43 |
1 |
| others[3] |
412 |
1 |
|
T41 |
1 |
|
T48 |
1 |
|
T52 |
15 |
| false |
128 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
10 |
| true |
5633 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
999 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T40 |
10 |
| others[1] |
1057 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T20 |
1 |
| others[2] |
1094 |
1 |
|
T4 |
2 |
|
T40 |
13 |
|
T19 |
1 |
| others[3] |
1756 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T37 |
1 |
| false |
568 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T15 |
1 |
| true |
1419 |
1 |
|
T16 |
1 |
|
T11 |
1 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T52 |
9 |
|
T53 |
6 |
|
T17 |
1 |
| others[1] |
213 |
1 |
|
T2 |
1 |
|
T52 |
12 |
|
T53 |
12 |
| others[2] |
246 |
1 |
|
T41 |
1 |
|
T42 |
1 |
|
T32 |
1 |
| others[3] |
384 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T32 |
1 |
| false |
125 |
1 |
|
T48 |
1 |
|
T52 |
3 |
|
T53 |
5 |
| true |
5721 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T19 |
1 |
| others[1] |
242 |
1 |
|
T5 |
1 |
|
T32 |
1 |
|
T58 |
1 |
| others[2] |
227 |
1 |
|
T32 |
1 |
|
T52 |
6 |
|
T53 |
9 |
| others[3] |
344 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T47 |
1 |
| false |
114 |
1 |
|
T52 |
8 |
|
T53 |
5 |
|
T388 |
1 |
| true |
5753 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1271 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T39 |
1 |
| others[1] |
1312 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T40 |
18 |
| others[2] |
1244 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T15 |
1 |
| others[3] |
1995 |
1 |
|
T4 |
4 |
|
T40 |
24 |
|
T172 |
1 |
| false |
625 |
1 |
|
T4 |
2 |
|
T40 |
4 |
|
T52 |
10 |
| true |
446 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |