Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T4 |
4 |
|
T16 |
1 |
|
T40 |
14 |
| others[1] |
1240 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T39 |
1 |
| others[2] |
1234 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
17 |
| others[3] |
2100 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T37 |
1 |
| false |
666 |
1 |
|
T4 |
1 |
|
T40 |
7 |
|
T52 |
12 |
| true |
431 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T37 |
1 |
|
T48 |
1 |
|
T52 |
2 |
| others[1] |
98 |
1 |
|
T52 |
4 |
|
T53 |
5 |
|
T220 |
1 |
| others[2] |
99 |
1 |
|
T19 |
1 |
|
T52 |
9 |
|
T53 |
1 |
| others[3] |
173 |
1 |
|
T15 |
2 |
|
T52 |
7 |
|
T53 |
11 |
| false |
71 |
1 |
|
T19 |
1 |
|
T52 |
5 |
|
T53 |
1 |
| true |
6351 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T32 |
1 |
|
T52 |
9 |
|
T53 |
12 |
| others[1] |
247 |
1 |
|
T38 |
1 |
|
T41 |
1 |
|
T52 |
10 |
| others[2] |
229 |
1 |
|
T32 |
1 |
|
T52 |
9 |
|
T53 |
10 |
| others[3] |
418 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T58 |
1 |
| false |
112 |
1 |
|
T19 |
2 |
|
T42 |
1 |
|
T52 |
13 |
| true |
5649 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1015 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T40 |
10 |
| others[1] |
1100 |
1 |
|
T4 |
2 |
|
T37 |
1 |
|
T40 |
15 |
| others[2] |
1085 |
1 |
|
T4 |
1 |
|
T15 |
2 |
|
T11 |
1 |
| others[3] |
1743 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T20 |
1 |
| false |
537 |
1 |
|
T4 |
1 |
|
T40 |
7 |
|
T19 |
1 |
| true |
1413 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T39 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T37 |
1 |
|
T38 |
1 |
|
T19 |
1 |
| others[1] |
217 |
1 |
|
T15 |
1 |
|
T32 |
2 |
|
T52 |
5 |
| others[2] |
239 |
1 |
|
T39 |
1 |
|
T52 |
16 |
|
T53 |
12 |
| others[3] |
386 |
1 |
|
T19 |
1 |
|
T41 |
1 |
|
T32 |
1 |
| false |
123 |
1 |
|
T2 |
1 |
|
T52 |
5 |
|
T53 |
3 |
| true |
5678 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T32 |
1 |
|
T48 |
1 |
|
T52 |
11 |
| others[1] |
233 |
1 |
|
T15 |
1 |
|
T52 |
12 |
|
T53 |
6 |
| others[2] |
184 |
1 |
|
T52 |
10 |
|
T53 |
7 |
|
T221 |
1 |
| others[3] |
384 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T37 |
1 |
| false |
115 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T58 |
1 |
| true |
5728 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T4 |
3 |
|
T40 |
14 |
|
T19 |
1 |
| others[1] |
1182 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T20 |
1 |
| others[2] |
1270 |
1 |
|
T4 |
2 |
|
T40 |
10 |
|
T41 |
1 |
| others[3] |
2108 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T15 |
1 |
| false |
660 |
1 |
|
T40 |
11 |
|
T48 |
1 |
|
T52 |
8 |
| true |
433 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1285 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T20 |
1 |
| others[1] |
1174 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
13 |
| others[2] |
1240 |
1 |
|
T4 |
1 |
|
T40 |
16 |
|
T78 |
1 |
| others[3] |
2111 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T16 |
1 |
| false |
651 |
1 |
|
T4 |
3 |
|
T40 |
5 |
|
T52 |
10 |
| true |
432 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T80 |
1 |
| others[1] |
96 |
1 |
|
T15 |
1 |
|
T52 |
5 |
|
T53 |
4 |
| others[2] |
95 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T19 |
1 |
| others[3] |
166 |
1 |
|
T19 |
1 |
|
T32 |
2 |
|
T52 |
3 |
| false |
51 |
1 |
|
T47 |
1 |
|
T52 |
1 |
|
T221 |
1 |
| true |
6393 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T42 |
1 |
|
T47 |
1 |
|
T52 |
11 |
| others[1] |
246 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T52 |
15 |
| others[2] |
235 |
1 |
|
T37 |
1 |
|
T41 |
1 |
|
T52 |
15 |
| others[3] |
394 |
1 |
|
T38 |
1 |
|
T39 |
1 |
|
T32 |
3 |
| false |
111 |
1 |
|
T48 |
1 |
|
T52 |
5 |
|
T53 |
3 |
| true |
5673 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1025 |
1 |
|
T4 |
3 |
|
T40 |
12 |
|
T19 |
1 |
| others[1] |
1090 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T39 |
1 |
| others[2] |
1052 |
1 |
|
T4 |
1 |
|
T15 |
2 |
|
T37 |
1 |
| others[3] |
1788 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T20 |
1 |
| false |
551 |
1 |
|
T16 |
1 |
|
T40 |
5 |
|
T172 |
1 |
| true |
1387 |
1 |
|
T5 |
1 |
|
T11 |
1 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T19 |
1 |
|
T41 |
1 |
|
T52 |
17 |
| others[1] |
223 |
1 |
|
T52 |
9 |
|
T53 |
12 |
|
T79 |
8 |
| others[2] |
219 |
1 |
|
T42 |
1 |
|
T32 |
1 |
|
T52 |
4 |
| others[3] |
405 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T38 |
1 |
| false |
122 |
1 |
|
T52 |
3 |
|
T53 |
5 |
|
T79 |
7 |
| true |
5704 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T5 |
1 |
|
T52 |
7 |
|
T53 |
5 |
| others[1] |
222 |
1 |
|
T52 |
7 |
|
T53 |
13 |
|
T181 |
1 |
| others[2] |
213 |
1 |
|
T19 |
1 |
|
T47 |
1 |
|
T52 |
12 |
| others[3] |
390 |
1 |
|
T15 |
1 |
|
T48 |
1 |
|
T52 |
26 |
| false |
122 |
1 |
|
T52 |
6 |
|
T53 |
5 |
|
T79 |
3 |
| true |
5720 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T4 |
1 |
|
T40 |
19 |
|
T19 |
2 |
| others[1] |
1269 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
14 |
| others[2] |
1212 |
1 |
|
T4 |
3 |
|
T40 |
14 |
|
T12 |
1 |
| others[3] |
2082 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T16 |
1 |
| false |
630 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T40 |
8 |
| true |
430 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1271 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T37 |
1 |
| others[1] |
1189 |
1 |
|
T4 |
3 |
|
T40 |
18 |
|
T172 |
1 |
| others[2] |
1247 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
10 |
| others[3] |
2089 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T16 |
1 |
| false |
672 |
1 |
|
T4 |
1 |
|
T40 |
10 |
|
T12 |
1 |
| true |
425 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T15 |
2 |
|
T37 |
1 |
|
T52 |
4 |
| others[1] |
82 |
1 |
|
T48 |
1 |
|
T52 |
3 |
|
T53 |
4 |
| others[2] |
87 |
1 |
|
T19 |
1 |
|
T52 |
2 |
|
T53 |
2 |
| others[3] |
181 |
1 |
|
T19 |
1 |
|
T52 |
4 |
|
T53 |
10 |
| false |
50 |
1 |
|
T52 |
2 |
|
T53 |
1 |
|
T387 |
1 |
| true |
6392 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T15 |
1 |
|
T42 |
1 |
|
T32 |
1 |
| others[1] |
221 |
1 |
|
T5 |
1 |
|
T52 |
13 |
|
T53 |
9 |
| others[2] |
226 |
1 |
|
T52 |
11 |
|
T53 |
11 |
|
T220 |
1 |
| others[3] |
397 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T19 |
1 |
| false |
118 |
1 |
|
T32 |
1 |
|
T52 |
5 |
|
T53 |
5 |
| true |
5699 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1103 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T20 |
1 |
| others[1] |
1052 |
1 |
|
T4 |
1 |
|
T40 |
11 |
|
T12 |
1 |
| others[2] |
1094 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T38 |
1 |
| others[3] |
1692 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T11 |
1 |
| false |
552 |
1 |
|
T15 |
1 |
|
T40 |
8 |
|
T172 |
1 |
| true |
1400 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T39 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T52 |
8 |
|
T53 |
8 |
|
T273 |
1 |
| others[1] |
215 |
1 |
|
T37 |
1 |
|
T32 |
1 |
|
T52 |
11 |
| others[2] |
260 |
1 |
|
T48 |
1 |
|
T52 |
7 |
|
T53 |
12 |
| others[3] |
389 |
1 |
|
T5 |
1 |
|
T32 |
2 |
|
T52 |
13 |
| false |
123 |
1 |
|
T52 |
4 |
|
T53 |
5 |
|
T388 |
1 |
| true |
5673 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T38 |
1 |
|
T52 |
10 |
|
T53 |
9 |
| others[1] |
249 |
1 |
|
T15 |
2 |
|
T58 |
1 |
|
T52 |
12 |
| others[2] |
216 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T47 |
1 |
| others[3] |
333 |
1 |
|
T32 |
1 |
|
T52 |
17 |
|
T53 |
16 |
| false |
110 |
1 |
|
T32 |
1 |
|
T48 |
1 |
|
T52 |
6 |
| true |
5760 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T4 |
4 |
|
T40 |
13 |
|
T52 |
22 |
| others[1] |
1218 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T40 |
12 |
| others[2] |
1190 |
1 |
|
T37 |
1 |
|
T38 |
1 |
|
T40 |
16 |
| others[3] |
2086 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T40 |
25 |
| false |
693 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T15 |
1 |
| true |
452 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1257 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T20 |
1 |
| others[1] |
1269 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T40 |
10 |
| others[2] |
1218 |
1 |
|
T4 |
1 |
|
T40 |
14 |
|
T12 |
1 |
| others[3] |
2074 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T37 |
1 |
| false |
646 |
1 |
|
T4 |
2 |
|
T40 |
6 |
|
T19 |
1 |
| true |
429 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T52 |
7 |
| others[1] |
108 |
1 |
|
T15 |
1 |
|
T52 |
3 |
|
T53 |
4 |
| others[2] |
112 |
1 |
|
T48 |
1 |
|
T52 |
6 |
|
T53 |
3 |
| others[3] |
164 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T47 |
1 |
| false |
52 |
1 |
|
T19 |
1 |
|
T52 |
1 |
|
T53 |
1 |
| true |
6341 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T19 |
1 |
|
T32 |
2 |
|
T52 |
8 |
| others[1] |
212 |
1 |
|
T19 |
1 |
|
T52 |
7 |
|
T53 |
8 |
| others[2] |
238 |
1 |
|
T38 |
1 |
|
T41 |
1 |
|
T32 |
2 |
| others[3] |
414 |
1 |
|
T15 |
1 |
|
T43 |
1 |
|
T52 |
19 |
| false |
126 |
1 |
|
T52 |
8 |
|
T53 |
10 |
|
T33 |
1 |
| true |
5686 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1112 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T15 |
1 |
| others[1] |
1045 |
1 |
|
T4 |
2 |
|
T37 |
1 |
|
T38 |
1 |
| others[2] |
1014 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
1769 |
1 |
|
T4 |
3 |
|
T40 |
28 |
|
T47 |
1 |
| false |
568 |
1 |
|
T4 |
2 |
|
T20 |
1 |
|
T40 |
8 |
| true |
1385 |
1 |
|
T16 |
1 |
|
T11 |
1 |
|
T39 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T2 |
1 |
|
T32 |
1 |
|
T52 |
14 |
| others[1] |
231 |
1 |
|
T58 |
1 |
|
T52 |
10 |
|
T53 |
8 |
| others[2] |
225 |
1 |
|
T39 |
1 |
|
T19 |
1 |
|
T47 |
1 |
| others[3] |
413 |
1 |
|
T37 |
1 |
|
T19 |
1 |
|
T41 |
1 |
| false |
112 |
1 |
|
T52 |
3 |
|
T53 |
5 |
|
T91 |
1 |
| true |
5674 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T32 |
2 |
|
T52 |
9 |
|
T53 |
6 |
| others[1] |
218 |
1 |
|
T52 |
12 |
|
T53 |
7 |
|
T79 |
13 |
| others[2] |
224 |
1 |
|
T52 |
10 |
|
T53 |
9 |
|
T220 |
1 |
| others[3] |
375 |
1 |
|
T15 |
1 |
|
T52 |
20 |
|
T53 |
15 |
| false |
119 |
1 |
|
T58 |
1 |
|
T48 |
1 |
|
T52 |
6 |
| true |
5747 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T4 |
1 |
|
T40 |
15 |
|
T19 |
1 |
| others[1] |
1280 |
1 |
|
T4 |
4 |
|
T16 |
1 |
|
T20 |
1 |
| others[2] |
1232 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T15 |
1 |
| others[3] |
2115 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T11 |
1 |
| false |
617 |
1 |
|
T4 |
1 |
|
T40 |
5 |
|
T41 |
1 |
| true |
429 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T4 |
3 |
|
T40 |
12 |
|
T19 |
1 |
| others[1] |
1273 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
1 |
| others[2] |
1239 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T20 |
1 |
| others[3] |
2119 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
21 |
| false |
627 |
1 |
|
T4 |
2 |
|
T40 |
9 |
|
T52 |
13 |
| true |
424 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T53 |
4 |
|
T220 |
1 |
|
T79 |
7 |
| others[1] |
104 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T47 |
1 |
| others[2] |
89 |
1 |
|
T37 |
1 |
|
T52 |
8 |
|
T387 |
1 |
| others[3] |
179 |
1 |
|
T15 |
1 |
|
T52 |
8 |
|
T53 |
4 |
| false |
57 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T53 |
1 |
| true |
6359 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T32 |
1 |
|
T58 |
1 |
|
T47 |
1 |
| others[1] |
235 |
1 |
|
T43 |
1 |
|
T32 |
1 |
|
T52 |
7 |
| others[2] |
272 |
1 |
|
T16 |
1 |
|
T52 |
12 |
|
T53 |
6 |
| others[3] |
384 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T38 |
1 |
| false |
109 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T32 |
1 |
| true |
5650 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |