Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1041 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T40 |
15 |
| others[1] |
1062 |
1 |
|
T4 |
2 |
|
T40 |
13 |
|
T19 |
1 |
| others[2] |
1121 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T20 |
1 |
| others[3] |
1724 |
1 |
|
T4 |
5 |
|
T15 |
2 |
|
T37 |
1 |
| false |
551 |
1 |
|
T4 |
1 |
|
T40 |
13 |
|
T52 |
9 |
| true |
1394 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
11 |
| others[1] |
205 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
12 |
| others[2] |
234 |
1 |
|
T52 |
11 |
|
T53 |
13 |
|
T388 |
1 |
| others[3] |
417 |
1 |
|
T15 |
1 |
|
T39 |
1 |
|
T58 |
1 |
| false |
112 |
1 |
|
T52 |
1 |
|
T53 |
3 |
|
T79 |
4 |
| true |
5707 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T32 |
1 |
|
T52 |
9 |
|
T53 |
8 |
| others[1] |
226 |
1 |
|
T32 |
1 |
|
T47 |
1 |
|
T48 |
1 |
| others[2] |
250 |
1 |
|
T32 |
1 |
|
T52 |
18 |
|
T53 |
12 |
| others[3] |
391 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
18 |
| false |
110 |
1 |
|
T5 |
1 |
|
T52 |
4 |
|
T53 |
4 |
| true |
5695 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
13 |
| others[1] |
1252 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T40 |
14 |
| others[2] |
1250 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T15 |
1 |
| others[3] |
2077 |
1 |
|
T4 |
5 |
|
T20 |
1 |
|
T40 |
29 |
| false |
645 |
1 |
|
T40 |
3 |
|
T52 |
6 |
|
T53 |
12 |
| true |
435 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T37 |
1 |
| others[1] |
1286 |
1 |
|
T4 |
1 |
|
T40 |
16 |
|
T52 |
15 |
| others[2] |
1180 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T40 |
12 |
| others[3] |
2154 |
1 |
|
T4 |
3 |
|
T20 |
1 |
|
T40 |
17 |
| false |
605 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
6 |
| true |
423 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T52 |
7 |
|
T53 |
2 |
|
T79 |
5 |
| others[1] |
111 |
1 |
|
T52 |
3 |
|
T53 |
5 |
|
T221 |
1 |
| others[2] |
123 |
1 |
|
T15 |
2 |
|
T37 |
1 |
|
T19 |
1 |
| others[3] |
159 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
8 |
| false |
54 |
1 |
|
T48 |
1 |
|
T52 |
4 |
|
T389 |
1 |
| true |
6353 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T32 |
1 |
|
T52 |
9 |
|
T53 |
10 |
| others[1] |
230 |
1 |
|
T47 |
1 |
|
T52 |
13 |
|
T53 |
13 |
| others[2] |
236 |
1 |
|
T15 |
1 |
|
T52 |
8 |
|
T53 |
10 |
| others[3] |
405 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T37 |
1 |
| false |
119 |
1 |
|
T52 |
9 |
|
T53 |
4 |
|
T390 |
1 |
| true |
5652 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1067 |
1 |
|
T4 |
5 |
|
T40 |
13 |
|
T52 |
17 |
| others[1] |
1088 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T37 |
1 |
| others[2] |
966 |
1 |
|
T4 |
3 |
|
T38 |
1 |
|
T40 |
14 |
| others[3] |
1816 |
1 |
|
T4 |
3 |
|
T15 |
2 |
|
T11 |
1 |
| false |
549 |
1 |
|
T16 |
1 |
|
T40 |
6 |
|
T78 |
1 |
| true |
1407 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T39 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T41 |
1 |
|
T52 |
8 |
|
T53 |
7 |
| others[1] |
226 |
1 |
|
T15 |
1 |
|
T32 |
2 |
|
T58 |
1 |
| others[2] |
237 |
1 |
|
T52 |
7 |
|
T53 |
10 |
|
T386 |
1 |
| others[3] |
372 |
1 |
|
T38 |
1 |
|
T39 |
1 |
|
T32 |
2 |
| false |
116 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T52 |
2 |
| true |
5718 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T48 |
1 |
| others[1] |
222 |
1 |
|
T37 |
1 |
|
T19 |
1 |
|
T52 |
6 |
| others[2] |
211 |
1 |
|
T32 |
1 |
|
T58 |
1 |
|
T52 |
6 |
| others[3] |
353 |
1 |
|
T15 |
1 |
|
T52 |
11 |
|
T53 |
20 |
| false |
112 |
1 |
|
T52 |
7 |
|
T387 |
1 |
|
T391 |
1 |
| true |
5764 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T4 |
2 |
|
T40 |
18 |
|
T52 |
21 |
| others[1] |
1242 |
1 |
|
T4 |
4 |
|
T16 |
1 |
|
T37 |
1 |
| others[2] |
1272 |
1 |
|
T4 |
1 |
|
T40 |
7 |
|
T172 |
1 |
| others[3] |
2039 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T15 |
2 |
| false |
624 |
1 |
|
T4 |
2 |
|
T40 |
10 |
|
T19 |
1 |
| true |
446 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T4 |
2 |
|
T40 |
15 |
|
T172 |
1 |
| others[1] |
1216 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T40 |
14 |
| others[2] |
1209 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
14 |
| others[3] |
2111 |
1 |
|
T4 |
5 |
|
T15 |
1 |
|
T20 |
1 |
| false |
701 |
1 |
|
T4 |
1 |
|
T40 |
9 |
|
T52 |
8 |
| true |
437 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T32 |
1 |
|
T52 |
1 |
|
T53 |
2 |
| others[1] |
94 |
1 |
|
T19 |
2 |
|
T52 |
2 |
|
T53 |
3 |
| others[2] |
92 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T52 |
3 |
| others[3] |
173 |
1 |
|
T15 |
1 |
|
T48 |
1 |
|
T52 |
6 |
| false |
58 |
1 |
|
T52 |
4 |
|
T53 |
1 |
|
T221 |
1 |
| true |
6380 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T38 |
1 |
|
T39 |
1 |
|
T52 |
13 |
| others[1] |
226 |
1 |
|
T37 |
1 |
|
T32 |
1 |
|
T52 |
8 |
| others[2] |
227 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
6 |
| others[3] |
406 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T19 |
1 |
| false |
127 |
1 |
|
T52 |
9 |
|
T53 |
7 |
|
T386 |
1 |
| true |
5674 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1023 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T40 |
19 |
| others[1] |
1096 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
18 |
| others[2] |
1044 |
1 |
|
T4 |
2 |
|
T37 |
1 |
|
T40 |
13 |
| others[3] |
1797 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T15 |
1 |
| false |
558 |
1 |
|
T4 |
1 |
|
T38 |
1 |
|
T39 |
1 |
| true |
1375 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T41 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T42 |
1 |
|
T48 |
1 |
|
T52 |
5 |
| others[1] |
237 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
9 |
| others[2] |
201 |
1 |
|
T38 |
1 |
|
T58 |
1 |
|
T52 |
8 |
| others[3] |
402 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T19 |
1 |
| false |
113 |
1 |
|
T52 |
6 |
|
T53 |
7 |
|
T211 |
1 |
| true |
5702 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T52 |
14 |
| others[1] |
222 |
1 |
|
T58 |
1 |
|
T52 |
6 |
|
T53 |
8 |
| others[2] |
220 |
1 |
|
T19 |
1 |
|
T48 |
1 |
|
T52 |
11 |
| others[3] |
346 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T32 |
2 |
| false |
128 |
1 |
|
T32 |
1 |
|
T52 |
6 |
|
T53 |
4 |
| true |
5745 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T4 |
2 |
|
T20 |
1 |
|
T40 |
15 |
| others[1] |
1268 |
1 |
|
T15 |
2 |
|
T38 |
1 |
|
T40 |
12 |
| others[2] |
1307 |
1 |
|
T4 |
2 |
|
T37 |
1 |
|
T40 |
21 |
| others[3] |
2015 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T40 |
15 |
| false |
634 |
1 |
|
T4 |
2 |
|
T11 |
1 |
|
T40 |
9 |
| true |
446 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T40 |
13 |
| others[1] |
1240 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T20 |
1 |
| others[2] |
1263 |
1 |
|
T4 |
2 |
|
T40 |
10 |
|
T52 |
19 |
| others[3] |
2045 |
1 |
|
T4 |
2 |
|
T40 |
28 |
|
T78 |
1 |
| false |
641 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T15 |
1 |
| true |
434 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T47 |
1 |
| others[1] |
97 |
1 |
|
T52 |
4 |
|
T53 |
8 |
|
T138 |
1 |
| others[2] |
94 |
1 |
|
T15 |
1 |
|
T52 |
2 |
|
T53 |
4 |
| others[3] |
176 |
1 |
|
T52 |
5 |
|
T53 |
3 |
|
T50 |
1 |
| false |
47 |
1 |
|
T37 |
1 |
|
T19 |
1 |
|
T32 |
1 |
| true |
6369 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T43 |
1 |
|
T32 |
1 |
|
T58 |
1 |
| others[1] |
215 |
1 |
|
T16 |
1 |
|
T52 |
8 |
|
T53 |
8 |
| others[2] |
256 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T39 |
1 |
| others[3] |
373 |
1 |
|
T41 |
1 |
|
T32 |
1 |
|
T52 |
13 |
| false |
138 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T42 |
1 |
| true |
5680 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1102 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T40 |
11 |
| others[1] |
1130 |
1 |
|
T4 |
3 |
|
T15 |
2 |
|
T16 |
1 |
| others[2] |
1032 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T40 |
14 |
| others[3] |
1729 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
1 |
| false |
537 |
1 |
|
T4 |
2 |
|
T39 |
1 |
|
T40 |
12 |
| true |
1363 |
1 |
|
T38 |
1 |
|
T41 |
1 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T32 |
1 |
|
T52 |
5 |
|
T53 |
15 |
| others[1] |
247 |
1 |
|
T19 |
1 |
|
T48 |
1 |
|
T52 |
13 |
| others[2] |
236 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T37 |
1 |
| others[3] |
377 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T52 |
22 |
| false |
107 |
1 |
|
T15 |
1 |
|
T47 |
1 |
|
T52 |
9 |
| true |
5721 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T52 |
7 |
|
T53 |
14 |
|
T388 |
1 |
| others[1] |
194 |
1 |
|
T47 |
1 |
|
T52 |
10 |
|
T53 |
11 |
| others[2] |
246 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T52 |
9 |
| others[3] |
359 |
1 |
|
T19 |
1 |
|
T32 |
2 |
|
T52 |
18 |
| false |
118 |
1 |
|
T52 |
7 |
|
T53 |
8 |
|
T221 |
1 |
| true |
5751 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T4 |
2 |
|
T20 |
1 |
|
T40 |
15 |
| others[1] |
1323 |
1 |
|
T3 |
1 |
|
T40 |
12 |
|
T172 |
1 |
| others[2] |
1217 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T37 |
1 |
| others[3] |
2049 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T15 |
1 |
| false |
622 |
1 |
|
T4 |
2 |
|
T40 |
7 |
|
T52 |
10 |
| true |
424 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1264 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
16 |
| others[1] |
1272 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T40 |
15 |
| others[2] |
1216 |
1 |
|
T4 |
2 |
|
T39 |
1 |
|
T40 |
9 |
| others[3] |
2113 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T20 |
1 |
| false |
601 |
1 |
|
T40 |
6 |
|
T52 |
1 |
|
T53 |
7 |
| true |
427 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T52 |
4 |
|
T53 |
1 |
|
T79 |
5 |
| others[1] |
110 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T52 |
6 |
| others[2] |
100 |
1 |
|
T19 |
1 |
|
T52 |
3 |
|
T53 |
8 |
| others[3] |
175 |
1 |
|
T15 |
1 |
|
T52 |
3 |
|
T53 |
1 |
| false |
46 |
1 |
|
T37 |
1 |
|
T52 |
2 |
|
T53 |
2 |
| true |
6355 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T42 |
1 |
|
T32 |
1 |
|
T52 |
8 |
| others[1] |
221 |
1 |
|
T37 |
1 |
|
T19 |
1 |
|
T52 |
13 |
| others[2] |
245 |
1 |
|
T32 |
1 |
|
T52 |
8 |
|
T53 |
9 |
| others[3] |
373 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T41 |
1 |
| false |
123 |
1 |
|
T52 |
6 |
|
T53 |
4 |
|
T50 |
1 |
| true |
5689 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1080 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T20 |
1 |
| others[1] |
1032 |
1 |
|
T4 |
2 |
|
T40 |
13 |
|
T19 |
1 |
| others[2] |
1010 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
10 |
| others[3] |
1842 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T15 |
1 |
| false |
546 |
1 |
|
T4 |
1 |
|
T40 |
4 |
|
T32 |
1 |
| true |
1383 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T52 |
10 |
|
T53 |
12 |
|
T386 |
1 |
| others[1] |
216 |
1 |
|
T42 |
1 |
|
T48 |
1 |
|
T52 |
14 |
| others[2] |
228 |
1 |
|
T15 |
1 |
|
T52 |
13 |
|
T53 |
8 |
| others[3] |
362 |
1 |
|
T5 |
1 |
|
T39 |
1 |
|
T19 |
1 |
| false |
149 |
1 |
|
T52 |
4 |
|
T53 |
12 |
|
T91 |
1 |
| true |
5703 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
200 |
1 |
|
T52 |
9 |
|
T53 |
12 |
|
T79 |
7 |
| others[1] |
234 |
1 |
|
T15 |
1 |
|
T32 |
1 |
|
T52 |
9 |
| others[2] |
207 |
1 |
|
T32 |
2 |
|
T52 |
4 |
|
T53 |
2 |
| others[3] |
372 |
1 |
|
T5 |
1 |
|
T32 |
1 |
|
T52 |
13 |
| false |
111 |
1 |
|
T19 |
1 |
|
T52 |
5 |
|
T53 |
5 |
| true |
5769 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |