Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1208 |
1 |
|
T4 |
1 |
|
T40 |
17 |
|
T19 |
1 |
| others[1] |
1282 |
1 |
|
T4 |
5 |
|
T37 |
1 |
|
T40 |
18 |
| others[2] |
1231 |
1 |
|
T4 |
1 |
|
T40 |
9 |
|
T12 |
1 |
| others[3] |
2041 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T20 |
1 |
| false |
684 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T15 |
1 |
| true |
447 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T4 |
5 |
|
T15 |
1 |
|
T40 |
15 |
| others[1] |
1204 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T40 |
15 |
| others[2] |
1310 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T37 |
1 |
| others[3] |
2050 |
1 |
|
T4 |
2 |
|
T20 |
1 |
|
T40 |
22 |
| false |
694 |
1 |
|
T4 |
1 |
|
T40 |
8 |
|
T19 |
1 |
| true |
424 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T15 |
1 |
|
T52 |
2 |
|
T53 |
7 |
| others[1] |
114 |
1 |
|
T32 |
1 |
|
T47 |
1 |
|
T52 |
3 |
| others[2] |
104 |
1 |
|
T37 |
1 |
|
T19 |
1 |
|
T52 |
3 |
| others[3] |
164 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T48 |
1 |
| false |
41 |
1 |
|
T52 |
5 |
|
T53 |
1 |
|
T138 |
1 |
| true |
6354 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T16 |
1 |
|
T52 |
11 |
|
T53 |
3 |
| others[1] |
234 |
1 |
|
T32 |
1 |
|
T52 |
12 |
|
T53 |
6 |
| others[2] |
264 |
1 |
|
T43 |
1 |
|
T32 |
2 |
|
T52 |
15 |
| others[3] |
399 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T32 |
1 |
| false |
133 |
1 |
|
T52 |
7 |
|
T53 |
8 |
|
T50 |
1 |
| true |
5634 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1142 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
1 |
| others[1] |
1035 |
1 |
|
T4 |
3 |
|
T40 |
9 |
|
T19 |
1 |
| others[2] |
1063 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T38 |
1 |
| others[3] |
1751 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T11 |
1 |
| false |
568 |
1 |
|
T4 |
2 |
|
T40 |
7 |
|
T52 |
11 |
| true |
1334 |
1 |
|
T39 |
1 |
|
T43 |
1 |
|
T32 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T32 |
1 |
|
T58 |
1 |
|
T52 |
6 |
| others[1] |
231 |
1 |
|
T42 |
1 |
|
T48 |
1 |
|
T52 |
6 |
| others[2] |
207 |
1 |
|
T2 |
1 |
|
T32 |
2 |
|
T52 |
10 |
| others[3] |
380 |
1 |
|
T5 |
1 |
|
T39 |
1 |
|
T41 |
1 |
| false |
119 |
1 |
|
T52 |
9 |
|
T53 |
2 |
|
T79 |
4 |
| true |
5728 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T15 |
1 |
|
T52 |
9 |
|
T53 |
7 |
| others[1] |
221 |
1 |
|
T19 |
1 |
|
T32 |
2 |
|
T52 |
13 |
| others[2] |
224 |
1 |
|
T47 |
1 |
|
T52 |
9 |
|
T53 |
4 |
| others[3] |
365 |
1 |
|
T32 |
1 |
|
T58 |
1 |
|
T52 |
14 |
| false |
120 |
1 |
|
T38 |
1 |
|
T52 |
8 |
|
T53 |
5 |
| true |
5746 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T20 |
1 |
| others[1] |
1234 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T38 |
1 |
| others[2] |
1280 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T40 |
10 |
| others[3] |
2075 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T40 |
29 |
| false |
628 |
1 |
|
T4 |
2 |
|
T40 |
5 |
|
T52 |
6 |
| true |
445 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T15 |
1 |
| others[1] |
1311 |
1 |
|
T4 |
4 |
|
T40 |
12 |
|
T19 |
1 |
| others[2] |
1244 |
1 |
|
T4 |
1 |
|
T40 |
12 |
|
T52 |
14 |
| others[3] |
2072 |
1 |
|
T4 |
5 |
|
T20 |
1 |
|
T37 |
1 |
| false |
639 |
1 |
|
T15 |
1 |
|
T40 |
6 |
|
T52 |
13 |
| true |
424 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T37 |
1 |
|
T52 |
4 |
|
T53 |
5 |
| others[1] |
117 |
1 |
|
T19 |
2 |
|
T47 |
1 |
|
T52 |
2 |
| others[2] |
105 |
1 |
|
T52 |
5 |
|
T53 |
5 |
|
T50 |
1 |
| others[3] |
192 |
1 |
|
T15 |
2 |
|
T32 |
1 |
|
T52 |
5 |
| false |
39 |
1 |
|
T48 |
1 |
|
T52 |
2 |
|
T53 |
1 |
| true |
6342 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T52 |
7 |
| others[1] |
258 |
1 |
|
T2 |
1 |
|
T32 |
2 |
|
T52 |
14 |
| others[2] |
233 |
1 |
|
T15 |
1 |
|
T32 |
2 |
|
T52 |
9 |
| others[3] |
389 |
1 |
|
T19 |
1 |
|
T41 |
1 |
|
T58 |
1 |
| false |
119 |
1 |
|
T39 |
1 |
|
T52 |
2 |
|
T53 |
3 |
| true |
5692 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1115 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T15 |
1 |
| others[1] |
1063 |
1 |
|
T4 |
2 |
|
T40 |
20 |
|
T12 |
1 |
| others[2] |
1032 |
1 |
|
T4 |
3 |
|
T37 |
1 |
|
T39 |
1 |
| others[3] |
1724 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T20 |
1 |
| false |
581 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T40 |
9 |
| true |
1378 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T58 |
1 |
|
T52 |
9 |
|
T53 |
4 |
| others[1] |
227 |
1 |
|
T52 |
10 |
|
T53 |
8 |
|
T273 |
1 |
| others[2] |
216 |
1 |
|
T15 |
1 |
|
T48 |
1 |
|
T52 |
15 |
| others[3] |
394 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T41 |
1 |
| false |
117 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
7 |
| true |
5711 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T52 |
9 |
|
T53 |
13 |
|
T388 |
1 |
| others[1] |
244 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T52 |
12 |
| others[2] |
215 |
1 |
|
T58 |
1 |
|
T52 |
13 |
|
T53 |
9 |
| others[3] |
370 |
1 |
|
T38 |
1 |
|
T32 |
2 |
|
T52 |
14 |
| false |
115 |
1 |
|
T19 |
1 |
|
T47 |
1 |
|
T52 |
5 |
| true |
5720 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T4 |
3 |
|
T40 |
14 |
|
T12 |
1 |
| others[1] |
1198 |
1 |
|
T15 |
1 |
|
T40 |
11 |
|
T19 |
1 |
| others[2] |
1223 |
1 |
|
T4 |
5 |
|
T15 |
1 |
|
T20 |
1 |
| others[3] |
2083 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| false |
675 |
1 |
|
T4 |
2 |
|
T37 |
1 |
|
T40 |
13 |
| true |
433 |
1 |
|
T2 |
1 |
|
T11 |
1 |
|
T39 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1269 |
1 |
|
T4 |
2 |
|
T40 |
13 |
|
T48 |
1 |
| others[1] |
1259 |
1 |
|
T4 |
4 |
|
T20 |
1 |
|
T40 |
17 |
| others[2] |
1258 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T15 |
1 |
| others[3] |
2026 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T37 |
1 |
| false |
642 |
1 |
|
T4 |
1 |
|
T40 |
5 |
|
T52 |
7 |
| true |
439 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T15 |
1 |
|
T52 |
7 |
|
T53 |
2 |
| others[1] |
111 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T52 |
6 |
| others[2] |
109 |
1 |
|
T52 |
3 |
|
T53 |
6 |
|
T388 |
1 |
| others[3] |
165 |
1 |
|
T15 |
1 |
|
T52 |
6 |
|
T53 |
4 |
| false |
51 |
1 |
|
T37 |
1 |
|
T19 |
1 |
|
T52 |
2 |
| true |
6341 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T42 |
1 |
| others[1] |
235 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T52 |
7 |
| others[2] |
251 |
1 |
|
T19 |
1 |
|
T52 |
11 |
|
T53 |
9 |
| others[3] |
408 |
1 |
|
T16 |
1 |
|
T39 |
1 |
|
T19 |
1 |
| false |
136 |
1 |
|
T32 |
1 |
|
T52 |
10 |
|
T53 |
7 |
| true |
5638 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1137 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T40 |
14 |
| others[1] |
1045 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T5 |
1 |
| others[2] |
1029 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
8 |
| others[3] |
1755 |
1 |
|
T4 |
5 |
|
T15 |
1 |
|
T40 |
26 |
| false |
504 |
1 |
|
T20 |
1 |
|
T37 |
1 |
|
T40 |
11 |
| true |
1423 |
1 |
|
T11 |
1 |
|
T38 |
1 |
|
T39 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T2 |
1 |
|
T52 |
7 |
|
T53 |
12 |
| others[1] |
237 |
1 |
|
T39 |
1 |
|
T19 |
1 |
|
T42 |
1 |
| others[2] |
226 |
1 |
|
T15 |
2 |
|
T32 |
1 |
|
T48 |
1 |
| others[3] |
398 |
1 |
|
T37 |
1 |
|
T41 |
1 |
|
T32 |
1 |
| false |
138 |
1 |
|
T47 |
1 |
|
T52 |
9 |
|
T53 |
6 |
| true |
5647 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T15 |
1 |
|
T52 |
6 |
|
T53 |
12 |
| others[1] |
242 |
1 |
|
T5 |
1 |
|
T32 |
1 |
|
T48 |
1 |
| others[2] |
222 |
1 |
|
T38 |
1 |
|
T19 |
1 |
|
T52 |
9 |
| others[3] |
339 |
1 |
|
T32 |
2 |
|
T58 |
1 |
|
T52 |
18 |
| false |
112 |
1 |
|
T37 |
1 |
|
T47 |
1 |
|
T52 |
1 |
| true |
5737 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T4 |
3 |
|
T37 |
1 |
|
T40 |
14 |
| others[1] |
1257 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T20 |
1 |
| others[2] |
1209 |
1 |
|
T15 |
2 |
|
T40 |
13 |
|
T52 |
16 |
| others[3] |
2112 |
1 |
|
T4 |
1 |
|
T40 |
26 |
|
T19 |
1 |
| false |
621 |
1 |
|
T4 |
1 |
|
T40 |
6 |
|
T32 |
1 |
| true |
447 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1216 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T40 |
16 |
| others[1] |
1239 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T40 |
13 |
| others[2] |
1231 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
16 |
| others[3] |
2094 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T40 |
23 |
| false |
677 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T40 |
4 |
| true |
436 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
85 |
1 |
|
T37 |
1 |
|
T52 |
3 |
|
T53 |
3 |
| others[1] |
113 |
1 |
|
T19 |
1 |
|
T52 |
5 |
|
T53 |
5 |
| others[2] |
110 |
1 |
|
T19 |
1 |
|
T52 |
5 |
|
T53 |
3 |
| others[3] |
177 |
1 |
|
T15 |
1 |
|
T52 |
5 |
|
T53 |
9 |
| false |
50 |
1 |
|
T15 |
1 |
|
T52 |
1 |
|
T53 |
2 |
| true |
6358 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T15 |
1 |
|
T32 |
1 |
|
T52 |
9 |
| others[1] |
271 |
1 |
|
T37 |
1 |
|
T19 |
2 |
|
T42 |
1 |
| others[2] |
213 |
1 |
|
T52 |
9 |
|
T53 |
6 |
|
T17 |
1 |
| others[3] |
435 |
1 |
|
T32 |
1 |
|
T52 |
20 |
|
T53 |
23 |
| false |
104 |
1 |
|
T52 |
6 |
|
T53 |
6 |
|
T33 |
1 |
| true |
5626 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1051 |
1 |
|
T4 |
4 |
|
T40 |
9 |
|
T19 |
1 |
| others[1] |
1052 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T40 |
12 |
| others[2] |
1085 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T20 |
1 |
| others[3] |
1804 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T37 |
1 |
| false |
505 |
1 |
|
T40 |
8 |
|
T19 |
1 |
|
T52 |
8 |
| true |
1396 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T52 |
12 |
|
T53 |
15 |
|
T221 |
1 |
| others[1] |
277 |
1 |
|
T32 |
1 |
|
T52 |
13 |
|
T53 |
15 |
| others[2] |
201 |
1 |
|
T52 |
6 |
|
T53 |
6 |
|
T119 |
1 |
| others[3] |
384 |
1 |
|
T32 |
1 |
|
T58 |
1 |
|
T52 |
17 |
| false |
125 |
1 |
|
T37 |
1 |
|
T52 |
4 |
|
T53 |
7 |
| true |
5694 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T52 |
12 |
|
T53 |
10 |
|
T79 |
4 |
| others[1] |
249 |
1 |
|
T32 |
1 |
|
T52 |
16 |
|
T53 |
12 |
| others[2] |
212 |
1 |
|
T32 |
1 |
|
T52 |
7 |
|
T53 |
10 |
| others[3] |
329 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T52 |
17 |
| false |
108 |
1 |
|
T15 |
1 |
|
T48 |
1 |
|
T52 |
3 |
| true |
5755 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T40 |
10 |
|
T19 |
1 |
|
T52 |
15 |
| others[1] |
1296 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T37 |
1 |
| others[2] |
1294 |
1 |
|
T4 |
2 |
|
T15 |
2 |
|
T40 |
12 |
| others[3] |
2057 |
1 |
|
T4 |
5 |
|
T11 |
1 |
|
T20 |
1 |
| false |
596 |
1 |
|
T4 |
2 |
|
T40 |
8 |
|
T52 |
13 |
| true |
423 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7 |
1 |
|
T135 |
1 |
|
T392 |
1 |
|
T393 |
1 |
| others[1] |
11 |
1 |
|
T329 |
1 |
|
T169 |
1 |
|
T158 |
1 |
| others[2] |
3 |
1 |
|
T394 |
1 |
|
T395 |
1 |
|
T396 |
1 |
| others[3] |
16 |
1 |
|
T168 |
1 |
|
T122 |
1 |
|
T155 |
1 |
| false |
4 |
1 |
|
T397 |
1 |
|
T398 |
1 |
|
T399 |
1 |
| true |
36 |
1 |
|
T10 |
1 |
|
T11 |
1 |
|
T121 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T400 |
1 |
|
T401 |
1 |
|
T402 |
1 |
| others[1] |
2 |
1 |
|
T175 |
1 |
|
T403 |
1 |
|
- |
- |
| others[2] |
6 |
1 |
|
T384 |
1 |
|
T404 |
1 |
|
T405 |
1 |
| others[3] |
6 |
1 |
|
T370 |
1 |
|
T336 |
1 |
|
T406 |
1 |
| false |
9 |
1 |
|
T111 |
1 |
|
T326 |
1 |
|
T382 |
1 |
| true |
22 |
1 |
|
T6 |
1 |
|
T385 |
1 |
|
T407 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |