Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10116 |
1 |
|
T1 |
129 |
|
T3 |
1 |
|
T4 |
1 |
| others[1] |
842 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
13 |
| others[2] |
771 |
1 |
|
T4 |
4 |
|
T40 |
14 |
|
T78 |
1 |
| others[3] |
1300 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T20 |
1 |
| false |
407 |
1 |
|
T4 |
1 |
|
T40 |
4 |
|
T52 |
11 |
| true |
514 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2423 |
1 |
|
T1 |
19 |
|
T3 |
1 |
|
T4 |
1 |
| others[1] |
2430 |
1 |
|
T1 |
27 |
|
T40 |
20 |
|
T77 |
16 |
| others[2] |
2261 |
1 |
|
T1 |
25 |
|
T4 |
1 |
|
T15 |
1 |
| others[3] |
3961 |
1 |
|
T1 |
42 |
|
T4 |
6 |
|
T37 |
1 |
| false |
1271 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T20 |
1 |
| true |
1604 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9530 |
1 |
|
T1 |
129 |
|
T19 |
2 |
|
T77 |
96 |
| others[1] |
269 |
1 |
|
T20 |
1 |
|
T32 |
1 |
|
T47 |
1 |
| others[2] |
246 |
1 |
|
T39 |
1 |
|
T48 |
1 |
|
T52 |
3 |
| others[3] |
480 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T172 |
1 |
| false |
144 |
1 |
|
T32 |
1 |
|
T52 |
4 |
|
T53 |
4 |
| true |
3281 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9762 |
1 |
|
T1 |
129 |
|
T2 |
1 |
|
T3 |
1 |
| others[1] |
472 |
1 |
|
T15 |
1 |
|
T40 |
8 |
|
T19 |
1 |
| others[2] |
465 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
5 |
| others[3] |
798 |
1 |
|
T4 |
3 |
|
T40 |
14 |
|
T12 |
1 |
| false |
253 |
1 |
|
T40 |
4 |
|
T52 |
2 |
|
T53 |
7 |
| true |
2200 |
1 |
|
T4 |
7 |
|
T16 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9555 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T32 |
1 |
| others[1] |
280 |
1 |
|
T38 |
1 |
|
T172 |
1 |
|
T48 |
1 |
| others[2] |
268 |
1 |
|
T52 |
15 |
|
T53 |
12 |
|
T91 |
1 |
| others[3] |
460 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T19 |
1 |
| false |
143 |
1 |
|
T15 |
1 |
|
T52 |
5 |
|
T53 |
4 |
| true |
3244 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9518 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T32 |
1 |
| others[1] |
250 |
1 |
|
T37 |
1 |
|
T58 |
1 |
|
T47 |
1 |
| others[2] |
265 |
1 |
|
T20 |
1 |
|
T52 |
10 |
|
T53 |
11 |
| others[3] |
403 |
1 |
|
T172 |
1 |
|
T32 |
1 |
|
T78 |
1 |
| false |
144 |
1 |
|
T52 |
4 |
|
T53 |
8 |
|
T221 |
1 |
| true |
3370 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10100 |
1 |
|
T1 |
129 |
|
T4 |
4 |
|
T40 |
17 |
| others[1] |
831 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T15 |
1 |
| others[2] |
851 |
1 |
|
T4 |
2 |
|
T20 |
1 |
|
T40 |
19 |
| others[3] |
1275 |
1 |
|
T4 |
3 |
|
T40 |
23 |
|
T12 |
1 |
| false |
400 |
1 |
|
T40 |
7 |
|
T52 |
9 |
|
T53 |
10 |
| true |
493 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10029 |
1 |
|
T1 |
129 |
|
T3 |
1 |
|
T4 |
2 |
| others[1] |
756 |
1 |
|
T4 |
4 |
|
T40 |
13 |
|
T78 |
1 |
| others[2] |
838 |
1 |
|
T4 |
2 |
|
T40 |
18 |
|
T47 |
1 |
| others[3] |
1365 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T20 |
1 |
| false |
413 |
1 |
|
T40 |
9 |
|
T52 |
12 |
|
T53 |
12 |
| true |
516 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2322 |
1 |
|
T1 |
29 |
|
T3 |
1 |
|
T4 |
1 |
| others[1] |
2387 |
1 |
|
T1 |
29 |
|
T4 |
4 |
|
T20 |
1 |
| others[2] |
2403 |
1 |
|
T1 |
26 |
|
T4 |
3 |
|
T40 |
8 |
| others[3] |
4068 |
1 |
|
T1 |
35 |
|
T4 |
3 |
|
T15 |
1 |
| false |
1194 |
1 |
|
T1 |
10 |
|
T40 |
6 |
|
T77 |
11 |
| true |
1543 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9553 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T52 |
9 |
| others[1] |
319 |
1 |
|
T2 |
1 |
|
T38 |
1 |
|
T19 |
1 |
| others[2] |
264 |
1 |
|
T3 |
1 |
|
T78 |
1 |
|
T52 |
5 |
| others[3] |
459 |
1 |
|
T15 |
1 |
|
T39 |
1 |
|
T48 |
1 |
| false |
151 |
1 |
|
T16 |
1 |
|
T42 |
1 |
|
T32 |
2 |
| true |
3171 |
1 |
|
T4 |
11 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9808 |
1 |
|
T1 |
129 |
|
T11 |
1 |
|
T37 |
1 |
| others[1] |
460 |
1 |
|
T39 |
1 |
|
T40 |
10 |
|
T32 |
1 |
| others[2] |
455 |
1 |
|
T15 |
1 |
|
T40 |
3 |
|
T12 |
1 |
| others[3] |
772 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T40 |
20 |
| false |
237 |
1 |
|
T4 |
3 |
|
T40 |
4 |
|
T52 |
4 |
| true |
2185 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9523 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T52 |
12 |
| others[1] |
256 |
1 |
|
T78 |
1 |
|
T52 |
8 |
|
T53 |
9 |
| others[2] |
263 |
1 |
|
T41 |
1 |
|
T52 |
9 |
|
T53 |
9 |
| others[3] |
441 |
1 |
|
T5 |
1 |
|
T37 |
1 |
|
T38 |
1 |
| false |
126 |
1 |
|
T2 |
1 |
|
T58 |
1 |
|
T52 |
4 |
| true |
3308 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9514 |
1 |
|
T1 |
129 |
|
T19 |
1 |
|
T77 |
96 |
| others[1] |
233 |
1 |
|
T15 |
1 |
|
T20 |
1 |
|
T32 |
1 |
| others[2] |
247 |
1 |
|
T32 |
1 |
|
T52 |
13 |
|
T53 |
11 |
| others[3] |
455 |
1 |
|
T32 |
1 |
|
T58 |
1 |
|
T52 |
15 |
| false |
128 |
1 |
|
T78 |
1 |
|
T52 |
5 |
|
T53 |
7 |
| true |
3340 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10070 |
1 |
|
T1 |
129 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
781 |
1 |
|
T4 |
4 |
|
T40 |
22 |
|
T19 |
1 |
| others[2] |
811 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T20 |
1 |
| others[3] |
1327 |
1 |
|
T4 |
3 |
|
T40 |
20 |
|
T12 |
1 |
| false |
422 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T40 |
10 |
| true |
506 |
1 |
|
T2 |
1 |
|
T15 |
2 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10071 |
1 |
|
T1 |
129 |
|
T4 |
1 |
|
T40 |
14 |
| others[1] |
787 |
1 |
|
T4 |
1 |
|
T40 |
18 |
|
T172 |
1 |
| others[2] |
783 |
1 |
|
T4 |
3 |
|
T40 |
10 |
|
T48 |
1 |
| others[3] |
1355 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T20 |
1 |
| false |
392 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T40 |
9 |
| true |
529 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2433 |
1 |
|
T1 |
18 |
|
T3 |
1 |
|
T20 |
1 |
| others[1] |
2434 |
1 |
|
T1 |
24 |
|
T4 |
2 |
|
T40 |
11 |
| others[2] |
2449 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T37 |
1 |
| others[3] |
3821 |
1 |
|
T1 |
48 |
|
T4 |
6 |
|
T15 |
2 |
| false |
1189 |
1 |
|
T1 |
19 |
|
T4 |
2 |
|
T40 |
5 |
| true |
1591 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9538 |
1 |
|
T1 |
129 |
|
T37 |
1 |
|
T38 |
1 |
| others[1] |
273 |
1 |
|
T15 |
1 |
|
T43 |
1 |
|
T52 |
10 |
| others[2] |
278 |
1 |
|
T52 |
10 |
|
T53 |
12 |
|
T57 |
1 |
| others[3] |
463 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T32 |
1 |
| false |
148 |
1 |
|
T172 |
1 |
|
T47 |
1 |
|
T52 |
5 |
| true |
3217 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9735 |
1 |
|
T1 |
129 |
|
T40 |
10 |
|
T77 |
96 |
| others[1] |
460 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T15 |
1 |
| others[2] |
454 |
1 |
|
T4 |
3 |
|
T37 |
1 |
|
T38 |
1 |
| others[3] |
728 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
12 |
| false |
248 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T52 |
4 |
| true |
2292 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9531 |
1 |
|
T1 |
129 |
|
T15 |
1 |
|
T20 |
1 |
| others[1] |
257 |
1 |
|
T5 |
1 |
|
T32 |
1 |
|
T48 |
1 |
| others[2] |
247 |
1 |
|
T2 |
1 |
|
T37 |
1 |
|
T47 |
1 |
| others[3] |
437 |
1 |
|
T39 |
1 |
|
T41 |
1 |
|
T32 |
1 |
| false |
138 |
1 |
|
T78 |
1 |
|
T52 |
7 |
|
T53 |
2 |
| true |
3307 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9549 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T32 |
2 |
| others[1] |
268 |
1 |
|
T32 |
1 |
|
T52 |
13 |
|
T53 |
8 |
| others[2] |
235 |
1 |
|
T3 |
1 |
|
T37 |
1 |
|
T48 |
1 |
| others[3] |
411 |
1 |
|
T38 |
1 |
|
T172 |
1 |
|
T52 |
14 |
| false |
120 |
1 |
|
T32 |
1 |
|
T52 |
3 |
|
T53 |
4 |
| true |
3334 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10043 |
1 |
|
T1 |
129 |
|
T4 |
3 |
|
T37 |
1 |
| others[1] |
803 |
1 |
|
T4 |
2 |
|
T40 |
12 |
|
T48 |
1 |
| others[2] |
812 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T20 |
1 |
| others[3] |
1334 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T5 |
1 |
| false |
426 |
1 |
|
T40 |
5 |
|
T41 |
1 |
|
T32 |
1 |
| true |
499 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10089 |
1 |
|
T1 |
129 |
|
T3 |
1 |
|
T4 |
7 |
| others[1] |
753 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
14 |
| others[2] |
819 |
1 |
|
T20 |
1 |
|
T40 |
14 |
|
T19 |
1 |
| others[3] |
1327 |
1 |
|
T4 |
2 |
|
T40 |
23 |
|
T12 |
1 |
| false |
399 |
1 |
|
T40 |
8 |
|
T19 |
1 |
|
T52 |
7 |
| true |
530 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2390 |
1 |
|
T1 |
17 |
|
T4 |
3 |
|
T40 |
15 |
| others[1] |
2450 |
1 |
|
T1 |
23 |
|
T4 |
3 |
|
T15 |
1 |
| others[2] |
2385 |
1 |
|
T1 |
26 |
|
T3 |
1 |
|
T20 |
1 |
| others[3] |
3879 |
1 |
|
T1 |
53 |
|
T4 |
3 |
|
T15 |
1 |
| false |
1262 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T37 |
1 |
| true |
1551 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9531 |
1 |
|
T1 |
129 |
|
T20 |
1 |
|
T39 |
1 |
| others[1] |
284 |
1 |
|
T19 |
1 |
|
T58 |
1 |
|
T52 |
6 |
| others[2] |
290 |
1 |
|
T37 |
1 |
|
T52 |
8 |
|
T53 |
10 |
| others[3] |
477 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T38 |
1 |
| false |
148 |
1 |
|
T52 |
6 |
|
T53 |
8 |
|
T220 |
1 |
| true |
3187 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9726 |
1 |
|
T1 |
129 |
|
T38 |
1 |
|
T39 |
1 |
| others[1] |
478 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T40 |
10 |
| others[2] |
491 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T40 |
9 |
| others[3] |
743 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T15 |
2 |
| false |
233 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T40 |
2 |
| true |
2246 |
1 |
|
T4 |
6 |
|
T16 |
1 |
|
T40 |
34 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9548 |
1 |
|
T1 |
129 |
|
T42 |
1 |
|
T77 |
96 |
| others[1] |
282 |
1 |
|
T38 |
1 |
|
T41 |
1 |
|
T47 |
1 |
| others[2] |
249 |
1 |
|
T32 |
1 |
|
T52 |
10 |
|
T53 |
11 |
| others[3] |
429 |
1 |
|
T37 |
1 |
|
T32 |
1 |
|
T58 |
1 |
| false |
137 |
1 |
|
T52 |
7 |
|
T53 |
2 |
|
T180 |
1 |
| true |
3272 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9527 |
1 |
|
T1 |
129 |
|
T5 |
1 |
|
T77 |
96 |
| others[1] |
280 |
1 |
|
T78 |
1 |
|
T52 |
12 |
|
T53 |
12 |
| others[2] |
259 |
1 |
|
T3 |
1 |
|
T32 |
3 |
|
T52 |
9 |
| others[3] |
397 |
1 |
|
T15 |
1 |
|
T32 |
1 |
|
T48 |
1 |
| false |
110 |
1 |
|
T15 |
1 |
|
T52 |
5 |
|
T53 |
3 |
| true |
3344 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10074 |
1 |
|
T1 |
129 |
|
T4 |
3 |
|
T15 |
1 |
| others[1] |
736 |
1 |
|
T4 |
1 |
|
T11 |
1 |
|
T37 |
1 |
| others[2] |
866 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T20 |
1 |
| others[3] |
1348 |
1 |
|
T4 |
3 |
|
T40 |
23 |
|
T19 |
1 |
| false |
403 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T40 |
11 |
| true |
490 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10080 |
1 |
|
T1 |
129 |
|
T4 |
1 |
|
T15 |
1 |
| others[1] |
814 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T40 |
13 |
| others[2] |
779 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T20 |
1 |
| others[3] |
1335 |
1 |
|
T4 |
5 |
|
T15 |
1 |
|
T40 |
29 |
| false |
396 |
1 |
|
T4 |
2 |
|
T40 |
8 |
|
T52 |
10 |
| true |
513 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2421 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T40 |
15 |
| others[1] |
2406 |
1 |
|
T1 |
29 |
|
T3 |
1 |
|
T4 |
4 |
| others[2] |
2417 |
1 |
|
T1 |
17 |
|
T5 |
1 |
|
T37 |
1 |
| others[3] |
3906 |
1 |
|
T1 |
45 |
|
T4 |
5 |
|
T15 |
2 |
| false |
1238 |
1 |
|
T1 |
16 |
|
T40 |
7 |
|
T77 |
14 |
| true |
1529 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9565 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T58 |
1 |
| others[1] |
256 |
1 |
|
T19 |
1 |
|
T172 |
1 |
|
T52 |
10 |
| others[2] |
303 |
1 |
|
T20 |
1 |
|
T37 |
1 |
|
T42 |
1 |
| others[3] |
448 |
1 |
|
T5 |
1 |
|
T43 |
1 |
|
T32 |
1 |
| false |
149 |
1 |
|
T16 |
1 |
|
T38 |
1 |
|
T52 |
3 |
| true |
3196 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |