Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9727 |
1 |
|
T1 |
129 |
|
T3 |
1 |
|
T4 |
2 |
| others[1] |
464 |
1 |
|
T40 |
13 |
|
T52 |
12 |
|
T53 |
2 |
| others[2] |
519 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
6 |
| others[3] |
762 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T16 |
1 |
| false |
248 |
1 |
|
T4 |
1 |
|
T40 |
4 |
|
T19 |
2 |
| true |
2197 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9549 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T47 |
1 |
| others[1] |
258 |
1 |
|
T172 |
1 |
|
T52 |
7 |
|
T53 |
12 |
| others[2] |
279 |
1 |
|
T20 |
1 |
|
T19 |
1 |
|
T32 |
1 |
| others[3] |
398 |
1 |
|
T15 |
1 |
|
T39 |
1 |
|
T19 |
1 |
| false |
141 |
1 |
|
T38 |
1 |
|
T52 |
3 |
|
T53 |
4 |
| true |
3292 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9532 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T78 |
1 |
| others[1] |
253 |
1 |
|
T19 |
1 |
|
T52 |
10 |
|
T53 |
11 |
| others[2] |
243 |
1 |
|
T38 |
1 |
|
T52 |
5 |
|
T53 |
8 |
| others[3] |
414 |
1 |
|
T32 |
2 |
|
T47 |
1 |
|
T52 |
21 |
| false |
123 |
1 |
|
T15 |
1 |
|
T52 |
7 |
|
T53 |
7 |
| true |
3352 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10063 |
1 |
|
T1 |
129 |
|
T4 |
2 |
|
T40 |
12 |
| others[1] |
813 |
1 |
|
T4 |
3 |
|
T20 |
1 |
|
T40 |
12 |
| others[2] |
775 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T37 |
1 |
| others[3] |
1311 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T40 |
27 |
| false |
433 |
1 |
|
T4 |
2 |
|
T40 |
7 |
|
T172 |
1 |
| true |
522 |
1 |
|
T2 |
1 |
|
T15 |
2 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10007 |
1 |
|
T1 |
129 |
|
T4 |
1 |
|
T37 |
1 |
| others[1] |
810 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T40 |
14 |
| others[2] |
847 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T40 |
19 |
| others[3] |
1317 |
1 |
|
T4 |
4 |
|
T15 |
1 |
|
T20 |
1 |
| false |
408 |
1 |
|
T4 |
1 |
|
T40 |
9 |
|
T52 |
15 |
| true |
528 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2437 |
1 |
|
T1 |
19 |
|
T4 |
1 |
|
T40 |
16 |
| others[1] |
2376 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T40 |
12 |
| others[2] |
2408 |
1 |
|
T1 |
26 |
|
T15 |
1 |
|
T20 |
1 |
| others[3] |
3910 |
1 |
|
T1 |
50 |
|
T3 |
1 |
|
T4 |
3 |
| false |
1263 |
1 |
|
T1 |
14 |
|
T4 |
4 |
|
T40 |
12 |
| true |
1523 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9560 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T48 |
1 |
| others[1] |
259 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T37 |
1 |
| others[2] |
277 |
1 |
|
T16 |
1 |
|
T19 |
1 |
|
T52 |
7 |
| others[3] |
471 |
1 |
|
T38 |
1 |
|
T19 |
1 |
|
T32 |
1 |
| false |
163 |
1 |
|
T52 |
5 |
|
T53 |
6 |
|
T408 |
1 |
| true |
3187 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9727 |
1 |
|
T1 |
129 |
|
T5 |
1 |
|
T20 |
1 |
| others[1] |
433 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
5 |
| others[2] |
484 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T15 |
1 |
| others[3] |
790 |
1 |
|
T4 |
4 |
|
T38 |
1 |
|
T39 |
1 |
| false |
253 |
1 |
|
T40 |
3 |
|
T58 |
1 |
|
T52 |
3 |
| true |
2230 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9554 |
1 |
|
T1 |
129 |
|
T2 |
1 |
|
T5 |
1 |
| others[1] |
262 |
1 |
|
T19 |
1 |
|
T48 |
1 |
|
T52 |
8 |
| others[2] |
253 |
1 |
|
T32 |
1 |
|
T52 |
7 |
|
T53 |
12 |
| others[3] |
458 |
1 |
|
T20 |
1 |
|
T37 |
1 |
|
T19 |
1 |
| false |
147 |
1 |
|
T52 |
9 |
|
T53 |
10 |
|
T180 |
1 |
| true |
3243 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9511 |
1 |
|
T1 |
129 |
|
T19 |
1 |
|
T77 |
96 |
| others[1] |
252 |
1 |
|
T5 |
1 |
|
T20 |
1 |
|
T19 |
1 |
| others[2] |
247 |
1 |
|
T15 |
1 |
|
T172 |
1 |
|
T32 |
1 |
| others[3] |
416 |
1 |
|
T32 |
1 |
|
T58 |
1 |
|
T52 |
20 |
| false |
133 |
1 |
|
T48 |
1 |
|
T52 |
7 |
|
T53 |
7 |
| true |
3358 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10118 |
1 |
|
T1 |
129 |
|
T4 |
1 |
|
T40 |
23 |
| others[1] |
784 |
1 |
|
T4 |
1 |
|
T40 |
10 |
|
T19 |
1 |
| others[2] |
812 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T20 |
1 |
| others[3] |
1292 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T5 |
1 |
| false |
405 |
1 |
|
T4 |
3 |
|
T40 |
4 |
|
T52 |
11 |
| true |
506 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10068 |
1 |
|
T1 |
129 |
|
T4 |
2 |
|
T40 |
13 |
| others[1] |
788 |
1 |
|
T4 |
4 |
|
T40 |
19 |
|
T52 |
16 |
| others[2] |
825 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T40 |
13 |
| others[3] |
1279 |
1 |
|
T4 |
2 |
|
T20 |
1 |
|
T37 |
1 |
| false |
424 |
1 |
|
T4 |
1 |
|
T40 |
2 |
|
T52 |
11 |
| true |
533 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2456 |
1 |
|
T1 |
23 |
|
T4 |
1 |
|
T40 |
19 |
| others[1] |
2325 |
1 |
|
T1 |
27 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
2343 |
1 |
|
T1 |
21 |
|
T3 |
1 |
|
T4 |
3 |
| others[3] |
3987 |
1 |
|
T1 |
45 |
|
T4 |
2 |
|
T20 |
1 |
| false |
1263 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T40 |
7 |
| true |
1543 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9541 |
1 |
|
T1 |
129 |
|
T5 |
1 |
|
T39 |
1 |
| others[1] |
275 |
1 |
|
T38 |
1 |
|
T32 |
1 |
|
T58 |
1 |
| others[2] |
286 |
1 |
|
T19 |
1 |
|
T43 |
1 |
|
T32 |
1 |
| others[3] |
455 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T32 |
1 |
| false |
135 |
1 |
|
T52 |
4 |
|
T53 |
4 |
|
T207 |
1 |
| true |
3225 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9737 |
1 |
|
T1 |
129 |
|
T4 |
2 |
|
T40 |
7 |
| others[1] |
477 |
1 |
|
T4 |
2 |
|
T15 |
1 |
|
T40 |
4 |
| others[2] |
461 |
1 |
|
T40 |
7 |
|
T19 |
1 |
|
T52 |
6 |
| others[3] |
796 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T15 |
1 |
| false |
228 |
1 |
|
T40 |
2 |
|
T12 |
1 |
|
T52 |
6 |
| true |
2218 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9516 |
1 |
|
T1 |
129 |
|
T15 |
1 |
|
T77 |
96 |
| others[1] |
280 |
1 |
|
T172 |
1 |
|
T32 |
2 |
|
T52 |
8 |
| others[2] |
272 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T52 |
8 |
| others[3] |
439 |
1 |
|
T5 |
1 |
|
T58 |
1 |
|
T47 |
1 |
| false |
128 |
1 |
|
T15 |
1 |
|
T39 |
1 |
|
T52 |
3 |
| true |
3282 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9501 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T52 |
11 |
| others[1] |
273 |
1 |
|
T32 |
2 |
|
T47 |
1 |
|
T52 |
10 |
| others[2] |
234 |
1 |
|
T48 |
1 |
|
T52 |
12 |
|
T53 |
8 |
| others[3] |
428 |
1 |
|
T172 |
1 |
|
T52 |
18 |
|
T53 |
13 |
| false |
136 |
1 |
|
T20 |
1 |
|
T32 |
1 |
|
T52 |
4 |
| true |
3345 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10076 |
1 |
|
T1 |
129 |
|
T3 |
1 |
|
T4 |
3 |
| others[1] |
779 |
1 |
|
T4 |
5 |
|
T40 |
10 |
|
T19 |
1 |
| others[2] |
821 |
1 |
|
T4 |
1 |
|
T40 |
19 |
|
T78 |
1 |
| others[3] |
1317 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T40 |
21 |
| false |
414 |
1 |
|
T4 |
1 |
|
T40 |
8 |
|
T47 |
1 |
| true |
510 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10057 |
1 |
|
T1 |
129 |
|
T4 |
1 |
|
T40 |
20 |
| others[1] |
806 |
1 |
|
T4 |
5 |
|
T20 |
1 |
|
T40 |
12 |
| others[2] |
838 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T40 |
13 |
| others[3] |
1302 |
1 |
|
T40 |
22 |
|
T12 |
1 |
|
T52 |
33 |
| false |
393 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T40 |
5 |
| true |
521 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2423 |
1 |
|
T1 |
26 |
|
T4 |
1 |
|
T40 |
13 |
| others[1] |
2363 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T40 |
17 |
| others[2] |
2313 |
1 |
|
T1 |
23 |
|
T3 |
1 |
|
T15 |
1 |
| others[3] |
4020 |
1 |
|
T1 |
49 |
|
T4 |
8 |
|
T15 |
1 |
| false |
1232 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T40 |
9 |
| true |
1566 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9546 |
1 |
|
T1 |
129 |
|
T2 |
1 |
|
T37 |
1 |
| others[1] |
304 |
1 |
|
T5 |
1 |
|
T52 |
15 |
|
T53 |
8 |
| others[2] |
272 |
1 |
|
T47 |
1 |
|
T52 |
8 |
|
T53 |
10 |
| others[3] |
447 |
1 |
|
T15 |
1 |
|
T20 |
1 |
|
T172 |
1 |
| false |
134 |
1 |
|
T19 |
1 |
|
T42 |
1 |
|
T52 |
3 |
| true |
3214 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9716 |
1 |
|
T1 |
129 |
|
T4 |
1 |
|
T40 |
3 |
| others[1] |
443 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T40 |
9 |
| others[2] |
443 |
1 |
|
T3 |
1 |
|
T40 |
10 |
|
T19 |
1 |
| others[3] |
782 |
1 |
|
T4 |
3 |
|
T15 |
1 |
|
T20 |
1 |
| false |
236 |
1 |
|
T4 |
1 |
|
T40 |
6 |
|
T43 |
1 |
| true |
2297 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9546 |
1 |
|
T1 |
129 |
|
T19 |
1 |
|
T77 |
96 |
| others[1] |
253 |
1 |
|
T5 |
1 |
|
T52 |
10 |
|
T53 |
12 |
| others[2] |
273 |
1 |
|
T2 |
1 |
|
T32 |
1 |
|
T52 |
11 |
| others[3] |
456 |
1 |
|
T15 |
1 |
|
T20 |
1 |
|
T42 |
1 |
| false |
133 |
1 |
|
T52 |
5 |
|
T53 |
10 |
|
T129 |
1 |
| true |
3256 |
1 |
|
T3 |
1 |
|
T4 |
11 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9523 |
1 |
|
T1 |
129 |
|
T77 |
96 |
|
T47 |
1 |
| others[1] |
258 |
1 |
|
T32 |
1 |
|
T52 |
6 |
|
T53 |
11 |
| others[2] |
243 |
1 |
|
T172 |
1 |
|
T48 |
1 |
|
T52 |
10 |
| others[3] |
390 |
1 |
|
T15 |
1 |
|
T20 |
1 |
|
T32 |
1 |
| false |
111 |
1 |
|
T52 |
1 |
|
T53 |
2 |
|
T95 |
1 |
| true |
3392 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10064 |
1 |
|
T1 |
129 |
|
T3 |
1 |
|
T4 |
1 |
| others[1] |
814 |
1 |
|
T4 |
3 |
|
T20 |
1 |
|
T40 |
20 |
| others[2] |
784 |
1 |
|
T4 |
3 |
|
T40 |
14 |
|
T52 |
24 |
| others[3] |
1343 |
1 |
|
T4 |
3 |
|
T11 |
1 |
|
T40 |
25 |
| false |
419 |
1 |
|
T4 |
1 |
|
T40 |
7 |
|
T52 |
15 |
| true |
493 |
1 |
|
T2 |
1 |
|
T15 |
2 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |