Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	222814	1		T1	785		T2	49		T3	297
auto[FlashEraseBank]	220176	1		T2	18		T3	405		T4	4

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	245188	1		T1	387		T2	32		T3	702
auto[FlashOpProgram]	178289	1		T1	199		T4	6		T5	350
auto[FlashOpErase]	15513	1		T1	199		T2	35		T4	4
auto[FlashOpInvalid]	4000	1		T99	200		T272	200		T293	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	245188	1		T1	387		T2	32		T3	702
op[FlashOpProgram]	178289	1		T1	199		T4	6		T5	350
op[FlashOpErase]	15513	1		T1	199		T2	35		T4	4
read_erase_read	694	1		T2	12		T15	1		T6	2
read_prog_read	1226	1		T5	4		T16	1		T38	13

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	304692	1		T2	25		T3	695		T4	11
auto[FlashPartInfo]	134683	1		T1	785		T2	42		T5	218
auto[FlashPartInfo1]	805	1		T3	2		T5	2		T38	3
auto[FlashPartInfo2]	2810	1		T3	5		T5	1		T20	6

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	182459	1		T2	7		T3	695		T4	1
auto[FlashPartData]	auto[FlashOpProgram]	114571	1		T4	6		T5	223		T16	1
auto[FlashPartData]	auto[FlashOpErase]	3768	1		T2	18		T4	4		T15	1
auto[FlashPartData]	auto[FlashOpInvalid]	3894	1		T99	196		T272	192		T293	188
auto[FlashPartInfo]	auto[FlashOpRead]	60291	1		T1	387		T2	25		T5	91
auto[FlashPartInfo]	auto[FlashOpProgram]	62615	1		T1	199		T5	127		T6	288
auto[FlashPartInfo]	auto[FlashOpErase]	11683	1		T1	199		T2	17		T6	12
auto[FlashPartInfo]	auto[FlashOpInvalid]	94	1		T99	4		T272	8		T293	12
auto[FlashPartInfo1]	auto[FlashOpRead]	700	1		T3	2		T5	2		T38	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	100	1		T48	1		T82	32		T105	1
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T24	1		T84	1		T410	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T410	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1738	1		T3	5		T5	1		T38	11
auto[FlashPartInfo2]	auto[FlashOpProgram]	1003	1		T20	6		T38	9		T78	4
auto[FlashPartInfo2]	auto[FlashOpErase]	59	1		T211	30		T25	1		T115	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T115	2		T411	4		T412	4