Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29777	1		T1	412		T4	5		T12	8
auto[1]	17	1		T331	1		T177	3		T332	3
auto[2]	146	1		T112	41		T203	9		T211	2
auto[3]	180	1		T2	22		T16	2		T39	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7559	1		T1	103		T2	9		T4	1
evic_idx[1]	7543	1		T1	103		T2	9		T4	2
evic_idx[2]	7513	1		T1	103		T2	2		T4	1
evic_idx[3]	7505	1		T1	103		T2	2		T4	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29015	1		T1	412		T2	22		T77	280
evic_op[2]	529	1		T4	1		T16	2		T39	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7220	1		T1	103		T77	70		T101	1
evic_idx[0]	evic_op[1]	auto[2]	6	1		T203	4		T211	1		T132	1
evic_idx[0]	evic_op[1]	auto[3]	53	1		T2	9		T333	23		T334	21
evic_idx[0]	evic_op[2]	auto[0]	87	1		T207	6		T335	6		T336	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T177	1		T337	1		T338	1
evic_idx[0]	evic_op[2]	auto[2]	27	1		T112	11		T339	1		T340	12
evic_idx[0]	evic_op[2]	auto[3]	18	1		T16	1		T43	1		T341	1
evic_idx[1]	evic_op[1]	auto[0]	7219	1		T1	103		T77	70		T101	1
evic_idx[1]	evic_op[1]	auto[2]	6	1		T203	4		T211	1		T132	1
evic_idx[1]	evic_op[1]	auto[3]	26	1		T2	9		T333	4		T334	13
evic_idx[1]	evic_op[2]	auto[0]	96	1		T4	1		T207	6		T60	1
evic_idx[1]	evic_op[2]	auto[1]	6	1		T331	1		T177	1		T332	1
evic_idx[1]	evic_op[2]	auto[2]	27	1		T112	12		T342	2		T340	9
evic_idx[1]	evic_op[2]	auto[3]	19	1		T16	1		T96	1		T343	1
evic_idx[2]	evic_op[1]	auto[0]	7220	1		T1	103		T77	70		T101	1
evic_idx[2]	evic_op[1]	auto[2]	2	1		T203	1		T132	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	21	1		T2	2		T333	7		T334	12
evic_idx[2]	evic_op[2]	auto[0]	84	1		T207	6		T62	1		T335	2
evic_idx[2]	evic_op[2]	auto[1]	3	1		T332	1		T338	1		T344	1
evic_idx[2]	evic_op[2]	auto[2]	27	1		T112	11		T342	1		T340	8
evic_idx[2]	evic_op[2]	auto[3]	12	1		T33	1		T96	1		T100	1
evic_idx[3]	evic_op[1]	auto[0]	7220	1		T1	103		T77	70		T101	1
evic_idx[3]	evic_op[1]	auto[2]	1	1		T132	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	21	1		T2	2		T333	9		T334	10
evic_idx[3]	evic_op[2]	auto[0]	83	1		T207	6		T335	4		T336	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T177	1		T332	1		T338	1
evic_idx[3]	evic_op[2]	auto[2]	22	1		T112	7		T342	1		T340	10
evic_idx[3]	evic_op[2]	auto[3]	10	1		T39	1		T96	1		T341	1