Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	59661	1		T49	5819		T50	4867		T51	1512
prog_lvl[2]	757	1		T51	755		T413	1		T414	1
prog_lvl[3]	1	1		T51	1		-	-		-	-

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	6078	1		T41	20		T17	14		T119	18
rd_lvl[2]	15148	1		T41	40		T17	27		T311	4025
rd_lvl[3]	15066	1		T41	21		T17	38		T311	2551
rd_lvl[4]	19672	1		T41	16		T17	253		T57	2427
rd_lvl[5]	11375	1		T41	548		T17	11		T57	729
rd_lvl[6]	16624	1		T41	905		T17	764		T130	1336
rd_lvl[7]	15276	1		T17	906		T130	678		T119	783
rd_lvl[8]	11416	1		T41	1		T54	415		T415	761
rd_lvl[9]	4310	1		T41	9		T17	2		T54	745
rd_lvl[10]	5591	1		T17	39		T129	399		T130	1
rd_lvl[11]	6670	1		T129	322		T54	1		T415	22
rd_lvl[12]	2963	1		T54	70		T416	627		T417	18
rd_lvl[13]	3556	1		T56	284		T235	454		T416	329
rd_lvl[14]	5583	1		T55	252		T56	650		T418	14
rd_lvl[15]	3471	1		T55	692		T419	8		T420	79