Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	332222	1		T1	1		T2	1		T3	2
all_pins[1]	332222	1		T1	1		T2	1		T3	2
all_pins[2]	332222	1		T1	1		T2	1		T3	2
all_pins[3]	332222	1		T1	1		T2	1		T3	2
all_pins[4]	332222	1		T1	1		T2	1		T3	2
all_pins[5]	332222	1		T1	1		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1616847	1		T1	6		T2	6		T3	12
values[0x1]	376485	1		T41	2590		T17	3173		T57	3945
transitions[0x0=>0x1]	356574	1		T41	2528		T17	2909		T57	3156
transitions[0x1=>0x0]	356583	1		T41	2528		T17	2909		T57	3156

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	268410	1		T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	63812	1		T49	2240		T50	2523		T94	4296
all_pins[0]	transitions[0x0=>0x1]	63792	1		T49	2240		T50	2523		T94	4296
all_pins[0]	transitions[0x1=>0x0]	63216	1		T49	5819		T50	4867		T51	3024
all_pins[1]	values[0x0]	268986	1		T1	1		T2	1		T3	2
all_pins[1]	values[0x1]	63236	1		T49	5819		T50	4867		T51	3024
all_pins[1]	transitions[0x0=>0x1]	63217	1		T49	5819		T50	4867		T51	3024
all_pins[1]	transitions[0x1=>0x0]	6584	1		T54	70		T55	846		T56	614
all_pins[2]	values[0x0]	325619	1		T1	1		T2	1		T3	2
all_pins[2]	values[0x1]	6603	1		T54	70		T55	846		T56	614
all_pins[2]	transitions[0x0=>0x1]	5613	1		T54	70		T55	813		T56	614
all_pins[2]	transitions[0x1=>0x0]	143793	1		T41	1561		T17	2055		T57	3156
all_pins[3]	values[0x0]	187439	1		T1	1		T2	1		T3	2
all_pins[3]	values[0x1]	144783	1		T41	1561		T17	2055		T57	3156
all_pins[3]	transitions[0x0=>0x1]	125943	1		T41	1499		T17	1791		T57	2367
all_pins[3]	transitions[0x1=>0x0]	79134	1		T41	967		T17	854		T129	721
all_pins[4]	values[0x0]	234248	1		T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	97974	1		T41	1029		T17	1118		T57	789
all_pins[4]	transitions[0x0=>0x1]	97956	1		T41	1029		T17	1118		T57	789
all_pins[4]	transitions[0x1=>0x0]	59	1		T348	1		T350	3		T351	3
all_pins[5]	values[0x0]	332145	1		T1	1		T2	1		T3	2
all_pins[5]	values[0x1]	77	1		T348	1		T349	2		T350	3
all_pins[5]	transitions[0x0=>0x1]	53	1		T348	1		T349	2		T350	1
all_pins[5]	transitions[0x1=>0x0]	63797	1		T49	2240		T50	2523		T94	4296