Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T257	4		T258	4		T352	4
all_values[1]	281	1		T257	4		T258	4		T352	4
all_values[2]	281	1		T257	4		T258	4		T352	4
all_values[3]	281	1		T257	4		T258	4		T352	4
all_values[4]	281	1		T257	4		T258	4		T352	4
all_values[5]	281	1		T257	4		T258	4		T352	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	920	1		T257	16		T258	16		T352	14
auto[1]	766	1		T257	8		T258	8		T352	10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	632	1		T257	11		T258	5		T352	12
auto[1]	1054	1		T257	13		T258	19		T352	12

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	999	1		T257	18		T258	13		T352	17
auto[1]	687	1		T257	6		T258	11		T352	7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	63	1		T257	1		T353	3		T350	1
all_values[0]	auto[0]	auto[0]	auto[1]	27	1		T258	1		T348	1		T349	1
all_values[0]	auto[0]	auto[1]	auto[0]	53	1		T352	1		T348	1		T353	1
all_values[0]	auto[0]	auto[1]	auto[1]	26	1		T257	2		T352	2		T354	1
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T258	2		T348	2		T349	1
all_values[0]	auto[1]	auto[1]	auto[1]	56	1		T257	1		T258	1		T352	1
all_values[1]	auto[0]	auto[0]	auto[0]	47	1		T258	2		T352	1		T348	1
all_values[1]	auto[0]	auto[0]	auto[1]	35	1		T257	2		T349	2		T354	2
all_values[1]	auto[0]	auto[1]	auto[0]	51	1		T352	1		T348	2		T349	1
all_values[1]	auto[0]	auto[1]	auto[1]	32	1		T258	1		T352	1		T353	1
all_values[1]	auto[1]	auto[0]	auto[1]	69	1		T257	2		T352	1		T348	1
all_values[1]	auto[1]	auto[1]	auto[1]	47	1		T258	1		T353	3		T349	1
all_values[2]	auto[0]	auto[0]	auto[0]	54	1		T257	4		T352	2		T348	1
all_values[2]	auto[0]	auto[0]	auto[1]	43	1		T258	2		T349	1		T351	1
all_values[2]	auto[0]	auto[1]	auto[0]	42	1		T352	1		T348	2		T349	2
all_values[2]	auto[0]	auto[1]	auto[1]	25	1		T353	1		T350	2		T351	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T258	1		T352	1		T348	1
all_values[2]	auto[1]	auto[1]	auto[1]	51	1		T258	1		T353	1		T349	1
all_values[3]	auto[0]	auto[0]	auto[0]	60	1		T257	2		T352	1		T350	1
all_values[3]	auto[0]	auto[0]	auto[1]	32	1		T257	1		T258	1		T352	1
all_values[3]	auto[0]	auto[1]	auto[0]	45	1		T353	1		T351	1		T354	2
all_values[3]	auto[0]	auto[1]	auto[1]	27	1		T258	1		T348	1		T350	1
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T257	1		T352	2		T348	1
all_values[3]	auto[1]	auto[1]	auto[1]	57	1		T258	2		T348	2		T353	2
all_values[4]	auto[0]	auto[0]	auto[0]	55	1		T257	1		T352	2		T348	1
all_values[4]	auto[0]	auto[0]	auto[1]	35	1		T257	1		T258	1		T348	1
all_values[4]	auto[0]	auto[1]	auto[0]	54	1		T258	1		T354	2		T355	2
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T257	1		T352	1		T353	1
all_values[4]	auto[1]	auto[0]	auto[1]	70	1		T258	2		T348	1		T353	1
all_values[4]	auto[1]	auto[1]	auto[1]	43	1		T257	1		T352	1		T348	1
all_values[5]	auto[0]	auto[0]	auto[0]	56	1		T258	2		T352	2		T348	1
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T258	1		T348	1		T356	1
all_values[5]	auto[0]	auto[1]	auto[0]	52	1		T257	3		T352	1		T356	1
all_values[5]	auto[0]	auto[1]	auto[1]	36	1		T349	2		T350	2		T351	3
all_values[5]	auto[1]	auto[0]	auto[1]	67	1		T257	1		T258	1		T352	1
all_values[5]	auto[1]	auto[1]	auto[1]	45	1		T348	1		T353	1		T350	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal