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Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2

Go back
Group Instances:
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0

Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 303 1 T44 3 T247 1 T253 2
auto[1] 854 1 T44 7 T46 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 422 1 T44 3 T247 1 T253 2
auto[1] 931 1 T44 7 T46 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 345 1 T44 3 T247 1 T253 2
auto[1] 883 1 T44 7 T46 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 264 1 T44 3 T247 1 T253 2
auto[1] 837 1 T44 7 T46 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 278 1 T44 2 T247 1 T253 2
auto[1] 899 1 T44 7 T46 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 394 1 T44 3 T247 1 T253 2
auto[1] 911 1 T44 7 T46 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 325 1 T44 3 T247 1 T253 2
auto[1] 867 1 T44 7 T46 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 674 1 T44 1 T188 1 T253 1
auto[1] 794 1 T44 9 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 838 1 T44 1 T188 1 T253 1
auto[1] 829 1 T44 9 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 741 1 T44 1 T188 1 T253 1
auto[1] 801 1 T44 9 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 644 1 T44 1 T253 1 T254 2
auto[1] 787 1 T44 9 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 770 1 T44 1 T188 1 T253 1
auto[1] 734 1 T44 8 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 804 1 T44 1 T188 1 T253 1
auto[1] 829 1 T44 9 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 708 1 T44 1 T188 1 T253 1
auto[1] 795 1 T44 8 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 415 1 T44 8 T188 1 T248 2
auto[1] 865 1 T44 2 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 539 1 T44 8 T188 1 T248 1
auto[1] 844 1 T44 2 T247 1 T188 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 462 1 T44 6 T188 1 T248 2
auto[1] 896 1 T44 2 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 393 1 T44 8 T188 1 T248 2
auto[1] 850 1 T44 1 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 490 1 T44 8 T188 1 T248 2
auto[1] 832 1 T44 1 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 515 1 T44 7 T188 1 T248 2
auto[1] 931 1 T44 1 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 347 1 T44 8 T188 1 T248 2
auto[1] 885 1 T44 2 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 570 1 T44 2 T46 1 T247 1
auto[1] 688 1 T44 8 T188 2 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 693 1 T44 2 T46 1 T247 1
auto[1] 769 1 T44 8 T188 1 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 621 1 T44 2 T46 1 T247 1
auto[1] 724 1 T44 8 T188 2 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 550 1 T44 2 T46 1 T247 1
auto[1] 667 1 T44 8 T188 2 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 535 1 T44 2 T46 1 T247 1
auto[1] 846 1 T44 6 T188 2 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 670 1 T44 2 T46 1 T247 1
auto[1] 756 1 T44 6 T188 2 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 597 1 T44 1 T46 1 T247 1
auto[1] 703 1 T44 7 T188 2 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 351 1 T44 3 T46 1 T248 1
auto[1] 717 1 T44 7 T247 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 522 1 T44 3 T46 1 T248 1
auto[1] 734 1 T44 7 T247 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306 1 T44 2 T46 1 T248 1
auto[1] 738 1 T44 7 T247 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 204 1 T44 3 T46 1 T248 1
auto[1] 709 1 T44 7 T247 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 335 1 T44 3 T46 1 T248 1
auto[1] 749 1 T44 7 T247 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 488 1 T44 3 T46 1 T248 1
auto[1] 743 1 T44 7 T247 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 391 1 T44 3 T46 1 T248 1
auto[1] 721 1 T44 7 T247 1 T188 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 471 1 T44 2 T248 1 T253 1
auto[1] 556 1 T44 8 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 678 1 T44 1 T188 1 T248 1
auto[1] 548 1 T44 8 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 554 1 T44 2 T188 1 T248 1
auto[1] 546 1 T44 8 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 435 1 T44 2 T188 1 T248 1
auto[1] 551 1 T44 7 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 600 1 T44 2 T188 1 T248 1
auto[1] 551 1 T44 8 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 637 1 T44 2 T248 1 T253 1
auto[1] 547 1 T44 8 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 516 1 T44 2 T188 1 T248 1
auto[1] 542 1 T44 7 T46 1 T247 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 495 1 T46 1 T248 2 T253 1
auto[1] 256 1 T44 5 T247 1 T188 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%