| T1080 |
/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2349964723 |
|
|
Feb 25 01:15:39 PM PST 24 |
Feb 25 01:18:48 PM PST 24 |
2157452400 ps |
| T402 |
/workspace/coverage/default/1.flash_ctrl_sec_info_access.1741733892 |
|
|
Feb 25 01:04:34 PM PST 24 |
Feb 25 01:05:52 PM PST 24 |
2042537100 ps |
| T1081 |
/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2175612356 |
|
|
Feb 25 01:08:19 PM PST 24 |
Feb 25 01:09:20 PM PST 24 |
10036141000 ps |
| T1082 |
/workspace/coverage/default/47.flash_ctrl_hw_sec_otp.4043241846 |
|
|
Feb 25 01:16:18 PM PST 24 |
Feb 25 01:17:15 PM PST 24 |
3171898100 ps |
| T1083 |
/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.2158552269 |
|
|
Feb 25 01:04:59 PM PST 24 |
Feb 25 01:18:09 PM PST 24 |
80136899600 ps |
| T1084 |
/workspace/coverage/default/30.flash_ctrl_disable.584334735 |
|
|
Feb 25 01:14:55 PM PST 24 |
Feb 25 01:15:16 PM PST 24 |
63649400 ps |
| T1085 |
/workspace/coverage/default/8.flash_ctrl_rw.1632569294 |
|
|
Feb 25 01:09:11 PM PST 24 |
Feb 25 01:18:01 PM PST 24 |
4258010500 ps |
| T1086 |
/workspace/coverage/default/10.flash_ctrl_wo.1116672515 |
|
|
Feb 25 01:09:58 PM PST 24 |
Feb 25 01:13:39 PM PST 24 |
9779828400 ps |
| T1087 |
/workspace/coverage/default/49.flash_ctrl_sec_info_access.3160235561 |
|
|
Feb 25 01:16:21 PM PST 24 |
Feb 25 01:17:38 PM PST 24 |
3333413400 ps |
| T1088 |
/workspace/coverage/default/7.flash_ctrl_mp_regions.2372426728 |
|
|
Feb 25 01:08:36 PM PST 24 |
Feb 25 01:25:34 PM PST 24 |
13671707800 ps |
| T1089 |
/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.3631013278 |
|
|
Feb 25 01:04:17 PM PST 24 |
Feb 25 01:04:39 PM PST 24 |
32531800 ps |
| T1090 |
/workspace/coverage/default/56.flash_ctrl_connect.3487554615 |
|
|
Feb 25 01:16:28 PM PST 24 |
Feb 25 01:16:44 PM PST 24 |
79107300 ps |
| T1091 |
/workspace/coverage/default/6.flash_ctrl_wo.4236590580 |
|
|
Feb 25 01:08:05 PM PST 24 |
Feb 25 01:11:10 PM PST 24 |
15581790600 ps |
| T1092 |
/workspace/coverage/default/17.flash_ctrl_wo.2465561894 |
|
|
Feb 25 01:12:25 PM PST 24 |
Feb 25 01:14:59 PM PST 24 |
2166307300 ps |
| T1093 |
/workspace/coverage/default/9.flash_ctrl_rw_serr.3356906779 |
|
|
Feb 25 01:09:30 PM PST 24 |
Feb 25 01:18:33 PM PST 24 |
14604436800 ps |
| T1094 |
/workspace/coverage/default/63.flash_ctrl_connect.220881503 |
|
|
Feb 25 01:16:39 PM PST 24 |
Feb 25 01:16:55 PM PST 24 |
168416400 ps |
| T1095 |
/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.2808768684 |
|
|
Feb 25 01:10:11 PM PST 24 |
Feb 25 01:10:25 PM PST 24 |
25572700 ps |
| T1096 |
/workspace/coverage/default/52.flash_ctrl_otp_reset.2395546170 |
|
|
Feb 25 01:16:25 PM PST 24 |
Feb 25 01:18:36 PM PST 24 |
62372900 ps |
| T1097 |
/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3233374273 |
|
|
Feb 25 01:09:39 PM PST 24 |
Feb 25 01:10:07 PM PST 24 |
74861200 ps |
| T1098 |
/workspace/coverage/default/55.flash_ctrl_connect.1403765102 |
|
|
Feb 25 01:16:29 PM PST 24 |
Feb 25 01:16:46 PM PST 24 |
22459200 ps |
| T200 |
/workspace/coverage/default/8.flash_ctrl_rw_derr.212767727 |
|
|
Feb 25 01:09:12 PM PST 24 |
Feb 25 01:17:48 PM PST 24 |
2967803700 ps |
| T1099 |
/workspace/coverage/default/3.flash_ctrl_stress_all.2993426249 |
|
|
Feb 25 01:06:31 PM PST 24 |
Feb 25 01:15:44 PM PST 24 |
164793000 ps |
| T1100 |
/workspace/coverage/default/45.flash_ctrl_connect.1965880376 |
|
|
Feb 25 01:16:22 PM PST 24 |
Feb 25 01:16:38 PM PST 24 |
45121300 ps |
| T1101 |
/workspace/coverage/default/49.flash_ctrl_alert_test.3024924646 |
|
|
Feb 25 01:16:23 PM PST 24 |
Feb 25 01:16:37 PM PST 24 |
37642800 ps |
| T1102 |
/workspace/coverage/default/4.flash_ctrl_ro.3294160015 |
|
|
Feb 25 01:07:02 PM PST 24 |
Feb 25 01:08:50 PM PST 24 |
511775400 ps |
| T1103 |
/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1391747322 |
|
|
Feb 25 01:07:17 PM PST 24 |
Feb 25 01:18:28 PM PST 24 |
347430044800 ps |
| T1104 |
/workspace/coverage/default/31.flash_ctrl_alert_test.1412553783 |
|
|
Feb 25 01:14:57 PM PST 24 |
Feb 25 01:15:11 PM PST 24 |
51681200 ps |
| T1105 |
/workspace/coverage/default/2.flash_ctrl_phy_arb.2843426309 |
|
|
Feb 25 01:04:49 PM PST 24 |
Feb 25 01:13:01 PM PST 24 |
5520035900 ps |
| T1106 |
/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.3888314634 |
|
|
Feb 25 01:15:49 PM PST 24 |
Feb 25 01:17:13 PM PST 24 |
1066174300 ps |
| T1107 |
/workspace/coverage/default/9.flash_ctrl_re_evict.2480811698 |
|
|
Feb 25 01:09:37 PM PST 24 |
Feb 25 01:10:10 PM PST 24 |
80141500 ps |
| T1108 |
/workspace/coverage/default/3.flash_ctrl_full_mem_access.2739829431 |
|
|
Feb 25 01:05:54 PM PST 24 |
Feb 25 01:44:21 PM PST 24 |
178912458000 ps |
| T1109 |
/workspace/coverage/default/46.flash_ctrl_otp_reset.2994495850 |
|
|
Feb 25 01:16:19 PM PST 24 |
Feb 25 01:18:10 PM PST 24 |
84586100 ps |
| T1110 |
/workspace/coverage/default/5.flash_ctrl_alert_test.769016469 |
|
|
Feb 25 01:07:51 PM PST 24 |
Feb 25 01:08:05 PM PST 24 |
38916800 ps |
| T1111 |
/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3606165872 |
|
|
Feb 25 01:11:58 PM PST 24 |
Feb 25 01:12:12 PM PST 24 |
47177100 ps |
| T1112 |
/workspace/coverage/default/77.flash_ctrl_connect.3199962578 |
|
|
Feb 25 01:16:47 PM PST 24 |
Feb 25 01:17:01 PM PST 24 |
33245600 ps |
| T1113 |
/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2633452335 |
|
|
Feb 25 01:08:07 PM PST 24 |
Feb 25 01:14:48 PM PST 24 |
170600549100 ps |
| T192 |
/workspace/coverage/default/3.flash_ctrl_sec_cm.1404676372 |
|
|
Feb 25 01:06:33 PM PST 24 |
Feb 25 02:26:06 PM PST 24 |
3193485400 ps |
| T1114 |
/workspace/coverage/default/32.flash_ctrl_alert_test.596764118 |
|
|
Feb 25 01:15:05 PM PST 24 |
Feb 25 01:15:19 PM PST 24 |
325892500 ps |
| T1115 |
/workspace/coverage/default/7.flash_ctrl_connect.1813071915 |
|
|
Feb 25 01:08:46 PM PST 24 |
Feb 25 01:09:03 PM PST 24 |
33232300 ps |
| T1116 |
/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.783240915 |
|
|
Feb 25 01:09:58 PM PST 24 |
Feb 25 01:12:51 PM PST 24 |
7637790400 ps |
| T1117 |
/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.2749003221 |
|
|
Feb 25 01:09:38 PM PST 24 |
Feb 25 01:09:51 PM PST 24 |
26160100 ps |
| T1118 |
/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.405509074 |
|
|
Feb 25 01:12:28 PM PST 24 |
Feb 25 01:14:34 PM PST 24 |
14286117800 ps |
| T383 |
/workspace/coverage/default/44.flash_ctrl_sec_info_access.3251261826 |
|
|
Feb 25 01:15:59 PM PST 24 |
Feb 25 01:17:08 PM PST 24 |
5735294400 ps |
| T1119 |
/workspace/coverage/default/2.flash_ctrl_rw_serr.690437037 |
|
|
Feb 25 01:05:21 PM PST 24 |
Feb 25 01:12:55 PM PST 24 |
6305927300 ps |
| T1120 |
/workspace/coverage/default/19.flash_ctrl_smoke.3630694164 |
|
|
Feb 25 01:13:08 PM PST 24 |
Feb 25 01:14:23 PM PST 24 |
51423600 ps |
| T1121 |
/workspace/coverage/default/14.flash_ctrl_smoke.3082592659 |
|
|
Feb 25 01:11:21 PM PST 24 |
Feb 25 01:13:27 PM PST 24 |
164047800 ps |
| T1122 |
/workspace/coverage/default/8.flash_ctrl_wo.367009684 |
|
|
Feb 25 01:08:56 PM PST 24 |
Feb 25 01:12:11 PM PST 24 |
2412451400 ps |
| T1123 |
/workspace/coverage/default/39.flash_ctrl_rw_evict.3307050611 |
|
|
Feb 25 01:15:37 PM PST 24 |
Feb 25 01:16:08 PM PST 24 |
74643300 ps |
| T1124 |
/workspace/coverage/default/1.flash_ctrl_rw_evict.2501804999 |
|
|
Feb 25 01:04:33 PM PST 24 |
Feb 25 01:05:10 PM PST 24 |
90103800 ps |
| T1125 |
/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2553819502 |
|
|
Feb 25 01:15:56 PM PST 24 |
Feb 25 01:17:41 PM PST 24 |
3767983900 ps |
| T1126 |
/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.1044530759 |
|
|
Feb 25 01:14:01 PM PST 24 |
Feb 25 01:17:48 PM PST 24 |
8064593100 ps |
| T1127 |
/workspace/coverage/default/16.flash_ctrl_sec_info_access.2532501172 |
|
|
Feb 25 01:12:13 PM PST 24 |
Feb 25 01:13:26 PM PST 24 |
2300481400 ps |
| T1128 |
/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3441558985 |
|
|
Feb 25 01:11:23 PM PST 24 |
Feb 25 01:11:36 PM PST 24 |
25394500 ps |
| T1129 |
/workspace/coverage/default/7.flash_ctrl_disable.4127819642 |
|
|
Feb 25 01:08:47 PM PST 24 |
Feb 25 01:09:09 PM PST 24 |
11226200 ps |
| T396 |
/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.3328997367 |
|
|
Feb 25 01:08:47 PM PST 24 |
Feb 25 01:22:00 PM PST 24 |
40129344000 ps |
| T1130 |
/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3015842749 |
|
|
Feb 25 01:05:52 PM PST 24 |
Feb 25 01:06:06 PM PST 24 |
25106300 ps |
| T1131 |
/workspace/coverage/default/3.flash_ctrl_otp_reset.1964572230 |
|
|
Feb 25 01:05:49 PM PST 24 |
Feb 25 01:07:46 PM PST 24 |
40705100 ps |
| T1132 |
/workspace/coverage/default/8.flash_ctrl_error_prog_win.117561150 |
|
|
Feb 25 01:08:52 PM PST 24 |
Feb 25 01:25:42 PM PST 24 |
1548088900 ps |
| T1133 |
/workspace/coverage/default/12.flash_ctrl_connect.99518270 |
|
|
Feb 25 01:10:53 PM PST 24 |
Feb 25 01:11:09 PM PST 24 |
22996400 ps |
| T1134 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.2256253513 |
|
|
Feb 25 01:04:21 PM PST 24 |
Feb 25 01:06:02 PM PST 24 |
62014264500 ps |
| T187 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1964636635 |
|
|
Feb 25 12:34:37 PM PST 24 |
Feb 25 12:34:56 PM PST 24 |
48783800 ps |
| T44 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1790281853 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:42:38 PM PST 24 |
386943400 ps |
| T45 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.333142345 |
|
|
Feb 25 12:34:49 PM PST 24 |
Feb 25 12:35:20 PM PST 24 |
55419900 ps |
| T46 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4089488122 |
|
|
Feb 25 12:34:43 PM PST 24 |
Feb 25 12:35:02 PM PST 24 |
64809500 ps |
| T1135 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2970381361 |
|
|
Feb 25 12:35:09 PM PST 24 |
Feb 25 12:35:25 PM PST 24 |
15432000 ps |
| T257 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.4018728356 |
|
|
Feb 25 12:35:27 PM PST 24 |
Feb 25 12:35:46 PM PST 24 |
15448700 ps |
| T246 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2221642777 |
|
|
Feb 25 12:34:56 PM PST 24 |
Feb 25 12:35:28 PM PST 24 |
752486700 ps |
| T213 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3803443695 |
|
|
Feb 25 12:34:42 PM PST 24 |
Feb 25 12:35:02 PM PST 24 |
217834300 ps |
| T247 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4004013397 |
|
|
Feb 25 12:34:58 PM PST 24 |
Feb 25 12:35:14 PM PST 24 |
21407700 ps |
| T230 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3741722769 |
|
|
Feb 25 12:34:38 PM PST 24 |
Feb 25 12:34:52 PM PST 24 |
60303300 ps |
| T1136 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3691467878 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
45630400 ps |
| T1137 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.763669493 |
|
|
Feb 25 12:34:44 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
15766600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.958395691 |
|
|
Feb 25 12:35:11 PM PST 24 |
Feb 25 12:35:28 PM PST 24 |
24072300 ps |
| T214 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1730814804 |
|
|
Feb 25 12:34:40 PM PST 24 |
Feb 25 12:34:56 PM PST 24 |
53770900 ps |
| T188 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.4077609602 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:11 PM PST 24 |
178745000 ps |
| T224 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1045670935 |
|
|
Feb 25 12:34:56 PM PST 24 |
Feb 25 12:35:17 PM PST 24 |
108186200 ps |
| T1139 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4163137399 |
|
|
Feb 25 12:35:12 PM PST 24 |
Feb 25 12:35:28 PM PST 24 |
50944400 ps |
| T225 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1272431261 |
|
|
Feb 25 12:35:11 PM PST 24 |
Feb 25 12:35:28 PM PST 24 |
117365100 ps |
| T1140 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3245327247 |
|
|
Feb 25 12:34:58 PM PST 24 |
Feb 25 12:35:17 PM PST 24 |
21238200 ps |
| T258 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2968254421 |
|
|
Feb 25 12:35:17 PM PST 24 |
Feb 25 12:35:30 PM PST 24 |
44455800 ps |
| T248 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.122256887 |
|
|
Feb 25 12:34:52 PM PST 24 |
Feb 25 12:35:10 PM PST 24 |
105595000 ps |
| T352 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3740058339 |
|
|
Feb 25 12:36:30 PM PST 24 |
Feb 25 12:36:44 PM PST 24 |
14585700 ps |
| T348 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3819384157 |
|
|
Feb 25 12:35:31 PM PST 24 |
Feb 25 12:35:45 PM PST 24 |
73804200 ps |
| T1141 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3956121212 |
|
|
Feb 25 12:35:15 PM PST 24 |
Feb 25 12:35:31 PM PST 24 |
11052200 ps |
| T353 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1480812175 |
|
|
Feb 25 12:35:03 PM PST 24 |
Feb 25 12:35:17 PM PST 24 |
15512600 ps |
| T1142 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3256054542 |
|
|
Feb 25 12:34:46 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
16938800 ps |
| T1143 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2049015673 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:02 PM PST 24 |
12376800 ps |
| T253 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1759791210 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:06 PM PST 24 |
50856000 ps |
| T1144 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1669624242 |
|
|
Feb 25 12:34:59 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
12589300 ps |
| T349 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1961218239 |
|
|
Feb 25 12:34:50 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
37538400 ps |
| T254 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2196744348 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:09 PM PST 24 |
68545700 ps |
| T295 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.526667028 |
|
|
Feb 25 12:36:33 PM PST 24 |
Feb 25 12:36:50 PM PST 24 |
102925400 ps |
| T350 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2865554057 |
|
|
Feb 25 12:36:02 PM PST 24 |
Feb 25 12:36:16 PM PST 24 |
17478300 ps |
| T351 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.888093340 |
|
|
Feb 25 12:34:55 PM PST 24 |
Feb 25 12:35:11 PM PST 24 |
58037200 ps |
| T1145 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.297017982 |
|
|
Feb 25 12:36:02 PM PST 24 |
Feb 25 12:36:37 PM PST 24 |
164162100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.4135226594 |
|
|
Feb 25 12:34:46 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
149068400 ps |
| T368 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.577040561 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
64702800 ps |
| T1147 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2300818684 |
|
|
Feb 25 12:34:53 PM PST 24 |
Feb 25 12:35:07 PM PST 24 |
19105200 ps |
| T226 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.630366669 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:49:50 PM PST 24 |
553385100 ps |
| T1148 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.535026686 |
|
|
Feb 25 12:34:57 PM PST 24 |
Feb 25 12:35:13 PM PST 24 |
18115600 ps |
| T354 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3651559771 |
|
|
Feb 25 12:35:01 PM PST 24 |
Feb 25 12:35:16 PM PST 24 |
48482400 ps |
| T356 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.5227595 |
|
|
Feb 25 12:35:19 PM PST 24 |
Feb 25 12:35:33 PM PST 24 |
18731800 ps |
| T355 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.895004452 |
|
|
Feb 25 12:35:00 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
55183800 ps |
| T1149 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.971595651 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
44002300 ps |
| T1150 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.988766832 |
|
|
Feb 25 12:35:23 PM PST 24 |
Feb 25 12:35:40 PM PST 24 |
12940300 ps |
| T1151 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3642762030 |
|
|
Feb 25 12:35:03 PM PST 24 |
Feb 25 12:35:17 PM PST 24 |
59743300 ps |
| T1152 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3570037295 |
|
|
Feb 25 12:36:20 PM PST 24 |
Feb 25 12:36:33 PM PST 24 |
19821100 ps |
| T1153 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2220884522 |
|
|
Feb 25 12:35:14 PM PST 24 |
Feb 25 12:35:29 PM PST 24 |
55341100 ps |
| T227 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.801021189 |
|
|
Feb 25 12:34:53 PM PST 24 |
Feb 25 12:49:42 PM PST 24 |
649738500 ps |
| T1154 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1348164843 |
|
|
Feb 25 12:35:01 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
76130800 ps |
| T1155 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2964392558 |
|
|
Feb 25 12:34:44 PM PST 24 |
Feb 25 12:35:01 PM PST 24 |
29938300 ps |
| T1156 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3599155947 |
|
|
Feb 25 12:34:46 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
109727900 ps |
| T296 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3373334894 |
|
|
Feb 25 12:35:09 PM PST 24 |
Feb 25 12:35:25 PM PST 24 |
396230700 ps |
| T228 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.406531577 |
|
|
Feb 25 12:34:55 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
183080500 ps |
| T256 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1128295824 |
|
|
Feb 25 12:34:52 PM PST 24 |
Feb 25 12:35:09 PM PST 24 |
126597200 ps |
| T259 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.989185983 |
|
|
Feb 25 12:35:00 PM PST 24 |
Feb 25 12:35:21 PM PST 24 |
217576200 ps |
| T1157 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2790204721 |
|
|
Feb 25 12:36:17 PM PST 24 |
Feb 25 12:36:30 PM PST 24 |
26737300 ps |
| T1158 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3414949415 |
|
|
Feb 25 12:35:09 PM PST 24 |
Feb 25 12:35:23 PM PST 24 |
15809700 ps |
| T369 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2815285188 |
|
|
Feb 25 12:34:52 PM PST 24 |
Feb 25 12:36:06 PM PST 24 |
3287866600 ps |
| T270 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.920162328 |
|
|
Feb 25 12:34:54 PM PST 24 |
Feb 25 12:42:38 PM PST 24 |
1467574300 ps |
| T1159 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.453303417 |
|
|
Feb 25 12:34:58 PM PST 24 |
Feb 25 12:35:28 PM PST 24 |
185184200 ps |
| T261 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.881429286 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:10 PM PST 24 |
160746200 ps |
| T231 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1444002216 |
|
|
Feb 25 12:34:40 PM PST 24 |
Feb 25 12:34:54 PM PST 24 |
16334900 ps |
| T1160 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3115123131 |
|
|
Feb 25 12:35:03 PM PST 24 |
Feb 25 12:35:19 PM PST 24 |
50430500 ps |
| T1161 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2271812989 |
|
|
Feb 25 12:34:58 PM PST 24 |
Feb 25 12:35:12 PM PST 24 |
31813500 ps |
| T1162 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3793466944 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:10 PM PST 24 |
249693600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3884705793 |
|
|
Feb 25 12:35:02 PM PST 24 |
Feb 25 12:35:18 PM PST 24 |
26891100 ps |
| T361 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1302348002 |
|
|
Feb 25 12:35:21 PM PST 24 |
Feb 25 12:50:21 PM PST 24 |
3551152900 ps |
| T232 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2510498682 |
|
|
Feb 25 12:34:44 PM PST 24 |
Feb 25 12:35:02 PM PST 24 |
46787700 ps |
| T266 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1060007957 |
|
|
Feb 25 12:35:03 PM PST 24 |
Feb 25 12:35:24 PM PST 24 |
265873100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2065051496 |
|
|
Feb 25 12:35:06 PM PST 24 |
Feb 25 12:35:43 PM PST 24 |
657813800 ps |
| T1165 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2390694213 |
|
|
Feb 25 12:35:09 PM PST 24 |
Feb 25 12:35:23 PM PST 24 |
15055100 ps |
| T1166 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.694965612 |
|
|
Feb 25 12:35:14 PM PST 24 |
Feb 25 12:35:31 PM PST 24 |
41981200 ps |
| T1167 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3539072534 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:02 PM PST 24 |
25145500 ps |
| T1168 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.936532647 |
|
|
Feb 25 12:35:08 PM PST 24 |
Feb 25 12:35:28 PM PST 24 |
325368200 ps |
| T1169 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4013091363 |
|
|
Feb 25 12:35:00 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
16075400 ps |
| T1170 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4170099678 |
|
|
Feb 25 12:35:12 PM PST 24 |
Feb 25 12:35:26 PM PST 24 |
73410200 ps |
| T1171 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.828571632 |
|
|
Feb 25 12:34:44 PM PST 24 |
Feb 25 12:36:08 PM PST 24 |
8772594700 ps |
| T1172 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3295224577 |
|
|
Feb 25 12:35:09 PM PST 24 |
Feb 25 12:35:24 PM PST 24 |
77905600 ps |
| T297 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1025228839 |
|
|
Feb 25 12:35:08 PM PST 24 |
Feb 25 12:41:37 PM PST 24 |
433788000 ps |
| T1173 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1951490826 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
198788400 ps |
| T1174 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1334699550 |
|
|
Feb 25 12:34:58 PM PST 24 |
Feb 25 12:35:21 PM PST 24 |
71873900 ps |
| T300 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2937405877 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:35:06 PM PST 24 |
268298800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.813102522 |
|
|
Feb 25 12:35:16 PM PST 24 |
Feb 25 12:35:30 PM PST 24 |
59552200 ps |
| T265 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1812282841 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
63452800 ps |
| T1176 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2422595129 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:09 PM PST 24 |
75991500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4127414296 |
|
|
Feb 25 12:34:57 PM PST 24 |
Feb 25 12:35:16 PM PST 24 |
62860600 ps |
| T1178 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2191061026 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
33985500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3687668580 |
|
|
Feb 25 12:34:45 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
25935100 ps |
| T233 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.662182938 |
|
|
Feb 25 12:34:50 PM PST 24 |
Feb 25 12:35:03 PM PST 24 |
46467200 ps |
| T264 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2102699746 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:08 PM PST 24 |
119812100 ps |
| T359 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.972055308 |
|
|
Feb 25 12:34:37 PM PST 24 |
Feb 25 12:42:16 PM PST 24 |
736146400 ps |
| T1180 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3235112424 |
|
|
Feb 25 12:36:02 PM PST 24 |
Feb 25 12:36:22 PM PST 24 |
52514500 ps |
| T1181 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2015847755 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:07 PM PST 24 |
18294300 ps |
| T1182 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2631076807 |
|
|
Feb 25 12:34:54 PM PST 24 |
Feb 25 12:35:07 PM PST 24 |
16339800 ps |
| T1183 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3306225279 |
|
|
Feb 25 12:35:00 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
170392800 ps |
| T358 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1963608422 |
|
|
Feb 25 12:35:13 PM PST 24 |
Feb 25 12:50:09 PM PST 24 |
866630000 ps |
| T298 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3855853549 |
|
|
Feb 25 12:34:50 PM PST 24 |
Feb 25 12:35:09 PM PST 24 |
142809000 ps |
| T299 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.581278531 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:35:07 PM PST 24 |
912314000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1869844347 |
|
|
Feb 25 12:35:11 PM PST 24 |
Feb 25 12:35:30 PM PST 24 |
331125700 ps |
| T360 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2782730314 |
|
|
Feb 25 12:34:58 PM PST 24 |
Feb 25 12:47:44 PM PST 24 |
704341200 ps |
| T269 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.69149000 |
|
|
Feb 25 12:36:16 PM PST 24 |
Feb 25 12:51:03 PM PST 24 |
579434600 ps |
| T255 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.166330219 |
|
|
Feb 25 12:34:58 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
68837500 ps |
| T301 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3573043320 |
|
|
Feb 25 12:34:52 PM PST 24 |
Feb 25 12:35:09 PM PST 24 |
42954700 ps |
| T263 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3318711669 |
|
|
Feb 25 12:34:49 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
33617800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.811657391 |
|
|
Feb 25 12:34:49 PM PST 24 |
Feb 25 12:35:28 PM PST 24 |
78529300 ps |
| T262 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3542106259 |
|
|
Feb 25 12:35:10 PM PST 24 |
Feb 25 12:35:30 PM PST 24 |
489972000 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1321893300 |
|
|
Feb 25 12:35:01 PM PST 24 |
Feb 25 12:35:17 PM PST 24 |
37117900 ps |
| T1187 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.78699197 |
|
|
Feb 25 12:36:02 PM PST 24 |
Feb 25 12:36:19 PM PST 24 |
31118200 ps |
| T1188 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3462110260 |
|
|
Feb 25 12:34:43 PM PST 24 |
Feb 25 12:35:00 PM PST 24 |
15448500 ps |
| T1189 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1657808642 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
65933500 ps |
| T363 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3628804104 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:42:26 PM PST 24 |
454273100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3214252744 |
|
|
Feb 25 12:35:10 PM PST 24 |
Feb 25 12:35:23 PM PST 24 |
58144200 ps |
| T1191 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3371978857 |
|
|
Feb 25 12:35:10 PM PST 24 |
Feb 25 12:35:26 PM PST 24 |
16264400 ps |
| T1192 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3193603302 |
|
|
Feb 25 12:35:04 PM PST 24 |
Feb 25 12:35:18 PM PST 24 |
26653100 ps |
| T1193 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2715015498 |
|
|
Feb 25 12:35:13 PM PST 24 |
Feb 25 12:35:49 PM PST 24 |
627429200 ps |
| T1194 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.395911433 |
|
|
Feb 25 12:34:46 PM PST 24 |
Feb 25 12:35:03 PM PST 24 |
151256200 ps |
| T1195 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1188777050 |
|
|
Feb 25 12:34:32 PM PST 24 |
Feb 25 12:34:48 PM PST 24 |
13989900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3572076809 |
|
|
Feb 25 12:34:42 PM PST 24 |
Feb 25 12:34:56 PM PST 24 |
18051200 ps |
| T229 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3145813152 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:02 PM PST 24 |
26034100 ps |
| T1197 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3007213028 |
|
|
Feb 25 12:34:50 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
15803300 ps |
| T1198 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2733552131 |
|
|
Feb 25 12:35:07 PM PST 24 |
Feb 25 12:35:23 PM PST 24 |
41299800 ps |
| T268 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1856883527 |
|
|
Feb 25 12:34:44 PM PST 24 |
Feb 25 12:35:08 PM PST 24 |
173635000 ps |
| T267 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.429895367 |
|
|
Feb 25 12:35:11 PM PST 24 |
Feb 25 12:35:32 PM PST 24 |
126772600 ps |
| T1199 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3067658721 |
|
|
Feb 25 12:34:57 PM PST 24 |
Feb 25 12:35:10 PM PST 24 |
17609100 ps |
| T302 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3192109939 |
|
|
Feb 25 12:34:52 PM PST 24 |
Feb 25 12:49:57 PM PST 24 |
889706700 ps |
| T1200 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1401678670 |
|
|
Feb 25 12:34:55 PM PST 24 |
Feb 25 12:35:11 PM PST 24 |
40987000 ps |
| T1201 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1000226970 |
|
|
Feb 25 12:35:11 PM PST 24 |
Feb 25 12:35:26 PM PST 24 |
151615300 ps |
| T1202 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4038195712 |
|
|
Feb 25 12:34:40 PM PST 24 |
Feb 25 12:35:18 PM PST 24 |
238581400 ps |
| T271 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2631153996 |
|
|
Feb 25 12:34:46 PM PST 24 |
Feb 25 12:42:29 PM PST 24 |
703833700 ps |
| T1203 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1880656054 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:08 PM PST 24 |
98413600 ps |
| T1204 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4118817581 |
|
|
Feb 25 12:34:46 PM PST 24 |
Feb 25 12:35:24 PM PST 24 |
1782609400 ps |
| T1205 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.786631350 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
11852400 ps |
| T1206 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3944436980 |
|
|
Feb 25 12:35:07 PM PST 24 |
Feb 25 12:35:24 PM PST 24 |
109937700 ps |
| T1207 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1663319252 |
|
|
Feb 25 12:35:13 PM PST 24 |
Feb 25 12:35:29 PM PST 24 |
25571300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.814587588 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
25729100 ps |
| T1209 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.860114714 |
|
|
Feb 25 12:35:10 PM PST 24 |
Feb 25 12:35:24 PM PST 24 |
181397900 ps |
| T1210 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3000222399 |
|
|
Feb 25 12:35:17 PM PST 24 |
Feb 25 12:35:34 PM PST 24 |
30911300 ps |
| T362 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1050408839 |
|
|
Feb 25 12:34:53 PM PST 24 |
Feb 25 12:47:28 PM PST 24 |
2730302900 ps |
| T1211 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1629217193 |
|
|
Feb 25 12:35:01 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
17818700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2077398666 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:07 PM PST 24 |
12432200 ps |
| T1213 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.951163555 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:06 PM PST 24 |
126103600 ps |
| T1214 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.459163249 |
|
|
Feb 25 12:36:30 PM PST 24 |
Feb 25 12:36:47 PM PST 24 |
39903800 ps |
| T1215 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.300420696 |
|
|
Feb 25 12:35:15 PM PST 24 |
Feb 25 12:35:35 PM PST 24 |
196971000 ps |
| T303 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3914779464 |
|
|
Feb 25 12:35:07 PM PST 24 |
Feb 25 12:35:27 PM PST 24 |
1346461800 ps |
| T1216 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1380688638 |
|
|
Feb 25 12:34:57 PM PST 24 |
Feb 25 12:35:14 PM PST 24 |
49003200 ps |
| T1217 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1291066435 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
38239700 ps |
| T1218 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1808256614 |
|
|
Feb 25 12:34:46 PM PST 24 |
Feb 25 12:35:19 PM PST 24 |
1113578000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2096527931 |
|
|
Feb 25 12:35:09 PM PST 24 |
Feb 25 12:35:23 PM PST 24 |
38371800 ps |
| T1220 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.380110792 |
|
|
Feb 25 12:34:49 PM PST 24 |
Feb 25 12:35:03 PM PST 24 |
41446300 ps |
| T1221 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4020090970 |
|
|
Feb 25 12:35:00 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
17851500 ps |
| T1222 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2152624801 |
|
|
Feb 25 12:34:56 PM PST 24 |
Feb 25 12:35:10 PM PST 24 |
33448800 ps |
| T1223 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1644827621 |
|
|
Feb 25 12:34:41 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
37992200 ps |
| T364 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4226741155 |
|
|
Feb 25 12:35:02 PM PST 24 |
Feb 25 12:47:41 PM PST 24 |
356216400 ps |
| T1224 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1255003087 |
|
|
Feb 25 12:34:58 PM PST 24 |
Feb 25 12:35:32 PM PST 24 |
248933600 ps |
| T1225 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4050870255 |
|
|
Feb 25 12:34:52 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
53602800 ps |
| T1226 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1358536000 |
|
|
Feb 25 12:34:57 PM PST 24 |
Feb 25 12:35:12 PM PST 24 |
184659100 ps |
| T1227 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3984734958 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
190140300 ps |
| T357 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.597744679 |
|
|
Feb 25 12:34:40 PM PST 24 |
Feb 25 12:34:57 PM PST 24 |
334501600 ps |
| T1228 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2596791606 |
|
|
Feb 25 12:35:07 PM PST 24 |
Feb 25 12:35:21 PM PST 24 |
125356100 ps |
| T1229 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1030913859 |
|
|
Feb 25 12:34:34 PM PST 24 |
Feb 25 12:34:48 PM PST 24 |
30191900 ps |
| T1230 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3535968259 |
|
|
Feb 25 12:34:54 PM PST 24 |
Feb 25 12:35:09 PM PST 24 |
46806800 ps |
| T1231 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2416375850 |
|
|
Feb 25 12:34:55 PM PST 24 |
Feb 25 12:35:11 PM PST 24 |
111552200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2862035464 |
|
|
Feb 25 12:34:49 PM PST 24 |
Feb 25 12:35:36 PM PST 24 |
902657400 ps |
| T1233 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3801746967 |
|
|
Feb 25 12:35:06 PM PST 24 |
Feb 25 12:35:20 PM PST 24 |
83877600 ps |
| T1234 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3177380425 |
|
|
Feb 25 12:35:02 PM PST 24 |
Feb 25 12:35:18 PM PST 24 |
39671300 ps |
| T304 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1387166626 |
|
|
Feb 25 12:34:48 PM PST 24 |
Feb 25 12:36:04 PM PST 24 |
6831106000 ps |
| T1235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.244201129 |
|
|
Feb 25 12:34:53 PM PST 24 |
Feb 25 12:35:40 PM PST 24 |
164101100 ps |
| T1236 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1949364510 |
|
|
Feb 25 12:35:28 PM PST 24 |
Feb 25 12:35:42 PM PST 24 |
45631400 ps |
| T1237 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.86606843 |
|
|
Feb 25 12:34:55 PM PST 24 |
Feb 25 12:35:08 PM PST 24 |
14787200 ps |
| T1238 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2250202063 |
|
|
Feb 25 12:34:57 PM PST 24 |
Feb 25 12:35:13 PM PST 24 |
41965700 ps |
| T260 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.626220982 |
|
|
Feb 25 12:34:53 PM PST 24 |
Feb 25 12:47:29 PM PST 24 |
2821715300 ps |
| T1239 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2516489904 |
|
|
Feb 25 12:34:59 PM PST 24 |
Feb 25 12:35:21 PM PST 24 |
116838500 ps |
| T1240 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2738571157 |
|
|
Feb 25 12:34:51 PM PST 24 |
Feb 25 12:35:05 PM PST 24 |
51386400 ps |
| T365 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3620189785 |
|
|
Feb 25 12:35:03 PM PST 24 |
Feb 25 12:49:57 PM PST 24 |
1753520900 ps |
| T1241 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3250198496 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:35:02 PM PST 24 |
95228500 ps |
| T1242 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.291337494 |
|
|
Feb 25 12:34:50 PM PST 24 |
Feb 25 12:35:04 PM PST 24 |
26256900 ps |
| T1243 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2521889600 |
|
|
Feb 25 12:35:00 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
16080200 ps |
| T1244 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.990750328 |
|
|
Feb 25 12:35:04 PM PST 24 |
Feb 25 12:35:18 PM PST 24 |
17789600 ps |
| T1245 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1787755396 |
|
|
Feb 25 12:35:04 PM PST 24 |
Feb 25 12:35:18 PM PST 24 |
87938000 ps |
| T1246 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4248605701 |
|
|
Feb 25 12:35:20 PM PST 24 |
Feb 25 12:35:38 PM PST 24 |
55184800 ps |
| T1247 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3849087739 |
|
|
Feb 25 12:34:44 PM PST 24 |
Feb 25 12:36:08 PM PST 24 |
12857959100 ps |
| T1248 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.874374242 |
|
|
Feb 25 12:34:47 PM PST 24 |
Feb 25 12:35:10 PM PST 24 |
35072500 ps |
| T1249 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.268975766 |
|
|
Feb 25 12:35:01 PM PST 24 |
Feb 25 12:35:15 PM PST 24 |
56263200 ps |
| T305 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2734510053 |
|
|
Feb 25 12:34:31 PM PST 24 |
Feb 25 12:35:38 PM PST 24 |
3171121400 ps |
| T1250 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2124010164 |
|
|
Feb 25 12:34:52 PM PST 24 |
Feb 25 12:35:07 PM PST 24 |
44821400 ps |
| T1251 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.961672833 |
|
|
Feb 25 12:36:16 PM PST 24 |
Feb 25 12:36:30 PM PST 24 |
15202900 ps |
| T1252 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3045707914 |
|
|
Feb 25 12:34:43 PM PST 24 |
Feb 25 12:35:00 PM PST 24 |
70207300 ps |
| T1253 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1279112486 |
|
|
Feb 25 12:35:04 PM PST 24 |
Feb 25 12:35:17 PM PST 24 |
11927700 ps |
| T1254 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3947296363 |
|
|
Feb 25 12:34:59 PM PST 24 |
Feb 25 12:35:17 PM PST 24 |
156349400 ps |