Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	336690	1		T1	2		T2	1		T3	2
all_values[1]	336690	1		T1	2		T2	1		T3	2
all_values[2]	336690	1		T1	2		T2	1		T3	2
all_values[3]	336690	1		T1	2		T2	1		T3	2
all_values[4]	336690	1		T1	2		T2	1		T3	2
all_values[5]	336690	1		T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10350	1		T1	12		T2	6		T3	12
auto[1]	2009790	1		T7	9492		T8	12858		T19	19524

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1635541	1		T1	10		T2	6		T3	11
auto[1]	384599	1		T1	2		T3	1		T4	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1293	1		T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	454	1		T1	1		T3	1		T4	1
all_values[0]	auto[1]	auto[0]	272930	1		T7	1582		T8	2143		T19	3254
all_values[0]	auto[1]	auto[1]	62013	1		T59	2394		T69	4732		T70	2496
all_values[1]	auto[0]	auto[0]	1652	1		T1	2		T2	1		T3	2
all_values[1]	auto[0]	auto[1]	74	1		T255	4		T256	1		T329	2
all_values[1]	auto[1]	auto[0]	264130	1		T7	1582		T8	2143		T19	3254
all_values[1]	auto[1]	auto[1]	70834	1		T59	4681		T70	4213		T71	4723
all_values[2]	auto[0]	auto[0]	1574	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	128	1		T26	1		T72	1		T73	1
all_values[2]	auto[1]	auto[0]	329891	1		T7	1582		T8	2143		T19	3254
all_values[2]	auto[1]	auto[1]	5097	1		T74	355		T75	449		T76	10
all_values[3]	auto[0]	auto[0]	1578	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	137	1		T26	1		T72	1		T73	1
all_values[3]	auto[1]	auto[0]	187538	1		T7	791		T8	660		T19	791
all_values[3]	auto[1]	auto[1]	147437	1		T7	791		T8	1483		T19	2463
all_values[4]	auto[0]	auto[0]	1177	1		T1	1		T2	1		T3	2
all_values[4]	auto[0]	auto[1]	546	1		T1	1		T4	1		T17	1
all_values[4]	auto[1]	auto[0]	237304	1		T7	791		T8	1082		T19	2124
all_values[4]	auto[1]	auto[1]	97663	1		T7	791		T8	1061		T19	1130
all_values[5]	auto[0]	auto[0]	1581	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	156	1		T18	1		T9	1		T27	2
all_values[5]	auto[1]	auto[0]	334893	1		T7	1582		T8	2143		T19	3254
all_values[5]	auto[1]	auto[1]	60	1		T254	2		T255	2		T256	2