Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1290 |
1 |
|
T1 |
21 |
|
T17 |
18 |
|
T23 |
5 |
| others[1] |
1298 |
1 |
|
T1 |
23 |
|
T17 |
24 |
|
T23 |
2 |
| others[2] |
1259 |
1 |
|
T1 |
18 |
|
T17 |
18 |
|
T7 |
1 |
| others[3] |
2053 |
1 |
|
T1 |
33 |
|
T16 |
1 |
|
T17 |
28 |
| false |
634 |
1 |
|
T1 |
6 |
|
T17 |
12 |
|
T23 |
2 |
| true |
421 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T1 |
2 |
|
T348 |
3 |
|
T53 |
8 |
| others[1] |
99 |
1 |
|
T1 |
5 |
|
T5 |
1 |
|
T43 |
1 |
| others[2] |
109 |
1 |
|
T1 |
1 |
|
T27 |
1 |
|
T63 |
1 |
| others[3] |
180 |
1 |
|
T1 |
6 |
|
T27 |
1 |
|
T210 |
2 |
| false |
71 |
1 |
|
T1 |
2 |
|
T347 |
1 |
|
T126 |
2 |
| true |
6394 |
1 |
|
T1 |
85 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
260 |
1 |
|
T1 |
2 |
|
T43 |
1 |
|
T19 |
1 |
| others[1] |
231 |
1 |
|
T1 |
15 |
|
T5 |
1 |
|
T8 |
1 |
| others[2] |
233 |
1 |
|
T1 |
9 |
|
T347 |
1 |
|
T78 |
1 |
| others[3] |
401 |
1 |
|
T1 |
15 |
|
T59 |
1 |
|
T63 |
1 |
| false |
122 |
1 |
|
T1 |
5 |
|
T77 |
1 |
|
T117 |
1 |
| true |
5708 |
1 |
|
T1 |
55 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1027 |
1 |
|
T1 |
20 |
|
T17 |
12 |
|
T8 |
1 |
| others[1] |
1070 |
1 |
|
T1 |
15 |
|
T17 |
12 |
|
T27 |
1 |
| others[2] |
1096 |
1 |
|
T1 |
18 |
|
T16 |
1 |
|
T17 |
3 |
| others[3] |
1756 |
1 |
|
T1 |
36 |
|
T17 |
15 |
|
T23 |
6 |
| false |
576 |
1 |
|
T1 |
12 |
|
T17 |
3 |
|
T7 |
1 |
| true |
1430 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T17 |
55 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T1 |
14 |
|
T63 |
1 |
|
T189 |
1 |
| others[1] |
217 |
1 |
|
T1 |
7 |
|
T27 |
2 |
|
T352 |
1 |
| others[2] |
248 |
1 |
|
T1 |
9 |
|
T210 |
1 |
|
T78 |
1 |
| others[3] |
407 |
1 |
|
T1 |
16 |
|
T5 |
1 |
|
T8 |
1 |
| false |
125 |
1 |
|
T1 |
2 |
|
T43 |
1 |
|
T27 |
1 |
| true |
5742 |
1 |
|
T1 |
53 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T1 |
12 |
|
T43 |
1 |
|
T27 |
2 |
| others[1] |
221 |
1 |
|
T1 |
3 |
|
T351 |
1 |
|
T350 |
1 |
| others[2] |
230 |
1 |
|
T1 |
8 |
|
T349 |
1 |
|
T210 |
2 |
| others[3] |
374 |
1 |
|
T1 |
24 |
|
T347 |
1 |
|
T126 |
1 |
| false |
124 |
1 |
|
T1 |
2 |
|
T348 |
3 |
|
T53 |
3 |
| true |
5782 |
1 |
|
T1 |
52 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1282 |
1 |
|
T1 |
20 |
|
T17 |
17 |
|
T23 |
3 |
| others[1] |
1259 |
1 |
|
T1 |
21 |
|
T17 |
25 |
|
T7 |
1 |
| others[2] |
1244 |
1 |
|
T1 |
20 |
|
T17 |
14 |
|
T18 |
1 |
| others[3] |
2107 |
1 |
|
T1 |
26 |
|
T16 |
1 |
|
T17 |
33 |
| false |
623 |
1 |
|
T1 |
14 |
|
T17 |
11 |
|
T23 |
2 |
| true |
440 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T1 |
21 |
|
T17 |
22 |
|
T23 |
4 |
| others[1] |
1265 |
1 |
|
T1 |
19 |
|
T16 |
1 |
|
T17 |
17 |
| others[2] |
1247 |
1 |
|
T1 |
15 |
|
T17 |
21 |
|
T23 |
1 |
| others[3] |
2080 |
1 |
|
T1 |
33 |
|
T17 |
29 |
|
T23 |
4 |
| false |
667 |
1 |
|
T1 |
13 |
|
T17 |
11 |
|
T7 |
1 |
| true |
415 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T1 |
2 |
|
T9 |
1 |
|
T126 |
3 |
| others[1] |
123 |
1 |
|
T1 |
4 |
|
T126 |
1 |
|
T351 |
1 |
| others[2] |
99 |
1 |
|
T1 |
5 |
|
T210 |
1 |
|
T348 |
2 |
| others[3] |
193 |
1 |
|
T1 |
6 |
|
T5 |
1 |
|
T43 |
1 |
| false |
53 |
1 |
|
T348 |
1 |
|
T53 |
2 |
|
T353 |
1 |
| true |
6392 |
1 |
|
T1 |
84 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T1 |
8 |
|
T20 |
1 |
|
T210 |
1 |
| others[1] |
224 |
1 |
|
T1 |
11 |
|
T9 |
1 |
|
T69 |
1 |
| others[2] |
260 |
1 |
|
T1 |
6 |
|
T8 |
1 |
|
T79 |
1 |
| others[3] |
400 |
1 |
|
T1 |
14 |
|
T5 |
1 |
|
T43 |
1 |
| false |
109 |
1 |
|
T1 |
6 |
|
T27 |
1 |
|
T63 |
1 |
| true |
5728 |
1 |
|
T1 |
56 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1073 |
1 |
|
T1 |
16 |
|
T16 |
1 |
|
T17 |
7 |
| others[1] |
1044 |
1 |
|
T1 |
21 |
|
T4 |
1 |
|
T17 |
9 |
| others[2] |
1067 |
1 |
|
T1 |
15 |
|
T17 |
9 |
|
T23 |
1 |
| others[3] |
1802 |
1 |
|
T1 |
40 |
|
T17 |
18 |
|
T7 |
1 |
| false |
549 |
1 |
|
T1 |
9 |
|
T17 |
8 |
|
T23 |
1 |
| true |
1420 |
1 |
|
T5 |
1 |
|
T17 |
49 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T1 |
9 |
|
T347 |
1 |
|
T78 |
1 |
| others[1] |
224 |
1 |
|
T1 |
13 |
|
T69 |
1 |
|
T351 |
1 |
| others[2] |
201 |
1 |
|
T1 |
8 |
|
T210 |
1 |
|
T126 |
1 |
| others[3] |
379 |
1 |
|
T1 |
19 |
|
T19 |
1 |
|
T20 |
1 |
| false |
126 |
1 |
|
T1 |
6 |
|
T348 |
1 |
|
T22 |
1 |
| true |
5778 |
1 |
|
T1 |
46 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T1 |
9 |
|
T62 |
1 |
|
T53 |
12 |
| others[1] |
218 |
1 |
|
T1 |
8 |
|
T27 |
2 |
|
T348 |
1 |
| others[2] |
221 |
1 |
|
T1 |
11 |
|
T349 |
1 |
|
T348 |
2 |
| others[3] |
376 |
1 |
|
T1 |
10 |
|
T9 |
1 |
|
T126 |
2 |
| false |
122 |
1 |
|
T1 |
6 |
|
T63 |
1 |
|
T352 |
1 |
| true |
5786 |
1 |
|
T1 |
57 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1301 |
1 |
|
T1 |
21 |
|
T16 |
1 |
|
T17 |
25 |
| others[1] |
1222 |
1 |
|
T1 |
22 |
|
T17 |
21 |
|
T18 |
1 |
| others[2] |
1266 |
1 |
|
T1 |
19 |
|
T17 |
10 |
|
T23 |
3 |
| others[3] |
2058 |
1 |
|
T1 |
34 |
|
T17 |
32 |
|
T23 |
3 |
| false |
662 |
1 |
|
T1 |
5 |
|
T17 |
12 |
|
T130 |
1 |
| true |
446 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T1 |
16 |
|
T17 |
25 |
|
T19 |
1 |
| others[1] |
1207 |
1 |
|
T1 |
19 |
|
T16 |
1 |
|
T17 |
22 |
| others[2] |
1273 |
1 |
|
T1 |
22 |
|
T17 |
15 |
|
T23 |
4 |
| others[3] |
2132 |
1 |
|
T1 |
36 |
|
T17 |
31 |
|
T7 |
1 |
| false |
675 |
1 |
|
T1 |
8 |
|
T17 |
7 |
|
T24 |
1 |
| true |
416 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T1 |
5 |
|
T348 |
2 |
|
T22 |
1 |
| others[1] |
124 |
1 |
|
T1 |
3 |
|
T210 |
1 |
|
T347 |
1 |
| others[2] |
99 |
1 |
|
T1 |
1 |
|
T69 |
1 |
|
T351 |
1 |
| others[3] |
185 |
1 |
|
T1 |
8 |
|
T126 |
2 |
|
T62 |
1 |
| false |
60 |
1 |
|
T1 |
1 |
|
T9 |
1 |
|
T210 |
1 |
| true |
6386 |
1 |
|
T1 |
83 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T1 |
8 |
|
T27 |
1 |
|
T347 |
1 |
| others[1] |
230 |
1 |
|
T1 |
8 |
|
T8 |
1 |
|
T43 |
1 |
| others[2] |
243 |
1 |
|
T1 |
6 |
|
T20 |
1 |
|
T27 |
1 |
| others[3] |
442 |
1 |
|
T1 |
20 |
|
T5 |
1 |
|
T39 |
1 |
| false |
114 |
1 |
|
T1 |
3 |
|
T53 |
5 |
|
T54 |
4 |
| true |
5694 |
1 |
|
T1 |
56 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1088 |
1 |
|
T1 |
27 |
|
T16 |
1 |
|
T17 |
7 |
| others[1] |
1019 |
1 |
|
T1 |
21 |
|
T17 |
7 |
|
T23 |
3 |
| others[2] |
1086 |
1 |
|
T1 |
22 |
|
T17 |
10 |
|
T7 |
1 |
| others[3] |
1781 |
1 |
|
T1 |
26 |
|
T17 |
21 |
|
T23 |
3 |
| false |
550 |
1 |
|
T1 |
5 |
|
T17 |
3 |
|
T24 |
2 |
| true |
1431 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T17 |
52 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T1 |
11 |
|
T43 |
1 |
|
T63 |
1 |
| others[1] |
235 |
1 |
|
T1 |
9 |
|
T210 |
1 |
|
T79 |
1 |
| others[2] |
234 |
1 |
|
T1 |
10 |
|
T8 |
1 |
|
T19 |
1 |
| others[3] |
375 |
1 |
|
T1 |
20 |
|
T27 |
1 |
|
T59 |
1 |
| false |
122 |
1 |
|
T1 |
2 |
|
T210 |
1 |
|
T53 |
6 |
| true |
5752 |
1 |
|
T1 |
49 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T1 |
6 |
|
T5 |
1 |
|
T210 |
1 |
| others[1] |
196 |
1 |
|
T1 |
6 |
|
T126 |
1 |
|
T348 |
4 |
| others[2] |
236 |
1 |
|
T1 |
12 |
|
T348 |
4 |
|
T53 |
11 |
| others[3] |
350 |
1 |
|
T1 |
16 |
|
T43 |
1 |
|
T351 |
2 |
| false |
126 |
1 |
|
T1 |
8 |
|
T347 |
1 |
|
T79 |
1 |
| true |
5818 |
1 |
|
T1 |
53 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1264 |
1 |
|
T1 |
21 |
|
T17 |
27 |
|
T23 |
2 |
| others[1] |
1301 |
1 |
|
T1 |
20 |
|
T17 |
19 |
|
T23 |
1 |
| others[2] |
1222 |
1 |
|
T1 |
16 |
|
T17 |
24 |
|
T7 |
1 |
| others[3] |
2054 |
1 |
|
T1 |
37 |
|
T16 |
1 |
|
T17 |
22 |
| false |
660 |
1 |
|
T1 |
7 |
|
T17 |
8 |
|
T23 |
6 |
| true |
454 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T1 |
19 |
|
T17 |
25 |
|
T23 |
2 |
| others[1] |
1323 |
1 |
|
T1 |
20 |
|
T17 |
15 |
|
T23 |
1 |
| others[2] |
1218 |
1 |
|
T1 |
19 |
|
T17 |
20 |
|
T7 |
1 |
| others[3] |
2116 |
1 |
|
T1 |
32 |
|
T16 |
1 |
|
T17 |
34 |
| false |
622 |
1 |
|
T1 |
11 |
|
T17 |
6 |
|
T29 |
7 |
| true |
427 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T1 |
4 |
|
T5 |
1 |
|
T126 |
1 |
| others[1] |
91 |
1 |
|
T1 |
3 |
|
T126 |
1 |
|
T348 |
2 |
| others[2] |
125 |
1 |
|
T1 |
1 |
|
T27 |
1 |
|
T210 |
2 |
| others[3] |
180 |
1 |
|
T1 |
6 |
|
T347 |
1 |
|
T126 |
1 |
| false |
55 |
1 |
|
T1 |
2 |
|
T351 |
1 |
|
T348 |
1 |
| true |
6397 |
1 |
|
T1 |
85 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T1 |
8 |
|
T43 |
1 |
|
T20 |
1 |
| others[1] |
230 |
1 |
|
T1 |
15 |
|
T349 |
1 |
|
T347 |
1 |
| others[2] |
249 |
1 |
|
T1 |
8 |
|
T8 |
1 |
|
T27 |
1 |
| others[3] |
378 |
1 |
|
T1 |
16 |
|
T19 |
1 |
|
T27 |
2 |
| false |
113 |
1 |
|
T1 |
1 |
|
T39 |
1 |
|
T115 |
1 |
| true |
5751 |
1 |
|
T1 |
53 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1038 |
1 |
|
T1 |
24 |
|
T4 |
1 |
|
T17 |
7 |
| others[1] |
1074 |
1 |
|
T1 |
22 |
|
T17 |
9 |
|
T23 |
3 |
| others[2] |
1053 |
1 |
|
T1 |
16 |
|
T16 |
1 |
|
T17 |
9 |
| others[3] |
1792 |
1 |
|
T1 |
27 |
|
T17 |
15 |
|
T6 |
1 |
| false |
564 |
1 |
|
T1 |
12 |
|
T17 |
5 |
|
T23 |
3 |
| true |
1434 |
1 |
|
T5 |
1 |
|
T17 |
55 |
|
T18 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T1 |
11 |
|
T349 |
1 |
|
T63 |
1 |
| others[1] |
220 |
1 |
|
T1 |
11 |
|
T19 |
1 |
|
T59 |
1 |
| others[2] |
221 |
1 |
|
T1 |
13 |
|
T20 |
1 |
|
T27 |
2 |
| others[3] |
373 |
1 |
|
T1 |
11 |
|
T8 |
1 |
|
T9 |
1 |
| false |
129 |
1 |
|
T1 |
4 |
|
T53 |
6 |
|
T54 |
2 |
| true |
5782 |
1 |
|
T1 |
51 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T1 |
5 |
|
T9 |
1 |
|
T210 |
1 |
| others[1] |
235 |
1 |
|
T1 |
6 |
|
T59 |
1 |
|
T69 |
1 |
| others[2] |
238 |
1 |
|
T1 |
12 |
|
T43 |
1 |
|
T126 |
1 |
| others[3] |
349 |
1 |
|
T1 |
13 |
|
T126 |
1 |
|
T352 |
1 |
| false |
115 |
1 |
|
T1 |
4 |
|
T27 |
1 |
|
T351 |
1 |
| true |
5794 |
1 |
|
T1 |
61 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T1 |
15 |
|
T16 |
1 |
|
T17 |
21 |
| others[1] |
1223 |
1 |
|
T1 |
23 |
|
T17 |
18 |
|
T23 |
3 |
| others[2] |
1281 |
1 |
|
T1 |
19 |
|
T17 |
23 |
|
T7 |
1 |
| others[3] |
2080 |
1 |
|
T1 |
35 |
|
T17 |
26 |
|
T23 |
1 |
| false |
699 |
1 |
|
T1 |
9 |
|
T17 |
12 |
|
T24 |
2 |
| true |
442 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7 |
1 |
|
T4 |
1 |
|
T103 |
1 |
|
T354 |
1 |
| others[1] |
8 |
1 |
|
T97 |
2 |
|
T28 |
1 |
|
T355 |
1 |
| others[2] |
12 |
1 |
|
T144 |
1 |
|
T356 |
1 |
|
T357 |
1 |
| others[3] |
12 |
1 |
|
T6 |
1 |
|
T101 |
1 |
|
T104 |
1 |
| false |
5 |
1 |
|
T358 |
1 |
|
T359 |
1 |
|
T360 |
1 |
| true |
49 |
1 |
|
T3 |
1 |
|
T61 |
1 |
|
T96 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T361 |
1 |
|
T362 |
1 |
|
T363 |
1 |
| others[1] |
3 |
1 |
|
T364 |
1 |
|
T365 |
1 |
|
T366 |
1 |
| others[2] |
5 |
1 |
|
T157 |
1 |
|
T367 |
1 |
|
T368 |
1 |
| others[3] |
2 |
1 |
|
T369 |
1 |
|
T370 |
1 |
|
- |
- |
| false |
12 |
1 |
|
T26 |
1 |
|
T73 |
1 |
|
T371 |
1 |
| true |
24 |
1 |
|
T72 |
1 |
|
T158 |
1 |
|
T372 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T373 |
1 |
|
T374 |
1 |
|
T375 |
1 |
| others[1] |
3 |
1 |
|
T376 |
1 |
|
T377 |
1 |
|
T378 |
1 |
| others[2] |
3 |
1 |
|
T379 |
1 |
|
T380 |
1 |
|
T381 |
1 |
| others[3] |
3 |
1 |
|
T369 |
1 |
|
T382 |
1 |
|
T383 |
1 |
| false |
10 |
1 |
|
T72 |
1 |
|
T361 |
1 |
|
T367 |
1 |
| true |
27 |
1 |
|
T26 |
1 |
|
T73 |
1 |
|
T157 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |