Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10556 |
1 |
|
T1 |
23 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
794 |
1 |
|
T1 |
22 |
|
T43 |
1 |
|
T23 |
2 |
| others[2] |
838 |
1 |
|
T1 |
16 |
|
T23 |
1 |
|
T24 |
1 |
| others[3] |
1340 |
1 |
|
T1 |
29 |
|
T7 |
1 |
|
T19 |
1 |
| false |
399 |
1 |
|
T1 |
11 |
|
T16 |
1 |
|
T44 |
1 |
| true |
534 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2454 |
1 |
|
T1 |
7 |
|
T2 |
7 |
|
T17 |
20 |
| others[1] |
2472 |
1 |
|
T1 |
19 |
|
T2 |
6 |
|
T3 |
1 |
| others[2] |
2471 |
1 |
|
T1 |
4 |
|
T2 |
11 |
|
T17 |
23 |
| others[3] |
4146 |
1 |
|
T1 |
9 |
|
T2 |
17 |
|
T3 |
1 |
| false |
1322 |
1 |
|
T1 |
6 |
|
T2 |
3 |
|
T17 |
8 |
| true |
1596 |
1 |
|
T1 |
56 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9998 |
1 |
|
T1 |
16 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
272 |
1 |
|
T1 |
11 |
|
T7 |
1 |
|
T20 |
1 |
| others[2] |
271 |
1 |
|
T1 |
10 |
|
T27 |
2 |
|
T59 |
1 |
| others[3] |
461 |
1 |
|
T1 |
14 |
|
T9 |
1 |
|
T34 |
1 |
| false |
156 |
1 |
|
T1 |
4 |
|
T25 |
1 |
|
T56 |
1 |
| true |
3303 |
1 |
|
T1 |
46 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10252 |
1 |
|
T1 |
12 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
469 |
1 |
|
T1 |
8 |
|
T8 |
1 |
|
T20 |
1 |
| others[2] |
495 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T23 |
1 |
| others[3] |
810 |
1 |
|
T1 |
16 |
|
T9 |
1 |
|
T43 |
1 |
| false |
231 |
1 |
|
T1 |
3 |
|
T18 |
1 |
|
T23 |
3 |
| true |
2204 |
1 |
|
T1 |
51 |
|
T16 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10001 |
1 |
|
T1 |
10 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
262 |
1 |
|
T1 |
10 |
|
T9 |
1 |
|
T20 |
1 |
| others[2] |
278 |
1 |
|
T1 |
8 |
|
T5 |
1 |
|
T27 |
1 |
| others[3] |
454 |
1 |
|
T1 |
16 |
|
T63 |
1 |
|
T25 |
1 |
| false |
138 |
1 |
|
T1 |
6 |
|
T217 |
1 |
|
T348 |
1 |
| true |
3328 |
1 |
|
T1 |
51 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9996 |
1 |
|
T1 |
11 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
264 |
1 |
|
T1 |
12 |
|
T7 |
1 |
|
T43 |
1 |
| others[2] |
265 |
1 |
|
T1 |
10 |
|
T16 |
1 |
|
T5 |
1 |
| others[3] |
426 |
1 |
|
T1 |
13 |
|
T27 |
1 |
|
T59 |
1 |
| false |
146 |
1 |
|
T1 |
6 |
|
T63 |
1 |
|
T56 |
1 |
| true |
3364 |
1 |
|
T1 |
49 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10602 |
1 |
|
T1 |
19 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
812 |
1 |
|
T1 |
14 |
|
T7 |
1 |
|
T18 |
1 |
| others[2] |
785 |
1 |
|
T1 |
23 |
|
T16 |
1 |
|
T23 |
3 |
| others[3] |
1311 |
1 |
|
T1 |
34 |
|
T23 |
6 |
|
T24 |
5 |
| false |
424 |
1 |
|
T1 |
11 |
|
T23 |
2 |
|
T52 |
1 |
| true |
527 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10514 |
1 |
|
T1 |
17 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
788 |
1 |
|
T1 |
19 |
|
T23 |
1 |
|
T24 |
3 |
| others[2] |
811 |
1 |
|
T1 |
22 |
|
T43 |
1 |
|
T23 |
6 |
| others[3] |
1359 |
1 |
|
T1 |
33 |
|
T16 |
1 |
|
T7 |
1 |
| false |
423 |
1 |
|
T1 |
10 |
|
T23 |
1 |
|
T44 |
1 |
| true |
534 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2543 |
1 |
|
T1 |
12 |
|
T2 |
8 |
|
T17 |
19 |
| others[1] |
2425 |
1 |
|
T1 |
9 |
|
T2 |
10 |
|
T3 |
1 |
| others[2] |
2475 |
1 |
|
T1 |
9 |
|
T2 |
13 |
|
T17 |
21 |
| others[3] |
4194 |
1 |
|
T1 |
17 |
|
T2 |
8 |
|
T3 |
1 |
| false |
1279 |
1 |
|
T1 |
5 |
|
T2 |
5 |
|
T17 |
8 |
| true |
1513 |
1 |
|
T1 |
49 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9972 |
1 |
|
T1 |
7 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
298 |
1 |
|
T1 |
12 |
|
T16 |
1 |
|
T89 |
1 |
| others[2] |
254 |
1 |
|
T1 |
8 |
|
T27 |
3 |
|
T91 |
1 |
| others[3] |
459 |
1 |
|
T1 |
17 |
|
T59 |
1 |
|
T34 |
1 |
| false |
146 |
1 |
|
T1 |
7 |
|
T352 |
1 |
|
T348 |
1 |
| true |
3300 |
1 |
|
T1 |
50 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10217 |
1 |
|
T1 |
6 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
486 |
1 |
|
T1 |
7 |
|
T6 |
1 |
|
T23 |
3 |
| others[2] |
433 |
1 |
|
T1 |
7 |
|
T59 |
1 |
|
T24 |
1 |
| others[3] |
764 |
1 |
|
T1 |
19 |
|
T16 |
1 |
|
T5 |
1 |
| false |
234 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T27 |
1 |
| true |
2295 |
1 |
|
T1 |
56 |
|
T7 |
1 |
|
T23 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9982 |
1 |
|
T1 |
9 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
283 |
1 |
|
T1 |
6 |
|
T9 |
1 |
|
T27 |
1 |
| others[2] |
266 |
1 |
|
T1 |
9 |
|
T27 |
1 |
|
T60 |
1 |
| others[3] |
441 |
1 |
|
T1 |
22 |
|
T34 |
1 |
|
T212 |
1 |
| false |
130 |
1 |
|
T1 |
3 |
|
T69 |
1 |
|
T56 |
1 |
| true |
3327 |
1 |
|
T1 |
52 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9990 |
1 |
|
T1 |
9 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
274 |
1 |
|
T1 |
9 |
|
T27 |
1 |
|
T59 |
1 |
| others[2] |
271 |
1 |
|
T1 |
9 |
|
T27 |
2 |
|
T44 |
1 |
| others[3] |
417 |
1 |
|
T1 |
23 |
|
T25 |
2 |
|
T56 |
1 |
| false |
130 |
1 |
|
T1 |
4 |
|
T27 |
2 |
|
T126 |
1 |
| true |
3347 |
1 |
|
T1 |
47 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10531 |
1 |
|
T1 |
15 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
779 |
1 |
|
T1 |
22 |
|
T9 |
1 |
|
T23 |
1 |
| others[2] |
801 |
1 |
|
T1 |
21 |
|
T23 |
2 |
|
T27 |
2 |
| others[3] |
1365 |
1 |
|
T1 |
28 |
|
T7 |
1 |
|
T18 |
1 |
| false |
433 |
1 |
|
T1 |
15 |
|
T23 |
1 |
|
T91 |
1 |
| true |
520 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10591 |
1 |
|
T1 |
13 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
777 |
1 |
|
T1 |
23 |
|
T43 |
1 |
|
T23 |
1 |
| others[2] |
797 |
1 |
|
T1 |
19 |
|
T16 |
1 |
|
T23 |
3 |
| others[3] |
1285 |
1 |
|
T1 |
33 |
|
T7 |
1 |
|
T23 |
4 |
| false |
432 |
1 |
|
T1 |
13 |
|
T24 |
2 |
|
T52 |
1 |
| true |
547 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2500 |
1 |
|
T1 |
5 |
|
T2 |
9 |
|
T17 |
16 |
| others[1] |
2421 |
1 |
|
T1 |
11 |
|
T2 |
5 |
|
T16 |
1 |
| others[2] |
2546 |
1 |
|
T1 |
10 |
|
T2 |
10 |
|
T3 |
2 |
| others[3] |
4108 |
1 |
|
T1 |
17 |
|
T2 |
11 |
|
T17 |
35 |
| false |
1276 |
1 |
|
T1 |
7 |
|
T2 |
9 |
|
T17 |
11 |
| true |
1578 |
1 |
|
T1 |
51 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9979 |
1 |
|
T1 |
4 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
277 |
1 |
|
T1 |
8 |
|
T5 |
1 |
|
T9 |
1 |
| others[2] |
298 |
1 |
|
T1 |
16 |
|
T27 |
1 |
|
T56 |
1 |
| others[3] |
460 |
1 |
|
T1 |
17 |
|
T27 |
2 |
|
T63 |
1 |
| false |
136 |
1 |
|
T1 |
4 |
|
T8 |
1 |
|
T212 |
1 |
| true |
3279 |
1 |
|
T1 |
52 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10195 |
1 |
|
T1 |
14 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
498 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T9 |
1 |
| others[2] |
474 |
1 |
|
T1 |
15 |
|
T27 |
1 |
|
T69 |
1 |
| others[3] |
808 |
1 |
|
T1 |
17 |
|
T16 |
1 |
|
T6 |
1 |
| false |
241 |
1 |
|
T1 |
5 |
|
T23 |
2 |
|
T130 |
1 |
| true |
2213 |
1 |
|
T1 |
41 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9994 |
1 |
|
T1 |
13 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
294 |
1 |
|
T1 |
8 |
|
T20 |
1 |
|
T27 |
1 |
| others[2] |
275 |
1 |
|
T1 |
11 |
|
T8 |
1 |
|
T25 |
1 |
| others[3] |
440 |
1 |
|
T1 |
16 |
|
T43 |
1 |
|
T69 |
1 |
| false |
156 |
1 |
|
T1 |
8 |
|
T27 |
1 |
|
T63 |
1 |
| true |
3270 |
1 |
|
T1 |
45 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9984 |
1 |
|
T1 |
10 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
257 |
1 |
|
T1 |
11 |
|
T25 |
2 |
|
T74 |
1 |
| others[2] |
267 |
1 |
|
T1 |
10 |
|
T9 |
1 |
|
T27 |
1 |
| others[3] |
405 |
1 |
|
T1 |
18 |
|
T44 |
1 |
|
T60 |
1 |
| false |
147 |
1 |
|
T1 |
5 |
|
T43 |
1 |
|
T240 |
1 |
| true |
3369 |
1 |
|
T1 |
47 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10523 |
1 |
|
T1 |
21 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
825 |
1 |
|
T1 |
20 |
|
T9 |
1 |
|
T23 |
3 |
| others[2] |
830 |
1 |
|
T1 |
15 |
|
T7 |
1 |
|
T23 |
2 |
| others[3] |
1312 |
1 |
|
T1 |
35 |
|
T23 |
3 |
|
T130 |
1 |
| false |
416 |
1 |
|
T1 |
10 |
|
T16 |
1 |
|
T23 |
2 |
| true |
523 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10575 |
1 |
|
T1 |
12 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
806 |
1 |
|
T1 |
17 |
|
T16 |
1 |
|
T7 |
1 |
| others[2] |
775 |
1 |
|
T1 |
25 |
|
T23 |
4 |
|
T24 |
4 |
| others[3] |
1341 |
1 |
|
T1 |
38 |
|
T23 |
4 |
|
T44 |
1 |
| false |
389 |
1 |
|
T1 |
9 |
|
T23 |
1 |
|
T24 |
1 |
| true |
543 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2495 |
1 |
|
T1 |
8 |
|
T2 |
8 |
|
T3 |
1 |
| others[1] |
2476 |
1 |
|
T1 |
11 |
|
T2 |
6 |
|
T17 |
17 |
| others[2] |
2491 |
1 |
|
T1 |
14 |
|
T2 |
9 |
|
T3 |
1 |
| others[3] |
4154 |
1 |
|
T1 |
14 |
|
T2 |
16 |
|
T16 |
1 |
| false |
1238 |
1 |
|
T1 |
6 |
|
T2 |
5 |
|
T17 |
7 |
| true |
1575 |
1 |
|
T1 |
48 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10002 |
1 |
|
T1 |
6 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
279 |
1 |
|
T1 |
16 |
|
T89 |
1 |
|
T91 |
1 |
| others[2] |
265 |
1 |
|
T1 |
10 |
|
T5 |
1 |
|
T27 |
2 |
| others[3] |
465 |
1 |
|
T1 |
16 |
|
T43 |
1 |
|
T19 |
1 |
| false |
146 |
1 |
|
T1 |
8 |
|
T347 |
1 |
|
T58 |
1 |
| true |
3272 |
1 |
|
T1 |
45 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10197 |
1 |
|
T1 |
7 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
480 |
1 |
|
T1 |
9 |
|
T23 |
1 |
|
T24 |
1 |
| others[2] |
478 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T16 |
1 |
| others[3] |
794 |
1 |
|
T1 |
14 |
|
T8 |
1 |
|
T23 |
1 |
| false |
235 |
1 |
|
T1 |
4 |
|
T27 |
1 |
|
T92 |
1 |
| true |
2245 |
1 |
|
T1 |
59 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10004 |
1 |
|
T1 |
6 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
253 |
1 |
|
T1 |
6 |
|
T20 |
1 |
|
T56 |
1 |
| others[2] |
256 |
1 |
|
T1 |
6 |
|
T44 |
1 |
|
T349 |
1 |
| others[3] |
450 |
1 |
|
T1 |
21 |
|
T5 |
1 |
|
T8 |
1 |
| false |
139 |
1 |
|
T1 |
6 |
|
T16 |
1 |
|
T60 |
1 |
| true |
3327 |
1 |
|
T1 |
56 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9993 |
1 |
|
T1 |
8 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
253 |
1 |
|
T1 |
9 |
|
T126 |
1 |
|
T351 |
1 |
| others[2] |
258 |
1 |
|
T1 |
9 |
|
T212 |
1 |
|
T25 |
1 |
| others[3] |
422 |
1 |
|
T1 |
16 |
|
T16 |
1 |
|
T27 |
2 |
| false |
136 |
1 |
|
T1 |
7 |
|
T25 |
1 |
|
T126 |
1 |
| true |
3367 |
1 |
|
T1 |
52 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10490 |
1 |
|
T1 |
17 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
854 |
1 |
|
T1 |
9 |
|
T23 |
3 |
|
T20 |
1 |
| others[2] |
779 |
1 |
|
T1 |
25 |
|
T23 |
3 |
|
T24 |
3 |
| others[3] |
1360 |
1 |
|
T1 |
39 |
|
T16 |
1 |
|
T7 |
1 |
| false |
413 |
1 |
|
T1 |
11 |
|
T23 |
1 |
|
T24 |
3 |
| true |
533 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10546 |
1 |
|
T1 |
23 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
818 |
1 |
|
T1 |
24 |
|
T23 |
5 |
|
T24 |
1 |
| others[2] |
786 |
1 |
|
T1 |
19 |
|
T43 |
1 |
|
T23 |
1 |
| others[3] |
1320 |
1 |
|
T1 |
28 |
|
T7 |
1 |
|
T23 |
3 |
| false |
410 |
1 |
|
T1 |
7 |
|
T24 |
2 |
|
T89 |
1 |
| true |
549 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2479 |
1 |
|
T1 |
7 |
|
T2 |
7 |
|
T17 |
20 |
| others[1] |
2470 |
1 |
|
T1 |
9 |
|
T2 |
9 |
|
T5 |
1 |
| others[2] |
2526 |
1 |
|
T1 |
9 |
|
T2 |
11 |
|
T16 |
1 |
| others[3] |
4047 |
1 |
|
T1 |
23 |
|
T2 |
13 |
|
T3 |
2 |
| false |
1329 |
1 |
|
T1 |
4 |
|
T2 |
4 |
|
T17 |
12 |
| true |
1578 |
1 |
|
T1 |
49 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9989 |
1 |
|
T1 |
9 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
312 |
1 |
|
T1 |
11 |
|
T212 |
1 |
|
T210 |
1 |
| others[2] |
269 |
1 |
|
T1 |
5 |
|
T19 |
1 |
|
T69 |
1 |
| others[3] |
475 |
1 |
|
T1 |
23 |
|
T8 |
1 |
|
T27 |
1 |
| false |
143 |
1 |
|
T1 |
6 |
|
T27 |
1 |
|
T106 |
2 |
| true |
3241 |
1 |
|
T1 |
47 |
|
T4 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |