Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10153 |
1 |
|
T1 |
6 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
473 |
1 |
|
T1 |
12 |
|
T24 |
2 |
|
T25 |
3 |
| others[2] |
465 |
1 |
|
T1 |
9 |
|
T23 |
1 |
|
T59 |
1 |
| others[3] |
804 |
1 |
|
T1 |
20 |
|
T16 |
1 |
|
T7 |
1 |
| false |
275 |
1 |
|
T1 |
2 |
|
T5 |
1 |
|
T8 |
1 |
| true |
2259 |
1 |
|
T1 |
52 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10019 |
1 |
|
T1 |
9 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
275 |
1 |
|
T1 |
8 |
|
T7 |
1 |
|
T27 |
1 |
| others[2] |
266 |
1 |
|
T1 |
4 |
|
T20 |
1 |
|
T69 |
1 |
| others[3] |
438 |
1 |
|
T1 |
23 |
|
T9 |
1 |
|
T43 |
1 |
| false |
127 |
1 |
|
T1 |
5 |
|
T25 |
2 |
|
T114 |
1 |
| true |
3304 |
1 |
|
T1 |
52 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9960 |
1 |
|
T1 |
9 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
298 |
1 |
|
T1 |
8 |
|
T27 |
1 |
|
T25 |
1 |
| others[2] |
257 |
1 |
|
T1 |
14 |
|
T114 |
1 |
|
T118 |
1 |
| others[3] |
409 |
1 |
|
T1 |
16 |
|
T69 |
1 |
|
T25 |
5 |
| false |
137 |
1 |
|
T1 |
3 |
|
T118 |
1 |
|
T348 |
3 |
| true |
3368 |
1 |
|
T1 |
51 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10543 |
1 |
|
T1 |
13 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
788 |
1 |
|
T1 |
15 |
|
T23 |
1 |
|
T44 |
1 |
| others[2] |
854 |
1 |
|
T1 |
25 |
|
T18 |
1 |
|
T23 |
5 |
| others[3] |
1302 |
1 |
|
T1 |
40 |
|
T23 |
2 |
|
T24 |
2 |
| false |
409 |
1 |
|
T1 |
8 |
|
T23 |
1 |
|
T20 |
1 |
| true |
533 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10516 |
1 |
|
T1 |
11 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
820 |
1 |
|
T1 |
32 |
|
T23 |
3 |
|
T24 |
4 |
| others[2] |
797 |
1 |
|
T1 |
20 |
|
T23 |
2 |
|
T24 |
4 |
| others[3] |
1357 |
1 |
|
T1 |
29 |
|
T7 |
1 |
|
T23 |
5 |
| false |
408 |
1 |
|
T1 |
9 |
|
T16 |
1 |
|
T52 |
1 |
| true |
531 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2490 |
1 |
|
T1 |
6 |
|
T2 |
13 |
|
T3 |
1 |
| others[1] |
2507 |
1 |
|
T1 |
13 |
|
T2 |
7 |
|
T17 |
22 |
| others[2] |
2447 |
1 |
|
T1 |
16 |
|
T2 |
11 |
|
T3 |
1 |
| others[3] |
4164 |
1 |
|
T1 |
10 |
|
T2 |
9 |
|
T17 |
42 |
| false |
1244 |
1 |
|
T1 |
10 |
|
T2 |
4 |
|
T17 |
8 |
| true |
1577 |
1 |
|
T1 |
46 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9988 |
1 |
|
T1 |
11 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
295 |
1 |
|
T1 |
9 |
|
T27 |
1 |
|
T92 |
1 |
| others[2] |
260 |
1 |
|
T1 |
11 |
|
T7 |
1 |
|
T20 |
1 |
| others[3] |
478 |
1 |
|
T1 |
18 |
|
T27 |
1 |
|
T59 |
1 |
| false |
165 |
1 |
|
T1 |
7 |
|
T25 |
1 |
|
T39 |
1 |
| true |
3243 |
1 |
|
T1 |
45 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10241 |
1 |
|
T1 |
10 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
506 |
1 |
|
T1 |
7 |
|
T19 |
1 |
|
T23 |
1 |
| others[2] |
477 |
1 |
|
T1 |
11 |
|
T5 |
1 |
|
T23 |
1 |
| others[3] |
786 |
1 |
|
T1 |
15 |
|
T8 |
1 |
|
T23 |
1 |
| false |
247 |
1 |
|
T1 |
5 |
|
T43 |
1 |
|
T23 |
1 |
| true |
2172 |
1 |
|
T1 |
53 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9997 |
1 |
|
T1 |
6 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
266 |
1 |
|
T1 |
14 |
|
T89 |
1 |
|
T349 |
1 |
| others[2] |
315 |
1 |
|
T1 |
12 |
|
T9 |
1 |
|
T25 |
2 |
| others[3] |
455 |
1 |
|
T1 |
22 |
|
T7 |
1 |
|
T27 |
1 |
| false |
129 |
1 |
|
T1 |
7 |
|
T43 |
1 |
|
T74 |
1 |
| true |
3267 |
1 |
|
T1 |
40 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9974 |
1 |
|
T1 |
6 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
278 |
1 |
|
T1 |
15 |
|
T27 |
1 |
|
T63 |
1 |
| others[2] |
243 |
1 |
|
T1 |
12 |
|
T59 |
1 |
|
T91 |
1 |
| others[3] |
459 |
1 |
|
T1 |
20 |
|
T5 |
1 |
|
T43 |
1 |
| false |
149 |
1 |
|
T1 |
2 |
|
T7 |
1 |
|
T27 |
1 |
| true |
3326 |
1 |
|
T1 |
46 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10547 |
1 |
|
T1 |
14 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
810 |
1 |
|
T1 |
20 |
|
T16 |
1 |
|
T23 |
2 |
| others[2] |
820 |
1 |
|
T1 |
30 |
|
T23 |
2 |
|
T44 |
1 |
| others[3] |
1331 |
1 |
|
T1 |
34 |
|
T6 |
1 |
|
T7 |
1 |
| false |
406 |
1 |
|
T1 |
3 |
|
T23 |
4 |
|
T349 |
1 |
| true |
515 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10548 |
1 |
|
T1 |
15 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
768 |
1 |
|
T1 |
21 |
|
T7 |
1 |
|
T23 |
3 |
| others[2] |
791 |
1 |
|
T1 |
18 |
|
T24 |
2 |
|
T25 |
2 |
| others[3] |
1333 |
1 |
|
T1 |
29 |
|
T23 |
6 |
|
T44 |
1 |
| false |
449 |
1 |
|
T1 |
18 |
|
T16 |
1 |
|
T25 |
2 |
| true |
540 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2485 |
1 |
|
T1 |
6 |
|
T2 |
11 |
|
T17 |
23 |
| others[1] |
2485 |
1 |
|
T1 |
9 |
|
T2 |
7 |
|
T17 |
11 |
| others[2] |
2424 |
1 |
|
T1 |
11 |
|
T2 |
11 |
|
T3 |
1 |
| others[3] |
4217 |
1 |
|
T1 |
20 |
|
T2 |
10 |
|
T3 |
1 |
| false |
1313 |
1 |
|
T1 |
4 |
|
T2 |
5 |
|
T16 |
1 |
| true |
1505 |
1 |
|
T1 |
51 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10007 |
1 |
|
T1 |
9 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
266 |
1 |
|
T1 |
3 |
|
T25 |
2 |
|
T106 |
2 |
| others[2] |
273 |
1 |
|
T1 |
9 |
|
T8 |
1 |
|
T27 |
2 |
| others[3] |
445 |
1 |
|
T1 |
13 |
|
T91 |
1 |
|
T56 |
1 |
| false |
160 |
1 |
|
T1 |
5 |
|
T210 |
1 |
|
T347 |
1 |
| true |
3278 |
1 |
|
T1 |
62 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10239 |
1 |
|
T1 |
8 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
460 |
1 |
|
T1 |
10 |
|
T18 |
1 |
|
T23 |
2 |
| others[2] |
476 |
1 |
|
T1 |
8 |
|
T9 |
1 |
|
T43 |
1 |
| others[3] |
797 |
1 |
|
T1 |
17 |
|
T7 |
1 |
|
T18 |
1 |
| false |
261 |
1 |
|
T1 |
3 |
|
T23 |
1 |
|
T25 |
1 |
| true |
2196 |
1 |
|
T1 |
55 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9996 |
1 |
|
T1 |
8 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
254 |
1 |
|
T1 |
9 |
|
T43 |
1 |
|
T59 |
1 |
| others[2] |
276 |
1 |
|
T1 |
13 |
|
T5 |
1 |
|
T7 |
1 |
| others[3] |
452 |
1 |
|
T1 |
14 |
|
T8 |
1 |
|
T27 |
1 |
| false |
131 |
1 |
|
T1 |
8 |
|
T210 |
1 |
|
T76 |
1 |
| true |
3320 |
1 |
|
T1 |
49 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9967 |
1 |
|
T1 |
7 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
290 |
1 |
|
T1 |
12 |
|
T60 |
1 |
|
T349 |
1 |
| others[2] |
258 |
1 |
|
T1 |
10 |
|
T27 |
1 |
|
T59 |
1 |
| others[3] |
447 |
1 |
|
T1 |
17 |
|
T16 |
1 |
|
T89 |
1 |
| false |
128 |
1 |
|
T1 |
4 |
|
T43 |
1 |
|
T27 |
1 |
| true |
3339 |
1 |
|
T1 |
51 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10551 |
1 |
|
T1 |
25 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
844 |
1 |
|
T1 |
25 |
|
T16 |
1 |
|
T24 |
3 |
| others[2] |
795 |
1 |
|
T1 |
20 |
|
T23 |
6 |
|
T89 |
1 |
| others[3] |
1351 |
1 |
|
T1 |
24 |
|
T7 |
1 |
|
T18 |
1 |
| false |
357 |
1 |
|
T1 |
7 |
|
T23 |
1 |
|
T44 |
1 |
| true |
531 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10522 |
1 |
|
T1 |
25 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
834 |
1 |
|
T1 |
19 |
|
T23 |
2 |
|
T24 |
4 |
| others[2] |
760 |
1 |
|
T1 |
17 |
|
T16 |
1 |
|
T19 |
1 |
| others[3] |
1350 |
1 |
|
T1 |
33 |
|
T23 |
6 |
|
T24 |
3 |
| false |
421 |
1 |
|
T1 |
7 |
|
T23 |
1 |
|
T24 |
2 |
| true |
542 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2474 |
1 |
|
T1 |
5 |
|
T2 |
8 |
|
T3 |
1 |
| others[1] |
2566 |
1 |
|
T1 |
17 |
|
T2 |
11 |
|
T17 |
18 |
| others[2] |
2478 |
1 |
|
T1 |
11 |
|
T2 |
8 |
|
T17 |
19 |
| others[3] |
4092 |
1 |
|
T1 |
16 |
|
T2 |
12 |
|
T3 |
1 |
| false |
1253 |
1 |
|
T1 |
5 |
|
T2 |
5 |
|
T16 |
1 |
| true |
1566 |
1 |
|
T1 |
47 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9998 |
1 |
|
T1 |
10 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
285 |
1 |
|
T1 |
8 |
|
T27 |
1 |
|
T349 |
1 |
| others[2] |
296 |
1 |
|
T1 |
7 |
|
T9 |
1 |
|
T27 |
1 |
| others[3] |
450 |
1 |
|
T1 |
17 |
|
T8 |
1 |
|
T43 |
1 |
| false |
159 |
1 |
|
T1 |
9 |
|
T16 |
1 |
|
T25 |
1 |
| true |
3241 |
1 |
|
T1 |
50 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10213 |
1 |
|
T1 |
10 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
478 |
1 |
|
T1 |
11 |
|
T23 |
5 |
|
T27 |
1 |
| others[2] |
491 |
1 |
|
T1 |
10 |
|
T16 |
1 |
|
T5 |
1 |
| others[3] |
802 |
1 |
|
T1 |
12 |
|
T18 |
1 |
|
T23 |
1 |
| false |
245 |
1 |
|
T1 |
3 |
|
T27 |
1 |
|
T60 |
1 |
| true |
2200 |
1 |
|
T1 |
55 |
|
T4 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10009 |
1 |
|
T1 |
14 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
263 |
1 |
|
T1 |
14 |
|
T114 |
2 |
|
T384 |
1 |
| others[2] |
282 |
1 |
|
T1 |
10 |
|
T8 |
1 |
|
T9 |
1 |
| others[3] |
464 |
1 |
|
T1 |
20 |
|
T43 |
1 |
|
T27 |
2 |
| false |
134 |
1 |
|
T1 |
4 |
|
T58 |
1 |
|
T114 |
2 |
| true |
3277 |
1 |
|
T1 |
39 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9997 |
1 |
|
T1 |
8 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
256 |
1 |
|
T1 |
12 |
|
T27 |
1 |
|
T89 |
1 |
| others[2] |
253 |
1 |
|
T1 |
6 |
|
T91 |
1 |
|
T74 |
1 |
| others[3] |
430 |
1 |
|
T1 |
20 |
|
T5 |
1 |
|
T43 |
1 |
| false |
133 |
1 |
|
T1 |
2 |
|
T27 |
1 |
|
T352 |
1 |
| true |
3360 |
1 |
|
T1 |
53 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10568 |
1 |
|
T1 |
25 |
|
T2 |
44 |
|
T3 |
2 |
| others[1] |
751 |
1 |
|
T1 |
21 |
|
T23 |
2 |
|
T24 |
3 |
| others[2] |
780 |
1 |
|
T1 |
17 |
|
T7 |
1 |
|
T18 |
1 |
| others[3] |
1406 |
1 |
|
T1 |
25 |
|
T23 |
3 |
|
T24 |
3 |
| false |
407 |
1 |
|
T1 |
13 |
|
T16 |
1 |
|
T23 |
3 |
| true |
517 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |