Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	223832	1		T1	100		T2	259		T3	1
auto[FlashEraseBank]	237084	1		T1	1011		T5	1		T7	395

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	255852	1		T1	569		T2	137		T3	1
auto[FlashOpProgram]	184731	1		T1	488		T2	61		T4	1
auto[FlashOpErase]	16333	1		T1	54		T2	61		T4	1
auto[FlashOpInvalid]	4000	1		T17	200		T123	200		T281	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	255852	1		T1	569		T2	137		T3	1
op[FlashOpProgram]	184731	1		T1	488		T2	61		T4	1
op[FlashOpErase]	16333	1		T1	54		T2	61		T4	1
read_erase_read	654	1		T1	2		T24	1		T25	2
read_prog_read	1217	1		T1	2		T27	1		T90	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	321794	1		T1	95		T3	1		T4	1
auto[FlashPartInfo]	135406	1		T1	1016		T2	259		T4	1
auto[FlashPartInfo1]	882	1		T25	8		T56	4		T58	1
auto[FlashPartInfo2]	2834	1		T8	30		T9	5		T19	29

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	192872	1		T1	23		T3	1		T17	200
auto[FlashPartData]	auto[FlashOpProgram]	121066	1		T1	39		T5	1		T17	100
auto[FlashPartData]	auto[FlashOpErase]	3938	1		T1	33		T4	1		T17	100
auto[FlashPartData]	auto[FlashOpInvalid]	3918	1		T17	200		T123	198		T281	198
auto[FlashPartInfo]	auto[FlashOpRead]	60533	1		T1	546		T2	137		T18	104
auto[FlashPartInfo]	auto[FlashOpProgram]	62430	1		T1	449		T2	61		T4	1
auto[FlashPartInfo]	auto[FlashOpErase]	12375	1		T1	21		T2	61		T26	13
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T281	2		T387	8		T388	2
auto[FlashPartInfo1]	auto[FlashOpRead]	743	1		T25	8		T56	4		T58	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	131	1		T55	32		T22	1		T120	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T122	1		T110	1		T389	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T122	2		T390	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1704	1		T8	30		T9	5		T19	29
auto[FlashPartInfo2]	auto[FlashOpProgram]	1104	1		T59	39		T60	11		T63	1
auto[FlashPartInfo2]	auto[FlashOpErase]	16	1		T25	2		T114	1		T123	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T123	2		T388	2		T391	2