Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31354	1		T1	32		T2	120		T17	400
auto[1]	46	1		T18	2		T78	1		T165	3
auto[2]	143	1		T196	64		T116	2		T117	3
auto[3]	275	1		T20	2		T90	2		T39	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8021	1		T1	8		T2	30		T17	100
evic_idx[1]	7950	1		T1	8		T2	30		T17	100
evic_idx[2]	7939	1		T1	8		T2	30		T17	100
evic_idx[3]	7908	1		T1	8		T2	30		T17	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30812	1		T2	120		T17	400		T24	3
evic_op[2]	403	1		T18	2		T20	2		T24	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7636	1		T2	30		T17	100		T24	1
evic_idx[0]	evic_op[1]	auto[1]	16	1		T314	16		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	33	1		T196	33		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	83	1		T315	1		T316	39		T317	20
evic_idx[0]	evic_op[2]	auto[0]	66	1		T56	1		T106	10		T127	4
evic_idx[0]	evic_op[2]	auto[1]	2	1		T165	1		T318	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	14	1		T319	2		T320	9		T321	3
evic_idx[0]	evic_op[2]	auto[3]	20	1		T20	1		T90	1		T117	1
evic_idx[1]	evic_op[1]	auto[0]	7626	1		T2	30		T17	100		T24	1
evic_idx[1]	evic_op[1]	auto[1]	5	1		T314	5		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	15	1		T196	15		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	50	1		T322	1		T316	15		T317	9
evic_idx[1]	evic_op[2]	auto[0]	66	1		T106	10		T127	4		T220	4
evic_idx[1]	evic_op[2]	auto[2]	17	1		T117	2		T319	1		T320	8
evic_idx[1]	evic_op[2]	auto[3]	20	1		T90	1		T119	1		T124	1
evic_idx[2]	evic_op[1]	auto[0]	7623	1		T2	30		T17	100		T168	151
evic_idx[2]	evic_op[1]	auto[1]	7	1		T314	7		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	10	1		T196	10		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	40	1		T316	11		T317	13		T323	16
evic_idx[2]	evic_op[2]	auto[0]	66	1		T24	1		T106	10		T80	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T18	1		T78	1		T165	1
evic_idx[2]	evic_op[2]	auto[2]	20	1		T117	1		T319	4		T324	1
evic_idx[2]	evic_op[2]	auto[3]	17	1		T39	1		T77	1		T115	1
evic_idx[3]	evic_op[1]	auto[0]	7623	1		T2	30		T17	100		T24	1
evic_idx[3]	evic_op[1]	auto[1]	7	1		T314	7		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	6	1		T196	6		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	32	1		T315	4		T322	1		T316	7
evic_idx[3]	evic_op[2]	auto[0]	61	1		T106	10		T127	4		T220	4
evic_idx[3]	evic_op[2]	auto[1]	4	1		T18	1		T165	1		T325	1
evic_idx[3]	evic_op[2]	auto[2]	12	1		T116	2		T326	1		T320	7
evic_idx[3]	evic_op[2]	auto[3]	13	1		T20	1		T327	1		T328	1