Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	63622	1		T59	4681		T70	3159		T71	4723
prog_lvl[2]	2535	1		T70	1		T392	1		T393	903
prog_lvl[3]	2	1		T393	1		T394	1		-	-

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	3515	1		T19	11		T34	925		T217	110
rd_lvl[2]	19866	1		T8	3		T19	341		T34	402
rd_lvl[3]	17813	1		T8	5		T19	20		T44	1345
rd_lvl[4]	13864	1		T8	11		T19	18		T218	1249
rd_lvl[5]	10363	1		T8	403		T19	6		T34	115
rd_lvl[6]	15510	1		T19	301		T212	988		T217	7
rd_lvl[7]	11826	1		T19	1116		T212	582		T76	497
rd_lvl[8]	10269	1		T19	650		T52	1289		T218	3
rd_lvl[9]	4162	1		T52	333		T76	192		T395	562
rd_lvl[10]	8400	1		T7	486		T396	533		T395	342
rd_lvl[11]	6569	1		T7	305		T8	596		T76	2
rd_lvl[12]	8103	1		T8	465		T76	10		T202	858
rd_lvl[13]	5155	1		T75	543		T395	11		T275	55
rd_lvl[14]	5287	1		T75	465		T397	489		T398	423
rd_lvl[15]	3494	1		T74	609		T202	13		T399	18