Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	336690	1		T1	2		T2	1		T3	2
all_pins[1]	336690	1		T1	2		T2	1		T3	2
all_pins[2]	336690	1		T1	2		T2	1		T3	2
all_pins[3]	336690	1		T1	2		T2	1		T3	2
all_pins[4]	336690	1		T1	2		T2	1		T3	2
all_pins[5]	336690	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1635209	1		T1	12		T2	6		T3	12
values[0x1]	384931	1		T7	1582		T8	2546		T19	3594
transitions[0x0=>0x1]	360053	1		T7	1582		T8	2143		T19	3254
transitions[0x1=>0x0]	360064	1		T7	1582		T8	2143		T19	3254

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274677	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	62013	1		T59	2394		T69	4732		T70	2496
all_pins[0]	transitions[0x0=>0x1]	62000	1		T59	2394		T69	4732		T70	2496
all_pins[0]	transitions[0x1=>0x0]	70821	1		T59	4681		T70	4213		T71	4723
all_pins[1]	values[0x0]	265856	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	70834	1		T59	4681		T70	4213		T71	4723
all_pins[1]	transitions[0x0=>0x1]	70821	1		T59	4681		T70	4213		T71	4723
all_pins[1]	transitions[0x1=>0x0]	6814	1		T74	711		T75	449		T76	10
all_pins[2]	values[0x0]	329863	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	6827	1		T74	711		T75	449		T76	10
all_pins[2]	transitions[0x0=>0x1]	5047	1		T74	355		T75	449		T76	10
all_pins[2]	transitions[0x1=>0x0]	145657	1		T7	791		T8	1483		T19	2463
all_pins[3]	values[0x0]	189253	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	147437	1		T7	791		T8	1483		T19	2463
all_pins[3]	transitions[0x0=>0x1]	124397	1		T7	791		T8	1080		T19	2123
all_pins[3]	transitions[0x1=>0x0]	74720	1		T7	791		T8	660		T19	791
all_pins[4]	values[0x0]	238930	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	97760	1		T7	791		T8	1063		T19	1131
all_pins[4]	transitions[0x0=>0x1]	97750	1		T7	791		T8	1063		T19	1131
all_pins[4]	transitions[0x1=>0x0]	50	1		T254	2		T255	2		T256	2
all_pins[5]	values[0x0]	336630	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	60	1		T254	2		T255	2		T256	2
all_pins[5]	transitions[0x0=>0x1]	38	1		T254	2		T255	1		T256	1
all_pins[5]	transitions[0x1=>0x0]	62002	1		T59	2394		T69	4732		T70	2496