Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T254	4		T255	4		T256	7
all_values[1]	272	1		T254	4		T255	4		T256	7
all_values[2]	272	1		T254	4		T255	4		T256	7
all_values[3]	272	1		T254	4		T255	4		T256	7
all_values[4]	272	1		T254	4		T255	4		T256	7
all_values[5]	272	1		T254	4		T255	4		T256	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	889	1		T254	10		T255	12		T256	26
auto[1]	743	1		T254	14		T255	12		T256	16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	631	1		T254	8		T255	9		T256	11
auto[1]	1001	1		T254	16		T255	15		T256	31

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	970	1		T254	13		T255	15		T256	23
auto[1]	662	1		T254	11		T255	9		T256	19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	62	1		T256	4		T330	3		T331	1
all_values[0]	auto[0]	auto[0]	auto[1]	34	1		T329	1		T332	2		T331	1
all_values[0]	auto[0]	auto[1]	auto[0]	41	1		T254	3		T255	2		T256	1
all_values[0]	auto[0]	auto[1]	auto[1]	33	1		T255	1		T332	1		T331	1
all_values[0]	auto[1]	auto[0]	auto[1]	60	1		T256	1		T329	1		T332	1
all_values[0]	auto[1]	auto[1]	auto[1]	42	1		T254	1		T255	1		T256	1
all_values[1]	auto[0]	auto[0]	auto[0]	55	1		T254	1		T256	1		T330	2
all_values[1]	auto[0]	auto[0]	auto[1]	29	1		T255	1		T332	1		T333	2
all_values[1]	auto[0]	auto[1]	auto[0]	57	1		T254	1		T256	2		T329	2
all_values[1]	auto[0]	auto[1]	auto[1]	21	1		T254	1		T256	1		T330	1
all_values[1]	auto[1]	auto[0]	auto[1]	68	1		T255	3		T256	1		T329	4
all_values[1]	auto[1]	auto[1]	auto[1]	42	1		T254	1		T256	2		T329	1
all_values[2]	auto[0]	auto[0]	auto[0]	48	1		T254	1		T255	1		T331	1
all_values[2]	auto[0]	auto[0]	auto[1]	24	1		T255	1		T256	1		T330	1
all_values[2]	auto[0]	auto[1]	auto[0]	61	1		T256	1		T329	1		T334	2
all_values[2]	auto[0]	auto[1]	auto[1]	27	1		T255	1		T256	2		T329	3
all_values[2]	auto[1]	auto[0]	auto[1]	58	1		T254	2		T256	2		T329	1
all_values[2]	auto[1]	auto[1]	auto[1]	54	1		T254	1		T255	1		T256	1
all_values[3]	auto[0]	auto[0]	auto[0]	50	1		T255	1		T329	1		T330	1
all_values[3]	auto[0]	auto[0]	auto[1]	24	1		T256	2		T332	1		T331	1
all_values[3]	auto[0]	auto[1]	auto[0]	55	1		T254	1		T255	2		T329	2
all_values[3]	auto[0]	auto[1]	auto[1]	24	1		T254	1		T256	2		T332	1
all_values[3]	auto[1]	auto[0]	auto[1]	66	1		T255	1		T256	2		T329	1
all_values[3]	auto[1]	auto[1]	auto[1]	53	1		T254	2		T256	1		T329	3
all_values[4]	auto[0]	auto[0]	auto[0]	59	1		T254	1		T255	1		T256	1
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T254	2		T255	1		T256	2
all_values[4]	auto[0]	auto[1]	auto[0]	46	1		T255	1		T329	2		T333	1
all_values[4]	auto[0]	auto[1]	auto[1]	33	1		T330	1		T331	1		T334	2
all_values[4]	auto[1]	auto[0]	auto[1]	66	1		T254	1		T255	1		T256	3
all_values[4]	auto[1]	auto[1]	auto[1]	40	1		T256	1		T329	1		T330	1
all_values[5]	auto[0]	auto[0]	auto[0]	56	1		T256	1		T329	2		T330	2
all_values[5]	auto[0]	auto[0]	auto[1]	38	1		T256	2		T333	2		T335	2
all_values[5]	auto[0]	auto[1]	auto[0]	41	1		T255	1		T332	2		T331	1
all_values[5]	auto[0]	auto[1]	auto[1]	24	1		T254	1		T255	1		T329	3
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T254	2		T255	1		T256	3
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T254	1		T255	1		T256	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal