| T1080 |
/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.568306594 |
|
|
Feb 28 04:52:25 PM PST 24 |
Feb 28 04:52:39 PM PST 24 |
47666500 ps |
| T1081 |
/workspace/coverage/default/48.flash_ctrl_alert_test.2061939761 |
|
|
Feb 28 04:58:42 PM PST 24 |
Feb 28 04:58:55 PM PST 24 |
297032100 ps |
| T1082 |
/workspace/coverage/default/6.flash_ctrl_intr_rd.2620235944 |
|
|
Feb 28 04:53:39 PM PST 24 |
Feb 28 04:56:19 PM PST 24 |
2323360500 ps |
| T1083 |
/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3343777837 |
|
|
Feb 28 04:55:07 PM PST 24 |
Feb 28 04:56:07 PM PST 24 |
10030981600 ps |
| T1084 |
/workspace/coverage/default/61.flash_ctrl_otp_reset.2131049043 |
|
|
Feb 28 04:58:57 PM PST 24 |
Feb 28 05:00:50 PM PST 24 |
44750200 ps |
| T1085 |
/workspace/coverage/default/47.flash_ctrl_connect.3209734741 |
|
|
Feb 28 04:58:43 PM PST 24 |
Feb 28 04:58:59 PM PST 24 |
13728800 ps |
| T1086 |
/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.42950836 |
|
|
Feb 28 04:52:54 PM PST 24 |
Feb 28 04:55:39 PM PST 24 |
36842818000 ps |
| T1087 |
/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1464087034 |
|
|
Feb 28 04:58:03 PM PST 24 |
Feb 28 05:00:52 PM PST 24 |
2071824700 ps |
| T1088 |
/workspace/coverage/default/9.flash_ctrl_rw_serr.1403358908 |
|
|
Feb 28 04:54:51 PM PST 24 |
Feb 28 05:04:47 PM PST 24 |
14190613800 ps |
| T1089 |
/workspace/coverage/default/5.flash_ctrl_rw_serr.320547951 |
|
|
Feb 28 04:53:23 PM PST 24 |
Feb 28 05:02:15 PM PST 24 |
12154983400 ps |
| T390 |
/workspace/coverage/default/3.flash_ctrl_invalid_op.543370362 |
|
|
Feb 28 04:52:37 PM PST 24 |
Feb 28 04:53:48 PM PST 24 |
2172038700 ps |
| T1090 |
/workspace/coverage/default/5.flash_ctrl_error_prog_win.1412740876 |
|
|
Feb 28 04:53:16 PM PST 24 |
Feb 28 05:09:00 PM PST 24 |
1217561300 ps |
| T1091 |
/workspace/coverage/default/23.flash_ctrl_otp_reset.778357949 |
|
|
Feb 28 04:56:49 PM PST 24 |
Feb 28 04:59:06 PM PST 24 |
79749400 ps |
| T1092 |
/workspace/coverage/default/32.flash_ctrl_intr_rd.1784857916 |
|
|
Feb 28 04:57:43 PM PST 24 |
Feb 28 05:00:17 PM PST 24 |
1159253300 ps |
| T321 |
/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2341907560 |
|
|
Feb 28 04:55:00 PM PST 24 |
Feb 28 04:55:38 PM PST 24 |
114971300 ps |
| T1093 |
/workspace/coverage/default/10.flash_ctrl_rw_evict.4065679683 |
|
|
Feb 28 04:54:51 PM PST 24 |
Feb 28 04:55:25 PM PST 24 |
163670800 ps |
| T1094 |
/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2406551528 |
|
|
Feb 28 04:55:53 PM PST 24 |
Feb 28 04:56:07 PM PST 24 |
47608300 ps |
| T1095 |
/workspace/coverage/default/4.flash_ctrl_error_mp.3241162014 |
|
|
Feb 28 04:52:58 PM PST 24 |
Feb 28 05:29:13 PM PST 24 |
31131294200 ps |
| T1096 |
/workspace/coverage/default/6.flash_ctrl_rw_serr.2813228111 |
|
|
Feb 28 04:53:37 PM PST 24 |
Feb 28 05:02:19 PM PST 24 |
10115661200 ps |
| T1097 |
/workspace/coverage/default/11.flash_ctrl_phy_arb.1610068894 |
|
|
Feb 28 04:54:59 PM PST 24 |
Feb 28 05:03:31 PM PST 24 |
758154100 ps |
| T216 |
/workspace/coverage/default/12.flash_ctrl_disable.1421048974 |
|
|
Feb 28 04:55:10 PM PST 24 |
Feb 28 04:55:30 PM PST 24 |
26503600 ps |
| T41 |
/workspace/coverage/default/5.flash_ctrl_fetch_code.1428356922 |
|
|
Feb 28 04:53:16 PM PST 24 |
Feb 28 04:53:44 PM PST 24 |
2030198200 ps |
| T378 |
/workspace/coverage/default/4.flash_ctrl_sec_info_access.2195105680 |
|
|
Feb 28 04:53:15 PM PST 24 |
Feb 28 04:54:22 PM PST 24 |
2599243500 ps |
| T1098 |
/workspace/coverage/default/3.flash_ctrl_smoke.2656500185 |
|
|
Feb 28 04:52:27 PM PST 24 |
Feb 28 04:54:30 PM PST 24 |
70121000 ps |
| T1099 |
/workspace/coverage/default/29.flash_ctrl_alert_test.949873405 |
|
|
Feb 28 04:57:30 PM PST 24 |
Feb 28 04:57:44 PM PST 24 |
104079900 ps |
| T383 |
/workspace/coverage/default/7.flash_ctrl_sec_info_access.3172308895 |
|
|
Feb 28 04:54:01 PM PST 24 |
Feb 28 04:55:12 PM PST 24 |
1906180200 ps |
| T1100 |
/workspace/coverage/default/63.flash_ctrl_otp_reset.3635157206 |
|
|
Feb 28 04:58:56 PM PST 24 |
Feb 28 05:00:49 PM PST 24 |
134797500 ps |
| T344 |
/workspace/coverage/default/27.flash_ctrl_disable.1981084022 |
|
|
Feb 28 04:57:16 PM PST 24 |
Feb 28 04:57:40 PM PST 24 |
15074700 ps |
| T1101 |
/workspace/coverage/default/0.flash_ctrl_fs_sup.4170704117 |
|
|
Feb 28 04:52:04 PM PST 24 |
Feb 28 04:52:42 PM PST 24 |
586611500 ps |
| T1102 |
/workspace/coverage/default/6.flash_ctrl_disable.2503350899 |
|
|
Feb 28 04:53:41 PM PST 24 |
Feb 28 04:54:03 PM PST 24 |
11407100 ps |
| T1103 |
/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.406087782 |
|
|
Feb 28 04:54:49 PM PST 24 |
Feb 28 04:55:20 PM PST 24 |
45212500 ps |
| T1104 |
/workspace/coverage/default/22.flash_ctrl_rw_evict.3600913610 |
|
|
Feb 28 04:56:46 PM PST 24 |
Feb 28 04:57:18 PM PST 24 |
50327500 ps |
| T42 |
/workspace/coverage/default/0.flash_ctrl_fetch_code.2756793977 |
|
|
Feb 28 04:51:55 PM PST 24 |
Feb 28 04:52:22 PM PST 24 |
1123966700 ps |
| T1105 |
/workspace/coverage/default/15.flash_ctrl_rw.3870076270 |
|
|
Feb 28 04:55:42 PM PST 24 |
Feb 28 05:04:42 PM PST 24 |
6887119700 ps |
| T1106 |
/workspace/coverage/default/12.flash_ctrl_phy_arb.3484435826 |
|
|
Feb 28 04:55:00 PM PST 24 |
Feb 28 05:05:10 PM PST 24 |
4085729400 ps |
| T1107 |
/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.1977167128 |
|
|
Feb 28 04:54:56 PM PST 24 |
Feb 28 05:09:20 PM PST 24 |
160195381100 ps |
| T1108 |
/workspace/coverage/default/4.flash_ctrl_stress_all.43343348 |
|
|
Feb 28 04:53:15 PM PST 24 |
Feb 28 05:14:14 PM PST 24 |
859946900 ps |
| T148 |
/workspace/coverage/default/0.flash_ctrl_rma_err.312646963 |
|
|
Feb 28 04:52:07 PM PST 24 |
Feb 28 05:06:45 PM PST 24 |
106750106000 ps |
| T1109 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.1927017076 |
|
|
Feb 28 04:51:58 PM PST 24 |
Feb 28 04:52:19 PM PST 24 |
31649400 ps |
| T1110 |
/workspace/coverage/default/22.flash_ctrl_connect.3843096523 |
|
|
Feb 28 04:56:49 PM PST 24 |
Feb 28 04:57:06 PM PST 24 |
41298600 ps |
| T1111 |
/workspace/coverage/default/11.flash_ctrl_wo.1728452593 |
|
|
Feb 28 04:54:58 PM PST 24 |
Feb 28 04:57:40 PM PST 24 |
1961781200 ps |
| T1112 |
/workspace/coverage/default/3.flash_ctrl_erase_suspend.1586673807 |
|
|
Feb 28 04:52:30 PM PST 24 |
Feb 28 04:57:26 PM PST 24 |
1008336300 ps |
| T1113 |
/workspace/coverage/default/16.flash_ctrl_phy_arb.1391112477 |
|
|
Feb 28 04:55:45 PM PST 24 |
Feb 28 05:03:33 PM PST 24 |
9027135000 ps |
| T1114 |
/workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.2709628100 |
|
|
Feb 28 04:56:52 PM PST 24 |
Feb 28 04:57:23 PM PST 24 |
88420600 ps |
| T1115 |
/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2107034494 |
|
|
Feb 28 04:54:51 PM PST 24 |
Feb 28 04:55:05 PM PST 24 |
17144200 ps |
| T1116 |
/workspace/coverage/default/6.flash_ctrl_alert_test.1746107944 |
|
|
Feb 28 04:53:46 PM PST 24 |
Feb 28 04:54:00 PM PST 24 |
84922700 ps |
| T1117 |
/workspace/coverage/default/8.flash_ctrl_otp_reset.3164886504 |
|
|
Feb 28 04:54:07 PM PST 24 |
Feb 28 04:56:27 PM PST 24 |
70498200 ps |
| T1118 |
/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3148829655 |
|
|
Feb 28 04:54:03 PM PST 24 |
Feb 28 04:55:15 PM PST 24 |
10024084400 ps |
| T1119 |
/workspace/coverage/default/4.flash_ctrl_ro_serr.2107881278 |
|
|
Feb 28 04:53:17 PM PST 24 |
Feb 28 04:55:44 PM PST 24 |
2848805600 ps |
| T1120 |
/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.76568896 |
|
|
Feb 28 04:52:54 PM PST 24 |
Feb 28 04:53:41 PM PST 24 |
774667900 ps |
| T1121 |
/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.50317920 |
|
|
Feb 28 04:55:36 PM PST 24 |
Feb 28 04:55:50 PM PST 24 |
26235400 ps |
| T1122 |
/workspace/coverage/default/3.flash_ctrl_re_evict.1690114445 |
|
|
Feb 28 04:52:46 PM PST 24 |
Feb 28 04:53:20 PM PST 24 |
388471500 ps |
| T1123 |
/workspace/coverage/default/28.flash_ctrl_otp_reset.1236835908 |
|
|
Feb 28 04:57:20 PM PST 24 |
Feb 28 04:59:35 PM PST 24 |
75900200 ps |
| T1124 |
/workspace/coverage/default/31.flash_ctrl_rw_evict.1147630242 |
|
|
Feb 28 04:57:40 PM PST 24 |
Feb 28 04:58:10 PM PST 24 |
157645500 ps |
| T1125 |
/workspace/coverage/default/3.flash_ctrl_ro_derr.1558701204 |
|
|
Feb 28 04:52:40 PM PST 24 |
Feb 28 04:54:57 PM PST 24 |
2360740200 ps |
| T1126 |
/workspace/coverage/default/0.flash_ctrl_disable.3105230781 |
|
|
Feb 28 04:52:00 PM PST 24 |
Feb 28 04:52:22 PM PST 24 |
11208900 ps |
| T1127 |
/workspace/coverage/default/69.flash_ctrl_connect.1263598394 |
|
|
Feb 28 04:59:05 PM PST 24 |
Feb 28 04:59:21 PM PST 24 |
29921500 ps |
| T1128 |
/workspace/coverage/default/4.flash_ctrl_connect.3784238376 |
|
|
Feb 28 04:53:15 PM PST 24 |
Feb 28 04:53:33 PM PST 24 |
70682800 ps |
| T1129 |
/workspace/coverage/default/8.flash_ctrl_intr_wr.1229364201 |
|
|
Feb 28 04:54:15 PM PST 24 |
Feb 28 04:55:55 PM PST 24 |
6918293200 ps |
| T1130 |
/workspace/coverage/default/9.flash_ctrl_ro.3603545183 |
|
|
Feb 28 04:54:50 PM PST 24 |
Feb 28 04:56:30 PM PST 24 |
1894583500 ps |
| T1131 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep.390303244 |
|
|
Feb 28 04:52:02 PM PST 24 |
Feb 28 04:52:17 PM PST 24 |
254900900 ps |
| T1132 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1531563040 |
|
|
Feb 28 04:18:40 PM PST 24 |
Feb 28 04:18:56 PM PST 24 |
44842900 ps |
| T49 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3154203983 |
|
|
Feb 28 04:19:09 PM PST 24 |
Feb 28 04:19:23 PM PST 24 |
150152600 ps |
| T254 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1785878921 |
|
|
Feb 28 04:19:12 PM PST 24 |
Feb 28 04:19:26 PM PST 24 |
14236500 ps |
| T255 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1800482333 |
|
|
Feb 28 04:19:00 PM PST 24 |
Feb 28 04:19:14 PM PST 24 |
70400400 ps |
| T256 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3223921122 |
|
|
Feb 28 04:19:23 PM PST 24 |
Feb 28 04:19:37 PM PST 24 |
53400200 ps |
| T177 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1938006153 |
|
|
Feb 28 04:18:48 PM PST 24 |
Feb 28 04:19:07 PM PST 24 |
51008500 ps |
| T50 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1897792067 |
|
|
Feb 28 04:19:25 PM PST 24 |
Feb 28 04:19:42 PM PST 24 |
33490800 ps |
| T51 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1653343411 |
|
|
Feb 28 04:18:52 PM PST 24 |
Feb 28 04:19:08 PM PST 24 |
167618700 ps |
| T329 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1764269232 |
|
|
Feb 28 04:18:55 PM PST 24 |
Feb 28 04:19:09 PM PST 24 |
46696900 ps |
| T178 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2041080553 |
|
|
Feb 28 04:19:00 PM PST 24 |
Feb 28 04:19:19 PM PST 24 |
43482300 ps |
| T330 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1331992876 |
|
|
Feb 28 04:18:52 PM PST 24 |
Feb 28 04:19:06 PM PST 24 |
25205100 ps |
| T332 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2314507192 |
|
|
Feb 28 04:18:43 PM PST 24 |
Feb 28 04:18:57 PM PST 24 |
30851300 ps |
| T244 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.130271385 |
|
|
Feb 28 04:18:50 PM PST 24 |
Feb 28 04:19:07 PM PST 24 |
180829500 ps |
| T1133 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1729461187 |
|
|
Feb 28 04:18:57 PM PST 24 |
Feb 28 04:19:13 PM PST 24 |
26400700 ps |
| T331 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2813589030 |
|
|
Feb 28 04:18:34 PM PST 24 |
Feb 28 04:18:48 PM PST 24 |
98918700 ps |
| T334 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.204786383 |
|
|
Feb 28 04:19:22 PM PST 24 |
Feb 28 04:19:36 PM PST 24 |
28561900 ps |
| T206 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.612041090 |
|
|
Feb 28 04:19:02 PM PST 24 |
Feb 28 04:19:21 PM PST 24 |
146856700 ps |
| T245 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4189985051 |
|
|
Feb 28 04:18:57 PM PST 24 |
Feb 28 04:19:15 PM PST 24 |
1092429600 ps |
| T248 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1742786600 |
|
|
Feb 28 04:18:40 PM PST 24 |
Feb 28 04:18:59 PM PST 24 |
166882200 ps |
| T333 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2287421140 |
|
|
Feb 28 04:19:16 PM PST 24 |
Feb 28 04:19:29 PM PST 24 |
112398000 ps |
| T249 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4265009429 |
|
|
Feb 28 04:18:48 PM PST 24 |
Feb 28 04:19:05 PM PST 24 |
391333800 ps |
| T1134 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3937136497 |
|
|
Feb 28 04:19:30 PM PST 24 |
Feb 28 04:19:50 PM PST 24 |
13629300 ps |
| T1135 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3186397757 |
|
|
Feb 28 04:19:37 PM PST 24 |
Feb 28 04:19:50 PM PST 24 |
52289800 ps |
| T229 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3336801916 |
|
|
Feb 28 04:18:56 PM PST 24 |
Feb 28 04:19:10 PM PST 24 |
46600500 ps |
| T207 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1143553446 |
|
|
Feb 28 04:18:46 PM PST 24 |
Feb 28 04:33:39 PM PST 24 |
1419728800 ps |
| T1136 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2254657621 |
|
|
Feb 28 04:18:33 PM PST 24 |
Feb 28 04:18:49 PM PST 24 |
36557800 ps |
| T335 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3871133169 |
|
|
Feb 28 04:18:19 PM PST 24 |
Feb 28 04:18:33 PM PST 24 |
89320100 ps |
| T1137 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.462994386 |
|
|
Feb 28 04:18:43 PM PST 24 |
Feb 28 04:18:58 PM PST 24 |
37159100 ps |
| T235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.244671450 |
|
|
Feb 28 04:18:23 PM PST 24 |
Feb 28 04:18:38 PM PST 24 |
31621000 ps |
| T230 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3976821646 |
|
|
Feb 28 04:18:45 PM PST 24 |
Feb 28 04:19:04 PM PST 24 |
312315100 ps |
| T208 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1035601936 |
|
|
Feb 28 04:18:55 PM PST 24 |
Feb 28 04:33:33 PM PST 24 |
748863600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3157998072 |
|
|
Feb 28 04:18:48 PM PST 24 |
Feb 28 04:19:01 PM PST 24 |
12920100 ps |
| T1139 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2045112613 |
|
|
Feb 28 04:19:06 PM PST 24 |
Feb 28 04:19:19 PM PST 24 |
52432500 ps |
| T1140 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1260373455 |
|
|
Feb 28 04:19:01 PM PST 24 |
Feb 28 04:19:18 PM PST 24 |
38318400 ps |
| T1141 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.479633449 |
|
|
Feb 28 04:18:54 PM PST 24 |
Feb 28 04:19:10 PM PST 24 |
125657400 ps |
| T1142 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.923697029 |
|
|
Feb 28 04:18:40 PM PST 24 |
Feb 28 04:18:53 PM PST 24 |
20893500 ps |
| T232 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1757576225 |
|
|
Feb 28 04:18:44 PM PST 24 |
Feb 28 04:25:07 PM PST 24 |
666474200 ps |
| T401 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3115858521 |
|
|
Feb 28 04:19:09 PM PST 24 |
Feb 28 04:19:56 PM PST 24 |
25894500 ps |
| T288 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2514910798 |
|
|
Feb 28 04:18:44 PM PST 24 |
Feb 28 04:18:58 PM PST 24 |
41321000 ps |
| T1143 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.181908160 |
|
|
Feb 28 04:18:57 PM PST 24 |
Feb 28 04:19:10 PM PST 24 |
28685400 ps |
| T284 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1820989038 |
|
|
Feb 28 04:18:52 PM PST 24 |
Feb 28 04:19:08 PM PST 24 |
361574600 ps |
| T231 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2794393019 |
|
|
Feb 28 04:18:29 PM PST 24 |
Feb 28 04:18:49 PM PST 24 |
190696400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1148110959 |
|
|
Feb 28 04:19:10 PM PST 24 |
Feb 28 04:19:23 PM PST 24 |
11939400 ps |
| T1145 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3866327747 |
|
|
Feb 28 04:18:51 PM PST 24 |
Feb 28 04:19:07 PM PST 24 |
26029100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1872259667 |
|
|
Feb 28 04:18:36 PM PST 24 |
Feb 28 04:18:50 PM PST 24 |
45787000 ps |
| T1147 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4228391140 |
|
|
Feb 28 04:18:42 PM PST 24 |
Feb 28 04:18:55 PM PST 24 |
14868100 ps |
| T233 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1539560111 |
|
|
Feb 28 04:18:45 PM PST 24 |
Feb 28 04:19:00 PM PST 24 |
28651700 ps |
| T267 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3422017696 |
|
|
Feb 28 04:18:46 PM PST 24 |
Feb 28 04:26:18 PM PST 24 |
1815247000 ps |
| T1148 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.739048210 |
|
|
Feb 28 04:19:01 PM PST 24 |
Feb 28 04:19:14 PM PST 24 |
31801600 ps |
| T1149 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.855653770 |
|
|
Feb 28 04:18:37 PM PST 24 |
Feb 28 04:18:52 PM PST 24 |
92620000 ps |
| T1150 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2991447155 |
|
|
Feb 28 04:18:47 PM PST 24 |
Feb 28 04:19:25 PM PST 24 |
195875500 ps |
| T1151 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2598258082 |
|
|
Feb 28 04:19:13 PM PST 24 |
Feb 28 04:20:06 PM PST 24 |
428109600 ps |
| T1152 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2285710089 |
|
|
Feb 28 04:18:56 PM PST 24 |
Feb 28 04:19:09 PM PST 24 |
12677900 ps |
| T1153 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1335079660 |
|
|
Feb 28 04:19:06 PM PST 24 |
Feb 28 04:19:20 PM PST 24 |
252369300 ps |
| T289 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3096889443 |
|
|
Feb 28 04:18:44 PM PST 24 |
Feb 28 04:19:22 PM PST 24 |
46939300 ps |
| T1154 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3012990011 |
|
|
Feb 28 04:18:59 PM PST 24 |
Feb 28 04:19:13 PM PST 24 |
135913600 ps |
| T1155 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1705399854 |
|
|
Feb 28 04:18:41 PM PST 24 |
Feb 28 04:18:54 PM PST 24 |
16773300 ps |
| T1156 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2541507425 |
|
|
Feb 28 04:19:46 PM PST 24 |
Feb 28 04:20:00 PM PST 24 |
14312000 ps |
| T1157 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4211429406 |
|
|
Feb 28 04:18:32 PM PST 24 |
Feb 28 04:18:47 PM PST 24 |
33969800 ps |
| T1158 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3150010782 |
|
|
Feb 28 04:18:59 PM PST 24 |
Feb 28 04:19:16 PM PST 24 |
159264300 ps |
| T1159 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.530010590 |
|
|
Feb 28 04:19:01 PM PST 24 |
Feb 28 04:19:16 PM PST 24 |
27110100 ps |
| T234 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.724031789 |
|
|
Feb 28 04:18:54 PM PST 24 |
Feb 28 04:33:49 PM PST 24 |
921414700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3268540200 |
|
|
Feb 28 04:19:21 PM PST 24 |
Feb 28 04:19:36 PM PST 24 |
26075800 ps |
| T1161 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1012723398 |
|
|
Feb 28 04:18:35 PM PST 24 |
Feb 28 04:18:52 PM PST 24 |
142546900 ps |
| T236 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3391934070 |
|
|
Feb 28 04:18:40 PM PST 24 |
Feb 28 04:18:53 PM PST 24 |
61793700 ps |
| T1162 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.133925297 |
|
|
Feb 28 04:18:31 PM PST 24 |
Feb 28 04:19:03 PM PST 24 |
300380600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4079091824 |
|
|
Feb 28 04:18:38 PM PST 24 |
Feb 28 04:18:54 PM PST 24 |
14663100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2473816525 |
|
|
Feb 28 04:18:32 PM PST 24 |
Feb 28 04:18:48 PM PST 24 |
1289709200 ps |
| T1165 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.874292758 |
|
|
Feb 28 04:19:02 PM PST 24 |
Feb 28 04:19:16 PM PST 24 |
28020200 ps |
| T1166 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1976765664 |
|
|
Feb 28 04:18:58 PM PST 24 |
Feb 28 04:19:13 PM PST 24 |
13509300 ps |
| T1167 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2583622865 |
|
|
Feb 28 04:18:45 PM PST 24 |
Feb 28 04:18:58 PM PST 24 |
13801900 ps |
| T1168 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2066563018 |
|
|
Feb 28 04:18:37 PM PST 24 |
Feb 28 04:18:52 PM PST 24 |
47766900 ps |
| T1169 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4163553436 |
|
|
Feb 28 04:18:33 PM PST 24 |
Feb 28 04:19:54 PM PST 24 |
14584933500 ps |
| T1170 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1758472223 |
|
|
Feb 28 04:18:38 PM PST 24 |
Feb 28 04:18:55 PM PST 24 |
20250200 ps |
| T1171 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1265614299 |
|
|
Feb 28 04:18:36 PM PST 24 |
Feb 28 04:18:52 PM PST 24 |
19967500 ps |
| T258 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1039558705 |
|
|
Feb 28 04:19:16 PM PST 24 |
Feb 28 04:19:33 PM PST 24 |
68190400 ps |
| T1172 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3314161101 |
|
|
Feb 28 04:18:42 PM PST 24 |
Feb 28 04:19:00 PM PST 24 |
35425900 ps |
| T1173 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2613610200 |
|
|
Feb 28 04:18:36 PM PST 24 |
Feb 28 04:19:39 PM PST 24 |
3336915200 ps |
| T1174 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.332523403 |
|
|
Feb 28 04:18:35 PM PST 24 |
Feb 28 04:18:51 PM PST 24 |
19890400 ps |
| T1175 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2292079308 |
|
|
Feb 28 04:18:51 PM PST 24 |
Feb 28 04:19:22 PM PST 24 |
104068200 ps |
| T1176 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3765585889 |
|
|
Feb 28 04:18:46 PM PST 24 |
Feb 28 04:19:02 PM PST 24 |
22760100 ps |
| T250 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1348789841 |
|
|
Feb 28 04:18:42 PM PST 24 |
Feb 28 04:19:00 PM PST 24 |
130691300 ps |
| T1177 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2302430020 |
|
|
Feb 28 04:18:55 PM PST 24 |
Feb 28 04:19:11 PM PST 24 |
171114400 ps |
| T1178 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.769611562 |
|
|
Feb 28 04:19:05 PM PST 24 |
Feb 28 04:19:19 PM PST 24 |
16322300 ps |
| T259 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.324702110 |
|
|
Feb 28 04:18:46 PM PST 24 |
Feb 28 04:19:04 PM PST 24 |
214659500 ps |
| T257 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1658436446 |
|
|
Feb 28 04:18:36 PM PST 24 |
Feb 28 04:18:52 PM PST 24 |
522868100 ps |
| T1179 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3334911651 |
|
|
Feb 28 04:18:59 PM PST 24 |
Feb 28 04:19:13 PM PST 24 |
120255700 ps |
| T1180 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3593265045 |
|
|
Feb 28 04:19:05 PM PST 24 |
Feb 28 04:19:22 PM PST 24 |
176790600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.237570112 |
|
|
Feb 28 04:18:41 PM PST 24 |
Feb 28 04:18:57 PM PST 24 |
31144200 ps |
| T1182 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.75632202 |
|
|
Feb 28 04:18:58 PM PST 24 |
Feb 28 04:19:16 PM PST 24 |
456725300 ps |
| T1183 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3503089958 |
|
|
Feb 28 04:18:46 PM PST 24 |
Feb 28 04:19:02 PM PST 24 |
53759800 ps |
| T266 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3863419796 |
|
|
Feb 28 04:18:52 PM PST 24 |
Feb 28 04:19:07 PM PST 24 |
212096800 ps |
| T237 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2064862235 |
|
|
Feb 28 04:18:37 PM PST 24 |
Feb 28 04:18:50 PM PST 24 |
29101600 ps |
| T253 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1819417798 |
|
|
Feb 28 04:18:45 PM PST 24 |
Feb 28 04:19:01 PM PST 24 |
654179600 ps |
| T285 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.583184276 |
|
|
Feb 28 04:19:07 PM PST 24 |
Feb 28 04:19:26 PM PST 24 |
364564200 ps |
| T286 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2936273750 |
|
|
Feb 28 04:18:43 PM PST 24 |
Feb 28 04:18:59 PM PST 24 |
73308500 ps |
| T265 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4239322792 |
|
|
Feb 28 04:19:05 PM PST 24 |
Feb 28 04:27:08 PM PST 24 |
900114200 ps |
| T1184 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2389550522 |
|
|
Feb 28 04:19:35 PM PST 24 |
Feb 28 04:19:56 PM PST 24 |
347698200 ps |
| T1185 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1342967192 |
|
|
Feb 28 04:19:35 PM PST 24 |
Feb 28 04:19:49 PM PST 24 |
14862700 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3617892703 |
|
|
Feb 28 04:18:38 PM PST 24 |
Feb 28 04:18:54 PM PST 24 |
40889100 ps |
| T287 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1885837214 |
|
|
Feb 28 04:19:08 PM PST 24 |
Feb 28 04:19:27 PM PST 24 |
221668800 ps |
| T1187 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.394732956 |
|
|
Feb 28 04:18:44 PM PST 24 |
Feb 28 04:19:20 PM PST 24 |
3186677000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.699815488 |
|
|
Feb 28 04:18:39 PM PST 24 |
Feb 28 04:18:57 PM PST 24 |
38510700 ps |
| T251 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2238424610 |
|
|
Feb 28 04:18:30 PM PST 24 |
Feb 28 04:18:49 PM PST 24 |
61313800 ps |
| T1189 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1072657593 |
|
|
Feb 28 04:19:03 PM PST 24 |
Feb 28 04:19:19 PM PST 24 |
48277900 ps |
| T341 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3747242302 |
|
|
Feb 28 04:19:05 PM PST 24 |
Feb 28 04:33:48 PM PST 24 |
1862244100 ps |
| T252 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1379266352 |
|
|
Feb 28 04:18:58 PM PST 24 |
Feb 28 04:19:15 PM PST 24 |
165870500 ps |
| T1190 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3201361746 |
|
|
Feb 28 04:19:04 PM PST 24 |
Feb 28 04:19:18 PM PST 24 |
23128600 ps |
| T1191 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2913129642 |
|
|
Feb 28 04:18:49 PM PST 24 |
Feb 28 04:19:06 PM PST 24 |
26116000 ps |
| T290 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2190158450 |
|
|
Feb 28 04:18:41 PM PST 24 |
Feb 28 04:25:03 PM PST 24 |
402715600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.721056611 |
|
|
Feb 28 04:18:44 PM PST 24 |
Feb 28 04:18:58 PM PST 24 |
30977700 ps |
| T263 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3294616901 |
|
|
Feb 28 04:19:10 PM PST 24 |
Feb 28 04:19:26 PM PST 24 |
60245200 ps |
| T1193 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3533629952 |
|
|
Feb 28 04:19:04 PM PST 24 |
Feb 28 04:19:19 PM PST 24 |
33399200 ps |
| T291 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.580895080 |
|
|
Feb 28 04:18:57 PM PST 24 |
Feb 28 04:19:12 PM PST 24 |
153852000 ps |
| T1194 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1383785712 |
|
|
Feb 28 04:18:43 PM PST 24 |
Feb 28 04:18:58 PM PST 24 |
20922700 ps |
| T1195 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1106812212 |
|
|
Feb 28 04:19:47 PM PST 24 |
Feb 28 04:20:05 PM PST 24 |
93095900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3422105233 |
|
|
Feb 28 04:18:47 PM PST 24 |
Feb 28 04:19:00 PM PST 24 |
49070600 ps |
| T1197 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3017480352 |
|
|
Feb 28 04:19:08 PM PST 24 |
Feb 28 04:19:25 PM PST 24 |
42880500 ps |
| T1198 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3354091117 |
|
|
Feb 28 04:18:54 PM PST 24 |
Feb 28 04:19:08 PM PST 24 |
14798000 ps |
| T1199 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2099624503 |
|
|
Feb 28 04:19:54 PM PST 24 |
Feb 28 04:20:07 PM PST 24 |
36113500 ps |
| T260 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2893088314 |
|
|
Feb 28 04:18:57 PM PST 24 |
Feb 28 04:19:16 PM PST 24 |
188134200 ps |
| T1200 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2252213726 |
|
|
Feb 28 04:18:59 PM PST 24 |
Feb 28 04:19:15 PM PST 24 |
24085700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.428487121 |
|
|
Feb 28 04:18:45 PM PST 24 |
Feb 28 04:19:03 PM PST 24 |
112810600 ps |
| T238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.645192087 |
|
|
Feb 28 04:18:31 PM PST 24 |
Feb 28 04:18:45 PM PST 24 |
51557100 ps |
| T1202 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.49069497 |
|
|
Feb 28 04:18:45 PM PST 24 |
Feb 28 04:19:02 PM PST 24 |
513969200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1066740027 |
|
|
Feb 28 04:18:35 PM PST 24 |
Feb 28 04:19:05 PM PST 24 |
232054600 ps |
| T292 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.4087192186 |
|
|
Feb 28 04:18:54 PM PST 24 |
Feb 28 04:19:10 PM PST 24 |
947670900 ps |
| T1204 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1359286985 |
|
|
Feb 28 04:18:42 PM PST 24 |
Feb 28 04:18:58 PM PST 24 |
66605700 ps |
| T1205 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1839106997 |
|
|
Feb 28 04:18:54 PM PST 24 |
Feb 28 04:19:07 PM PST 24 |
74707000 ps |
| T1206 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.425203746 |
|
|
Feb 28 04:18:48 PM PST 24 |
Feb 28 04:19:06 PM PST 24 |
53978900 ps |
| T1207 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4256025456 |
|
|
Feb 28 04:18:37 PM PST 24 |
Feb 28 04:18:51 PM PST 24 |
12997200 ps |
| T1208 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.497114786 |
|
|
Feb 28 04:18:50 PM PST 24 |
Feb 28 04:19:03 PM PST 24 |
43311000 ps |
| T1209 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3384334665 |
|
|
Feb 28 04:18:39 PM PST 24 |
Feb 28 04:18:53 PM PST 24 |
20952200 ps |
| T1210 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.4174657030 |
|
|
Feb 28 04:18:43 PM PST 24 |
Feb 28 04:19:19 PM PST 24 |
645201500 ps |
| T339 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3882768824 |
|
|
Feb 28 04:18:29 PM PST 24 |
Feb 28 04:26:00 PM PST 24 |
407682100 ps |
| T1211 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1475517222 |
|
|
Feb 28 04:18:55 PM PST 24 |
Feb 28 04:19:08 PM PST 24 |
63551800 ps |
| T1212 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4209593833 |
|
|
Feb 28 04:18:37 PM PST 24 |
Feb 28 04:18:53 PM PST 24 |
71669000 ps |
| T1213 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2709787474 |
|
|
Feb 28 04:19:05 PM PST 24 |
Feb 28 04:19:22 PM PST 24 |
29801700 ps |
| T1214 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1562814868 |
|
|
Feb 28 04:18:39 PM PST 24 |
Feb 28 04:18:53 PM PST 24 |
20319500 ps |
| T337 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3983390027 |
|
|
Feb 28 04:18:49 PM PST 24 |
Feb 28 04:25:28 PM PST 24 |
802425400 ps |
| T264 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.860831274 |
|
|
Feb 28 04:19:02 PM PST 24 |
Feb 28 04:19:21 PM PST 24 |
98571200 ps |
| T336 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.198781444 |
|
|
Feb 28 04:18:25 PM PST 24 |
Feb 28 04:25:56 PM PST 24 |
944402600 ps |
| T1215 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1929621990 |
|
|
Feb 28 04:19:10 PM PST 24 |
Feb 28 04:19:24 PM PST 24 |
25476700 ps |
| T1216 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2081307303 |
|
|
Feb 28 04:18:52 PM PST 24 |
Feb 28 04:19:06 PM PST 24 |
23339600 ps |
| T268 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4130513706 |
|
|
Feb 28 04:18:41 PM PST 24 |
Feb 28 04:18:57 PM PST 24 |
32618700 ps |
| T293 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2199718142 |
|
|
Feb 28 04:18:47 PM PST 24 |
Feb 28 04:19:07 PM PST 24 |
302572300 ps |
| T1217 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.195914879 |
|
|
Feb 28 04:19:06 PM PST 24 |
Feb 28 04:19:35 PM PST 24 |
66130500 ps |
| T1218 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1860592136 |
|
|
Feb 28 04:18:53 PM PST 24 |
Feb 28 04:19:12 PM PST 24 |
90456000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1398242910 |
|
|
Feb 28 04:18:47 PM PST 24 |
Feb 28 04:19:20 PM PST 24 |
1222606900 ps |
| T1220 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3663588686 |
|
|
Feb 28 04:19:08 PM PST 24 |
Feb 28 04:19:22 PM PST 24 |
31750400 ps |
| T1221 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.939470684 |
|
|
Feb 28 04:18:45 PM PST 24 |
Feb 28 04:19:02 PM PST 24 |
201132000 ps |
| T1222 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.46360943 |
|
|
Feb 28 04:19:23 PM PST 24 |
Feb 28 04:19:36 PM PST 24 |
55580800 ps |
| T1223 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.406343357 |
|
|
Feb 28 04:19:30 PM PST 24 |
Feb 28 04:19:44 PM PST 24 |
56462800 ps |
| T1224 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.797240617 |
|
|
Feb 28 04:18:48 PM PST 24 |
Feb 28 04:19:01 PM PST 24 |
20922300 ps |
| T1225 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3305234421 |
|
|
Feb 28 04:19:02 PM PST 24 |
Feb 28 04:19:18 PM PST 24 |
40176800 ps |
| T1226 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1381209882 |
|
|
Feb 28 04:18:52 PM PST 24 |
Feb 28 04:19:27 PM PST 24 |
608240000 ps |
| T1227 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1613163767 |
|
|
Feb 28 04:18:58 PM PST 24 |
Feb 28 04:19:13 PM PST 24 |
59188500 ps |
| T294 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.207032734 |
|
|
Feb 28 04:19:11 PM PST 24 |
Feb 28 04:19:46 PM PST 24 |
422510800 ps |
| T1228 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.452665229 |
|
|
Feb 28 04:19:00 PM PST 24 |
Feb 28 04:19:17 PM PST 24 |
96482000 ps |
| T295 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2100742918 |
|
|
Feb 28 04:18:50 PM PST 24 |
Feb 28 04:19:07 PM PST 24 |
91582200 ps |
| T1229 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3470799239 |
|
|
Feb 28 04:19:17 PM PST 24 |
Feb 28 04:19:34 PM PST 24 |
25594400 ps |
| T262 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2163493794 |
|
|
Feb 28 04:18:43 PM PST 24 |
Feb 28 04:19:02 PM PST 24 |
81859000 ps |
| T1230 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2066617629 |
|
|
Feb 28 04:19:03 PM PST 24 |
Feb 28 04:25:19 PM PST 24 |
679038300 ps |
| T1231 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.910556362 |
|
|
Feb 28 04:18:40 PM PST 24 |
Feb 28 04:18:55 PM PST 24 |
28048400 ps |
| T1232 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3150135493 |
|
|
Feb 28 04:18:41 PM PST 24 |
Feb 28 04:18:56 PM PST 24 |
73432000 ps |
| T1233 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3883985349 |
|
|
Feb 28 04:18:57 PM PST 24 |
Feb 28 04:19:10 PM PST 24 |
93559100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1957204643 |
|
|
Feb 28 04:18:41 PM PST 24 |
Feb 28 04:19:00 PM PST 24 |
429849500 ps |
| T1235 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.838043041 |
|
|
Feb 28 04:19:00 PM PST 24 |
Feb 28 04:19:18 PM PST 24 |
1036204300 ps |
| T1236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.4096330873 |
|
|
Feb 28 04:18:35 PM PST 24 |
Feb 28 04:18:51 PM PST 24 |
145553000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2245813389 |
|
|
Feb 28 04:19:39 PM PST 24 |
Feb 28 04:19:53 PM PST 24 |
53658000 ps |
| T338 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1860802529 |
|
|
Feb 28 04:19:04 PM PST 24 |
Feb 28 04:33:55 PM PST 24 |
1324460200 ps |
| T1238 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.242533120 |
|
|
Feb 28 04:18:58 PM PST 24 |
Feb 28 04:19:15 PM PST 24 |
331029100 ps |
| T1239 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1905912029 |
|
|
Feb 28 04:18:51 PM PST 24 |
Feb 28 04:19:07 PM PST 24 |
180798500 ps |
| T1240 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1954628258 |
|
|
Feb 28 04:18:55 PM PST 24 |
Feb 28 04:19:08 PM PST 24 |
59962400 ps |
| T1241 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1226906210 |
|
|
Feb 28 04:18:41 PM PST 24 |
Feb 28 04:19:45 PM PST 24 |
6235991100 ps |
| T1242 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3977662662 |
|
|
Feb 28 04:19:17 PM PST 24 |
Feb 28 04:19:31 PM PST 24 |
14326500 ps |
| T1243 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2121191904 |
|
|
Feb 28 04:19:09 PM PST 24 |
Feb 28 04:19:25 PM PST 24 |
96454000 ps |
| T1244 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1567649357 |
|
|
Feb 28 04:19:22 PM PST 24 |
Feb 28 04:19:41 PM PST 24 |
113418800 ps |
| T1245 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3494535980 |
|
|
Feb 28 04:18:56 PM PST 24 |
Feb 28 04:19:10 PM PST 24 |
112869700 ps |
| T1246 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.837785349 |
|
|
Feb 28 04:19:08 PM PST 24 |
Feb 28 04:19:26 PM PST 24 |
79877300 ps |
| T261 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2137692614 |
|
|
Feb 28 04:19:10 PM PST 24 |
Feb 28 04:35:40 PM PST 24 |
2072305500 ps |
| T343 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4086219018 |
|
|
Feb 28 04:18:58 PM PST 24 |
Feb 28 04:33:46 PM PST 24 |
756041100 ps |
| T1247 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3946653309 |
|
|
Feb 28 04:19:16 PM PST 24 |
Feb 28 04:31:42 PM PST 24 |
868792600 ps |
| T1248 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2926348309 |
|
|
Feb 28 04:19:11 PM PST 24 |
Feb 28 04:19:27 PM PST 24 |
22107000 ps |
| T1249 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.630602778 |
|
|
Feb 28 04:19:02 PM PST 24 |
Feb 28 04:19:19 PM PST 24 |
35325100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3249938715 |
|
|
Feb 28 04:18:55 PM PST 24 |
Feb 28 04:19:10 PM PST 24 |
80263800 ps |
| T1251 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2850336217 |
|
|
Feb 28 04:18:36 PM PST 24 |
Feb 28 04:18:50 PM PST 24 |
17727300 ps |
| T1252 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2926346769 |
|
|
Feb 28 04:18:44 PM PST 24 |
Feb 28 04:20:01 PM PST 24 |
9577698000 ps |
| T269 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1546279713 |
|
|
Feb 28 04:18:45 PM PST 24 |
Feb 28 04:31:08 PM PST 24 |
1357752000 ps |