Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	280339	1		T1	2		T3	1		T4	2
all_values[1]	280339	1		T1	2		T3	1		T4	2
all_values[2]	280339	1		T1	2		T3	1		T4	2
all_values[3]	280339	1		T1	2		T3	1		T4	2
all_values[4]	280339	1		T1	2		T3	1		T4	2
all_values[5]	280339	1		T1	2		T3	1		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	566908	1		T1	12		T3	6		T4	12
auto[1]	1115126	1		T5	8744		T8	18184		T7	13028

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	820071	1		T1	7		T3	4		T4	7
auto[1]	861963	1		T1	5		T3	2		T4	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	280166	1		T1	2		T3	1		T4	2
all_values[0]	auto[1]	auto[1]	173	1		T280	4		T281	5		T351	2
all_values[1]	auto[0]	auto[1]	280183	1		T1	2		T3	1		T4	2
all_values[1]	auto[1]	auto[1]	156	1		T280	1		T281	5		T351	1
all_values[2]	auto[0]	auto[0]	1582	1		T1	2		T3	1		T4	2
all_values[2]	auto[0]	auto[1]	58	1		T280	1		T281	1		T353	2
all_values[2]	auto[1]	auto[0]	278643	1		T5	2186		T8	4546		T7	3257
all_values[2]	auto[1]	auto[1]	56	1		T281	1		T351	2		T353	1
all_values[3]	auto[0]	auto[0]	1591	1		T1	2		T3	1		T4	2
all_values[3]	auto[0]	auto[1]	48	1		T280	1		T351	1		T353	2
all_values[3]	auto[1]	auto[0]	78181	1		T5	1093		T8	509		T7	1073
all_values[3]	auto[1]	auto[1]	200519	1		T5	1093		T8	4037		T7	2184
all_values[4]	auto[0]	auto[0]	1117	1		T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	510	1		T1	1		T4	1		T16	1
all_values[4]	auto[1]	auto[0]	178826	1		T5	1093		T8	3178		T7	2165
all_values[4]	auto[1]	auto[1]	99886	1		T5	1093		T8	1368		T7	1092
all_values[5]	auto[0]	auto[0]	1510	1		T1	2		T3	1		T4	2
all_values[5]	auto[0]	auto[1]	143	1		T32	1		T33	1		T34	1
all_values[5]	auto[1]	auto[0]	278621	1		T5	2186		T8	4546		T7	3257
all_values[5]	auto[1]	auto[1]	65	1		T281	1		T351	1		T353	2