Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T16 |
2 |
|
T18 |
12 |
|
T253 |
1 |
| others[1] |
212 |
1 |
|
T7 |
1 |
|
T56 |
1 |
|
T18 |
11 |
| others[2] |
203 |
1 |
|
T18 |
9 |
|
T239 |
1 |
|
T210 |
1 |
| others[3] |
414 |
1 |
|
T8 |
1 |
|
T19 |
1 |
|
T18 |
19 |
| false |
148 |
1 |
|
T18 |
9 |
|
T32 |
1 |
|
T51 |
1 |
| true |
12520 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T18 |
10 |
|
T122 |
1 |
|
T51 |
2 |
| others[1] |
223 |
1 |
|
T18 |
6 |
|
T211 |
1 |
|
T253 |
1 |
| others[2] |
229 |
1 |
|
T16 |
1 |
|
T18 |
11 |
|
T51 |
2 |
| others[3] |
364 |
1 |
|
T18 |
12 |
|
T211 |
1 |
|
T332 |
1 |
| false |
113 |
1 |
|
T18 |
6 |
|
T122 |
1 |
|
T193 |
1 |
| true |
12601 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8138 |
1 |
|
T3 |
2 |
|
T4 |
13 |
|
T6 |
22 |
| others[1] |
1225 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T6 |
13 |
| others[2] |
1230 |
1 |
|
T4 |
21 |
|
T6 |
16 |
|
T57 |
18 |
| others[3] |
2079 |
1 |
|
T4 |
29 |
|
T16 |
2 |
|
T6 |
36 |
| false |
640 |
1 |
|
T4 |
7 |
|
T6 |
13 |
|
T57 |
10 |
| true |
438 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8100 |
1 |
|
T3 |
2 |
|
T4 |
24 |
|
T16 |
1 |
| others[1] |
1319 |
1 |
|
T4 |
17 |
|
T6 |
22 |
|
T57 |
13 |
| others[2] |
1238 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T6 |
30 |
| others[3] |
2013 |
1 |
|
T4 |
29 |
|
T16 |
1 |
|
T6 |
26 |
| false |
654 |
1 |
|
T4 |
8 |
|
T6 |
4 |
|
T57 |
8 |
| true |
426 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
83 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T44 |
1 |
| others[1] |
92 |
1 |
|
T16 |
1 |
|
T18 |
7 |
|
T200 |
1 |
| others[2] |
109 |
1 |
|
T18 |
3 |
|
T210 |
1 |
|
T211 |
1 |
| others[3] |
179 |
1 |
|
T18 |
5 |
|
T332 |
1 |
|
T253 |
2 |
| false |
61 |
1 |
|
T18 |
2 |
|
T210 |
1 |
|
T51 |
1 |
| true |
13226 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T18 |
11 |
|
T22 |
1 |
|
T122 |
1 |
| others[1] |
248 |
1 |
|
T18 |
14 |
|
T239 |
1 |
|
T211 |
1 |
| others[2] |
242 |
1 |
|
T18 |
5 |
|
T210 |
1 |
|
T23 |
1 |
| others[3] |
428 |
1 |
|
T18 |
19 |
|
T332 |
1 |
|
T193 |
1 |
| false |
133 |
1 |
|
T19 |
1 |
|
T18 |
11 |
|
T32 |
1 |
| true |
12461 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7980 |
1 |
|
T3 |
2 |
|
T4 |
13 |
|
T6 |
12 |
| others[1] |
1003 |
1 |
|
T1 |
1 |
|
T4 |
12 |
|
T6 |
10 |
| others[2] |
1067 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T6 |
10 |
| others[3] |
1740 |
1 |
|
T2 |
1 |
|
T4 |
31 |
|
T5 |
1 |
| false |
560 |
1 |
|
T4 |
10 |
|
T6 |
5 |
|
T57 |
12 |
| true |
1400 |
1 |
|
T6 |
40 |
|
T8 |
1 |
|
T59 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T16 |
1 |
|
T18 |
12 |
|
T32 |
1 |
| others[1] |
208 |
1 |
|
T18 |
11 |
|
T44 |
1 |
|
T122 |
1 |
| others[2] |
205 |
1 |
|
T18 |
14 |
|
T24 |
1 |
|
T211 |
1 |
| others[3] |
405 |
1 |
|
T7 |
1 |
|
T18 |
11 |
|
T33 |
1 |
| false |
125 |
1 |
|
T5 |
1 |
|
T18 |
7 |
|
T200 |
1 |
| true |
12565 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T18 |
8 |
|
T211 |
1 |
|
T99 |
11 |
| others[1] |
205 |
1 |
|
T16 |
1 |
|
T18 |
9 |
|
T51 |
1 |
| others[2] |
229 |
1 |
|
T18 |
11 |
|
T210 |
1 |
|
T211 |
1 |
| others[3] |
386 |
1 |
|
T18 |
17 |
|
T210 |
1 |
|
T99 |
17 |
| false |
106 |
1 |
|
T18 |
2 |
|
T200 |
1 |
|
T125 |
1 |
| true |
12609 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8159 |
1 |
|
T3 |
2 |
|
T4 |
10 |
|
T6 |
16 |
| others[1] |
1215 |
1 |
|
T4 |
18 |
|
T6 |
20 |
|
T57 |
13 |
| others[2] |
1282 |
1 |
|
T4 |
17 |
|
T6 |
27 |
|
T59 |
1 |
| others[3] |
2064 |
1 |
|
T2 |
1 |
|
T4 |
30 |
|
T16 |
2 |
| false |
599 |
1 |
|
T4 |
10 |
|
T6 |
7 |
|
T57 |
6 |
| true |
431 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T4 |
14 |
|
T16 |
1 |
|
T6 |
27 |
| others[1] |
1256 |
1 |
|
T4 |
19 |
|
T6 |
18 |
|
T57 |
21 |
| others[2] |
1253 |
1 |
|
T2 |
1 |
|
T4 |
14 |
|
T16 |
1 |
| others[3] |
2063 |
1 |
|
T4 |
27 |
|
T6 |
26 |
|
T57 |
22 |
| false |
608 |
1 |
|
T4 |
11 |
|
T6 |
13 |
|
T57 |
8 |
| true |
434 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T18 |
3 |
|
T210 |
1 |
|
T122 |
1 |
| others[1] |
100 |
1 |
|
T18 |
4 |
|
T200 |
1 |
|
T125 |
1 |
| others[2] |
103 |
1 |
|
T16 |
1 |
|
T18 |
2 |
|
T44 |
1 |
| others[3] |
170 |
1 |
|
T16 |
1 |
|
T18 |
8 |
|
T211 |
1 |
| false |
62 |
1 |
|
T18 |
4 |
|
T211 |
1 |
|
T332 |
1 |
| true |
6312 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T5 |
1 |
|
T18 |
10 |
|
T99 |
9 |
| others[1] |
258 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T18 |
11 |
| others[2] |
232 |
1 |
|
T18 |
10 |
|
T24 |
1 |
|
T211 |
1 |
| others[3] |
405 |
1 |
|
T16 |
1 |
|
T19 |
1 |
|
T18 |
14 |
| false |
121 |
1 |
|
T18 |
8 |
|
T239 |
1 |
|
T253 |
1 |
| true |
5636 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1067 |
1 |
|
T1 |
1 |
|
T4 |
22 |
|
T5 |
1 |
| others[1] |
1041 |
1 |
|
T4 |
12 |
|
T6 |
11 |
|
T57 |
15 |
| others[2] |
1029 |
1 |
|
T2 |
1 |
|
T4 |
19 |
|
T6 |
5 |
| others[3] |
1753 |
1 |
|
T4 |
22 |
|
T16 |
1 |
|
T6 |
15 |
| false |
588 |
1 |
|
T4 |
10 |
|
T6 |
7 |
|
T57 |
9 |
| true |
1386 |
1 |
|
T6 |
53 |
|
T8 |
1 |
|
T56 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T18 |
9 |
|
T32 |
1 |
|
T23 |
1 |
| others[1] |
251 |
1 |
|
T16 |
1 |
|
T8 |
1 |
|
T18 |
8 |
| others[2] |
213 |
1 |
|
T18 |
10 |
|
T51 |
1 |
|
T99 |
11 |
| others[3] |
370 |
1 |
|
T18 |
15 |
|
T99 |
10 |
|
T52 |
1 |
| false |
116 |
1 |
|
T18 |
12 |
|
T297 |
1 |
|
T99 |
5 |
| true |
5662 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T16 |
1 |
|
T18 |
12 |
|
T332 |
1 |
| others[1] |
219 |
1 |
|
T18 |
13 |
|
T200 |
1 |
|
T122 |
1 |
| others[2] |
212 |
1 |
|
T18 |
10 |
|
T122 |
1 |
|
T99 |
9 |
| others[3] |
410 |
1 |
|
T18 |
15 |
|
T32 |
1 |
|
T44 |
1 |
| false |
125 |
1 |
|
T18 |
3 |
|
T51 |
1 |
|
T99 |
5 |
| true |
5682 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T4 |
15 |
|
T16 |
1 |
|
T6 |
20 |
| others[1] |
1233 |
1 |
|
T2 |
1 |
|
T4 |
16 |
|
T6 |
22 |
| others[2] |
1234 |
1 |
|
T4 |
24 |
|
T6 |
15 |
|
T57 |
11 |
| others[3] |
2037 |
1 |
|
T4 |
23 |
|
T16 |
1 |
|
T6 |
33 |
| false |
665 |
1 |
|
T4 |
7 |
|
T6 |
10 |
|
T57 |
4 |
| true |
443 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T4 |
16 |
|
T6 |
21 |
|
T57 |
17 |
| others[1] |
1260 |
1 |
|
T4 |
14 |
|
T16 |
1 |
|
T6 |
21 |
| others[2] |
1252 |
1 |
|
T4 |
20 |
|
T6 |
15 |
|
T57 |
15 |
| others[3] |
2055 |
1 |
|
T2 |
1 |
|
T4 |
25 |
|
T16 |
1 |
| false |
629 |
1 |
|
T4 |
10 |
|
T6 |
6 |
|
T57 |
5 |
| true |
425 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T18 |
5 |
|
T200 |
1 |
|
T51 |
1 |
| others[1] |
105 |
1 |
|
T18 |
2 |
|
T332 |
1 |
|
T99 |
5 |
| others[2] |
99 |
1 |
|
T16 |
1 |
|
T18 |
3 |
|
T44 |
1 |
| others[3] |
159 |
1 |
|
T16 |
1 |
|
T18 |
12 |
|
T211 |
1 |
| false |
52 |
1 |
|
T18 |
2 |
|
T210 |
2 |
|
T211 |
1 |
| true |
6348 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T18 |
9 |
| others[1] |
226 |
1 |
|
T18 |
8 |
|
T200 |
1 |
|
T253 |
1 |
| others[2] |
248 |
1 |
|
T18 |
8 |
|
T210 |
1 |
|
T211 |
1 |
| others[3] |
376 |
1 |
|
T5 |
1 |
|
T18 |
15 |
|
T239 |
1 |
| false |
131 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T33 |
1 |
| true |
5662 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1059 |
1 |
|
T4 |
17 |
|
T5 |
1 |
|
T16 |
1 |
| others[1] |
1061 |
1 |
|
T4 |
14 |
|
T6 |
13 |
|
T57 |
12 |
| others[2] |
1038 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T16 |
1 |
| others[3] |
1782 |
1 |
|
T4 |
31 |
|
T6 |
19 |
|
T57 |
23 |
| false |
522 |
1 |
|
T4 |
6 |
|
T6 |
6 |
|
T7 |
1 |
| true |
1402 |
1 |
|
T1 |
1 |
|
T6 |
46 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T18 |
7 |
|
T44 |
1 |
|
T24 |
1 |
| others[1] |
233 |
1 |
|
T18 |
10 |
|
T211 |
2 |
|
T99 |
8 |
| others[2] |
255 |
1 |
|
T18 |
7 |
|
T193 |
1 |
|
T99 |
10 |
| others[3] |
380 |
1 |
|
T18 |
15 |
|
T32 |
1 |
|
T210 |
1 |
| false |
110 |
1 |
|
T18 |
6 |
|
T99 |
8 |
|
T60 |
1 |
| true |
5676 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T18 |
9 |
|
T211 |
1 |
|
T51 |
1 |
| others[1] |
222 |
1 |
|
T18 |
14 |
|
T51 |
1 |
|
T127 |
1 |
| others[2] |
217 |
1 |
|
T18 |
8 |
|
T332 |
1 |
|
T99 |
14 |
| others[3] |
378 |
1 |
|
T18 |
14 |
|
T44 |
1 |
|
T211 |
1 |
| false |
103 |
1 |
|
T18 |
7 |
|
T99 |
5 |
|
T61 |
6 |
| true |
5728 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T4 |
13 |
|
T6 |
18 |
|
T57 |
20 |
| others[1] |
1226 |
1 |
|
T4 |
20 |
|
T16 |
2 |
|
T6 |
16 |
| others[2] |
1228 |
1 |
|
T4 |
19 |
|
T6 |
19 |
|
T57 |
7 |
| others[3] |
2091 |
1 |
|
T2 |
1 |
|
T4 |
25 |
|
T6 |
38 |
| false |
621 |
1 |
|
T4 |
8 |
|
T6 |
9 |
|
T57 |
9 |
| true |
445 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1208 |
1 |
|
T4 |
17 |
|
T6 |
21 |
|
T57 |
11 |
| others[1] |
1267 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T6 |
24 |
| others[2] |
1249 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T6 |
17 |
| others[3] |
2056 |
1 |
|
T2 |
1 |
|
T4 |
27 |
|
T6 |
22 |
| false |
659 |
1 |
|
T4 |
4 |
|
T6 |
16 |
|
T57 |
8 |
| true |
425 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
88 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T210 |
1 |
| others[1] |
94 |
1 |
|
T18 |
5 |
|
T33 |
1 |
|
T200 |
1 |
| others[2] |
101 |
1 |
|
T16 |
1 |
|
T18 |
3 |
|
T211 |
1 |
| others[3] |
144 |
1 |
|
T18 |
5 |
|
T44 |
1 |
|
T122 |
2 |
| false |
57 |
1 |
|
T210 |
1 |
|
T211 |
1 |
|
T253 |
1 |
| true |
6380 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T19 |
1 |
|
T18 |
10 |
|
T210 |
1 |
| others[1] |
231 |
1 |
|
T18 |
9 |
|
T33 |
1 |
|
T253 |
1 |
| others[2] |
245 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T18 |
11 |
| others[3] |
392 |
1 |
|
T56 |
1 |
|
T18 |
17 |
|
T44 |
1 |
| false |
126 |
1 |
|
T18 |
9 |
|
T99 |
7 |
|
T61 |
8 |
| true |
5638 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1107 |
1 |
|
T4 |
16 |
|
T6 |
15 |
|
T57 |
18 |
| others[1] |
1016 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T6 |
10 |
| others[2] |
1058 |
1 |
|
T1 |
1 |
|
T4 |
20 |
|
T6 |
10 |
| others[3] |
1761 |
1 |
|
T4 |
30 |
|
T5 |
1 |
|
T16 |
2 |
| false |
568 |
1 |
|
T4 |
8 |
|
T6 |
8 |
|
T57 |
7 |
| true |
1354 |
1 |
|
T6 |
38 |
|
T8 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T56 |
1 |
|
T19 |
1 |
|
T18 |
7 |
| others[1] |
239 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T250 |
1 |
| others[2] |
225 |
1 |
|
T18 |
11 |
|
T44 |
1 |
|
T51 |
1 |
| others[3] |
356 |
1 |
|
T16 |
1 |
|
T18 |
20 |
|
T24 |
1 |
| false |
117 |
1 |
|
T18 |
5 |
|
T33 |
1 |
|
T99 |
3 |
| true |
5709 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T18 |
15 |
|
T51 |
1 |
|
T99 |
11 |
| others[1] |
209 |
1 |
|
T18 |
11 |
|
T210 |
1 |
|
T122 |
1 |
| others[2] |
208 |
1 |
|
T18 |
9 |
|
T200 |
1 |
|
T211 |
1 |
| others[3] |
344 |
1 |
|
T16 |
1 |
|
T18 |
14 |
|
T210 |
1 |
| false |
94 |
1 |
|
T18 |
5 |
|
T51 |
1 |
|
T99 |
3 |
| true |
5775 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1184 |
1 |
|
T4 |
14 |
|
T16 |
1 |
|
T6 |
18 |
| others[1] |
1223 |
1 |
|
T4 |
21 |
|
T16 |
1 |
|
T6 |
21 |
| others[2] |
1254 |
1 |
|
T4 |
12 |
|
T6 |
19 |
|
T57 |
12 |
| others[3] |
2122 |
1 |
|
T2 |
1 |
|
T4 |
25 |
|
T6 |
29 |
| false |
643 |
1 |
|
T4 |
13 |
|
T6 |
13 |
|
T57 |
6 |
| true |
438 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |