Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T4 |
20 |
|
T16 |
1 |
|
T6 |
29 |
| others[1] |
1226 |
1 |
|
T4 |
25 |
|
T6 |
8 |
|
T57 |
23 |
| others[2] |
1226 |
1 |
|
T2 |
1 |
|
T4 |
12 |
|
T16 |
1 |
| others[3] |
2098 |
1 |
|
T4 |
22 |
|
T6 |
41 |
|
T57 |
16 |
| false |
635 |
1 |
|
T4 |
6 |
|
T6 |
5 |
|
T57 |
10 |
| true |
419 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T18 |
5 |
|
T200 |
1 |
|
T210 |
1 |
| others[1] |
80 |
1 |
|
T16 |
1 |
|
T18 |
3 |
|
T210 |
1 |
| others[2] |
97 |
1 |
|
T18 |
5 |
|
T211 |
1 |
|
T253 |
1 |
| others[3] |
191 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T44 |
1 |
| false |
49 |
1 |
|
T18 |
1 |
|
T99 |
1 |
|
T61 |
2 |
| true |
6336 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T18 |
6 |
|
T122 |
1 |
|
T51 |
1 |
| others[1] |
242 |
1 |
|
T5 |
1 |
|
T18 |
7 |
|
T32 |
1 |
| others[2] |
233 |
1 |
|
T18 |
10 |
|
T200 |
1 |
|
T51 |
1 |
| others[3] |
389 |
1 |
|
T18 |
16 |
|
T211 |
1 |
|
T123 |
1 |
| false |
105 |
1 |
|
T18 |
2 |
|
T211 |
1 |
|
T253 |
1 |
| true |
5652 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1071 |
1 |
|
T2 |
1 |
|
T4 |
14 |
|
T16 |
1 |
| others[1] |
1083 |
1 |
|
T4 |
14 |
|
T6 |
9 |
|
T57 |
13 |
| others[2] |
1065 |
1 |
|
T4 |
15 |
|
T6 |
10 |
|
T8 |
1 |
| others[3] |
1755 |
1 |
|
T4 |
29 |
|
T16 |
1 |
|
T6 |
21 |
| false |
524 |
1 |
|
T1 |
1 |
|
T4 |
13 |
|
T6 |
5 |
| true |
1366 |
1 |
|
T5 |
1 |
|
T6 |
51 |
|
T56 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T19 |
1 |
|
T18 |
6 |
|
T239 |
1 |
| others[1] |
254 |
1 |
|
T18 |
10 |
|
T32 |
1 |
|
T200 |
1 |
| others[2] |
212 |
1 |
|
T18 |
8 |
|
T33 |
1 |
|
T125 |
1 |
| others[3] |
393 |
1 |
|
T56 |
1 |
|
T18 |
19 |
|
T211 |
2 |
| false |
129 |
1 |
|
T7 |
1 |
|
T18 |
5 |
|
T99 |
5 |
| true |
5644 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T18 |
8 |
|
T51 |
1 |
|
T99 |
12 |
| others[1] |
209 |
1 |
|
T18 |
8 |
|
T44 |
1 |
|
T210 |
1 |
| others[2] |
234 |
1 |
|
T18 |
6 |
|
T122 |
1 |
|
T51 |
1 |
| others[3] |
355 |
1 |
|
T16 |
2 |
|
T18 |
11 |
|
T200 |
1 |
| false |
118 |
1 |
|
T18 |
6 |
|
T210 |
1 |
|
T51 |
1 |
| true |
5741 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1196 |
1 |
|
T4 |
22 |
|
T16 |
1 |
|
T6 |
13 |
| others[1] |
1290 |
1 |
|
T4 |
12 |
|
T6 |
26 |
|
T8 |
1 |
| others[2] |
1260 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
15 |
| others[3] |
2028 |
1 |
|
T4 |
28 |
|
T6 |
34 |
|
T57 |
23 |
| false |
641 |
1 |
|
T4 |
8 |
|
T16 |
1 |
|
T6 |
11 |
| true |
449 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T56 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T4 |
21 |
|
T16 |
1 |
|
T6 |
13 |
| others[1] |
1258 |
1 |
|
T4 |
18 |
|
T6 |
20 |
|
T57 |
19 |
| others[2] |
1222 |
1 |
|
T4 |
13 |
|
T16 |
1 |
|
T6 |
18 |
| others[3] |
2099 |
1 |
|
T2 |
1 |
|
T4 |
25 |
|
T6 |
40 |
| false |
648 |
1 |
|
T4 |
8 |
|
T6 |
9 |
|
T57 |
6 |
| true |
433 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T18 |
4 |
|
T253 |
1 |
|
T99 |
9 |
| others[1] |
102 |
1 |
|
T18 |
1 |
|
T210 |
1 |
|
T211 |
1 |
| others[2] |
103 |
1 |
|
T16 |
2 |
|
T18 |
3 |
|
T211 |
1 |
| others[3] |
154 |
1 |
|
T18 |
3 |
|
T200 |
1 |
|
T210 |
1 |
| false |
50 |
1 |
|
T18 |
1 |
|
T44 |
1 |
|
T99 |
1 |
| true |
6347 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T16 |
1 |
|
T18 |
12 |
|
T23 |
1 |
| others[1] |
253 |
1 |
|
T16 |
1 |
|
T18 |
14 |
|
T32 |
1 |
| others[2] |
241 |
1 |
|
T18 |
6 |
|
T211 |
1 |
|
T123 |
1 |
| others[3] |
389 |
1 |
|
T8 |
1 |
|
T7 |
1 |
|
T18 |
17 |
| false |
109 |
1 |
|
T56 |
1 |
|
T19 |
1 |
|
T18 |
5 |
| true |
5625 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1044 |
1 |
|
T2 |
1 |
|
T4 |
22 |
|
T5 |
1 |
| others[1] |
1046 |
1 |
|
T4 |
17 |
|
T16 |
1 |
|
T6 |
9 |
| others[2] |
1062 |
1 |
|
T4 |
17 |
|
T6 |
10 |
|
T57 |
16 |
| others[3] |
1775 |
1 |
|
T1 |
1 |
|
T4 |
21 |
|
T6 |
16 |
| false |
565 |
1 |
|
T4 |
8 |
|
T16 |
1 |
|
T6 |
6 |
| true |
1372 |
1 |
|
T6 |
51 |
|
T7 |
1 |
|
T56 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T18 |
12 |
|
T211 |
1 |
|
T253 |
1 |
| others[1] |
217 |
1 |
|
T18 |
17 |
|
T239 |
1 |
|
T24 |
1 |
| others[2] |
234 |
1 |
|
T16 |
1 |
|
T19 |
1 |
|
T18 |
5 |
| others[3] |
398 |
1 |
|
T8 |
1 |
|
T7 |
1 |
|
T18 |
10 |
| false |
134 |
1 |
|
T18 |
2 |
|
T210 |
1 |
|
T51 |
1 |
| true |
5663 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T18 |
9 |
|
T211 |
1 |
|
T51 |
1 |
| others[1] |
236 |
1 |
|
T18 |
15 |
|
T51 |
1 |
|
T99 |
7 |
| others[2] |
235 |
1 |
|
T18 |
8 |
|
T99 |
10 |
|
T395 |
1 |
| others[3] |
340 |
1 |
|
T18 |
5 |
|
T122 |
1 |
|
T51 |
1 |
| false |
111 |
1 |
|
T18 |
7 |
|
T200 |
1 |
|
T253 |
1 |
| true |
5726 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1283 |
1 |
|
T2 |
1 |
|
T4 |
18 |
|
T16 |
1 |
| others[1] |
1239 |
1 |
|
T4 |
16 |
|
T6 |
20 |
|
T57 |
10 |
| others[2] |
1207 |
1 |
|
T4 |
13 |
|
T6 |
20 |
|
T57 |
14 |
| others[3] |
2094 |
1 |
|
T4 |
28 |
|
T16 |
1 |
|
T6 |
38 |
| false |
611 |
1 |
|
T4 |
10 |
|
T6 |
10 |
|
T57 |
7 |
| true |
430 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T4 |
21 |
|
T6 |
19 |
|
T57 |
14 |
| others[1] |
1208 |
1 |
|
T4 |
17 |
|
T6 |
15 |
|
T57 |
19 |
| others[2] |
1252 |
1 |
|
T2 |
1 |
|
T4 |
18 |
|
T16 |
1 |
| others[3] |
2060 |
1 |
|
T4 |
23 |
|
T16 |
1 |
|
T6 |
32 |
| false |
679 |
1 |
|
T4 |
6 |
|
T6 |
10 |
|
T57 |
7 |
| true |
425 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T16 |
1 |
|
T18 |
5 |
|
T200 |
1 |
| others[1] |
115 |
1 |
|
T18 |
4 |
|
T99 |
5 |
|
T61 |
4 |
| others[2] |
94 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T122 |
2 |
| others[3] |
178 |
1 |
|
T18 |
10 |
|
T44 |
1 |
|
T210 |
1 |
| false |
52 |
1 |
|
T18 |
2 |
|
T332 |
1 |
|
T99 |
4 |
| true |
6319 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T8 |
1 |
|
T18 |
7 |
|
T51 |
1 |
| others[1] |
256 |
1 |
|
T5 |
1 |
|
T18 |
8 |
|
T125 |
1 |
| others[2] |
225 |
1 |
|
T16 |
1 |
|
T18 |
5 |
|
T211 |
1 |
| others[3] |
360 |
1 |
|
T18 |
11 |
|
T210 |
1 |
|
T24 |
1 |
| false |
119 |
1 |
|
T18 |
5 |
|
T332 |
1 |
|
T99 |
5 |
| true |
5675 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1061 |
1 |
|
T2 |
1 |
|
T4 |
14 |
|
T6 |
7 |
| others[1] |
1001 |
1 |
|
T4 |
23 |
|
T16 |
1 |
|
T6 |
14 |
| others[2] |
1038 |
1 |
|
T4 |
21 |
|
T6 |
10 |
|
T57 |
14 |
| others[3] |
1785 |
1 |
|
T4 |
17 |
|
T16 |
1 |
|
T6 |
18 |
| false |
551 |
1 |
|
T4 |
10 |
|
T6 |
4 |
|
T57 |
10 |
| true |
1428 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T18 |
12 |
|
T32 |
1 |
|
T239 |
1 |
| others[1] |
198 |
1 |
|
T18 |
7 |
|
T33 |
1 |
|
T51 |
1 |
| others[2] |
233 |
1 |
|
T16 |
1 |
|
T18 |
8 |
|
T211 |
2 |
| others[3] |
371 |
1 |
|
T18 |
19 |
|
T253 |
1 |
|
T51 |
1 |
| false |
127 |
1 |
|
T18 |
5 |
|
T210 |
1 |
|
T99 |
10 |
| true |
5704 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T18 |
7 |
|
T200 |
1 |
|
T253 |
1 |
| others[1] |
232 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T211 |
1 |
| others[2] |
228 |
1 |
|
T18 |
15 |
|
T32 |
1 |
|
T210 |
1 |
| others[3] |
356 |
1 |
|
T16 |
1 |
|
T18 |
10 |
|
T33 |
1 |
| false |
127 |
1 |
|
T18 |
7 |
|
T193 |
1 |
|
T99 |
6 |
| true |
5719 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T4 |
13 |
|
T16 |
1 |
|
T6 |
24 |
| others[1] |
1259 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T6 |
17 |
| others[2] |
1257 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T6 |
21 |
| others[3] |
2015 |
1 |
|
T4 |
32 |
|
T6 |
30 |
|
T57 |
30 |
| false |
642 |
1 |
|
T4 |
10 |
|
T6 |
8 |
|
T59 |
1 |
| true |
432 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T2 |
1 |
|
T4 |
12 |
|
T6 |
13 |
| others[1] |
1293 |
1 |
|
T4 |
17 |
|
T6 |
22 |
|
T57 |
14 |
| others[2] |
1257 |
1 |
|
T4 |
20 |
|
T6 |
21 |
|
T57 |
15 |
| others[3] |
2051 |
1 |
|
T4 |
28 |
|
T16 |
2 |
|
T6 |
37 |
| false |
609 |
1 |
|
T4 |
8 |
|
T6 |
7 |
|
T57 |
7 |
| true |
435 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T18 |
4 |
|
T200 |
1 |
|
T210 |
2 |
| others[1] |
105 |
1 |
|
T18 |
3 |
|
T211 |
1 |
|
T122 |
1 |
| others[2] |
87 |
1 |
|
T16 |
1 |
|
T18 |
4 |
|
T253 |
1 |
| others[3] |
168 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T44 |
1 |
| false |
64 |
1 |
|
T18 |
2 |
|
T211 |
1 |
|
T253 |
1 |
| true |
6334 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
294 |
1 |
|
T18 |
10 |
|
T200 |
1 |
|
T253 |
1 |
| others[1] |
240 |
1 |
|
T7 |
1 |
|
T18 |
8 |
|
T99 |
14 |
| others[2] |
234 |
1 |
|
T18 |
6 |
|
T211 |
1 |
|
T122 |
1 |
| others[3] |
385 |
1 |
|
T5 |
1 |
|
T16 |
2 |
|
T8 |
1 |
| false |
120 |
1 |
|
T18 |
5 |
|
T253 |
1 |
|
T122 |
1 |
| true |
5591 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1110 |
1 |
|
T4 |
16 |
|
T6 |
6 |
|
T56 |
1 |
| others[1] |
1004 |
1 |
|
T4 |
19 |
|
T5 |
1 |
|
T6 |
8 |
| others[2] |
1048 |
1 |
|
T4 |
15 |
|
T16 |
1 |
|
T6 |
10 |
| others[3] |
1822 |
1 |
|
T2 |
1 |
|
T4 |
27 |
|
T16 |
1 |
| false |
532 |
1 |
|
T4 |
8 |
|
T6 |
6 |
|
T57 |
6 |
| true |
1348 |
1 |
|
T1 |
1 |
|
T6 |
50 |
|
T59 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T18 |
7 |
|
T211 |
1 |
|
T51 |
1 |
| others[1] |
198 |
1 |
|
T18 |
10 |
|
T44 |
1 |
|
T200 |
1 |
| others[2] |
215 |
1 |
|
T19 |
1 |
|
T18 |
9 |
|
T210 |
1 |
| others[3] |
397 |
1 |
|
T16 |
1 |
|
T56 |
1 |
|
T18 |
18 |
| false |
139 |
1 |
|
T18 |
9 |
|
T250 |
1 |
|
T99 |
6 |
| true |
5683 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T18 |
9 |
|
T253 |
1 |
|
T99 |
12 |
| others[1] |
223 |
1 |
|
T16 |
1 |
|
T18 |
7 |
|
T211 |
1 |
| others[2] |
242 |
1 |
|
T18 |
12 |
|
T51 |
1 |
|
T193 |
1 |
| others[3] |
366 |
1 |
|
T18 |
14 |
|
T44 |
1 |
|
T210 |
1 |
| false |
101 |
1 |
|
T16 |
1 |
|
T18 |
4 |
|
T51 |
1 |
| true |
5714 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T4 |
18 |
|
T6 |
12 |
|
T57 |
17 |
| others[1] |
1220 |
1 |
|
T4 |
17 |
|
T6 |
23 |
|
T57 |
9 |
| others[2] |
1229 |
1 |
|
T2 |
1 |
|
T4 |
13 |
|
T6 |
17 |
| others[3] |
2115 |
1 |
|
T4 |
30 |
|
T16 |
2 |
|
T6 |
35 |
| false |
615 |
1 |
|
T4 |
7 |
|
T6 |
13 |
|
T57 |
7 |
| true |
445 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1166 |
1 |
|
T4 |
13 |
|
T16 |
2 |
|
T6 |
24 |
| others[1] |
1228 |
1 |
|
T4 |
22 |
|
T6 |
19 |
|
T57 |
18 |
| others[2] |
1262 |
1 |
|
T2 |
1 |
|
T4 |
8 |
|
T6 |
17 |
| others[3] |
2151 |
1 |
|
T4 |
31 |
|
T6 |
26 |
|
T57 |
26 |
| false |
633 |
1 |
|
T4 |
11 |
|
T6 |
14 |
|
T57 |
3 |
| true |
424 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T16 |
1 |
|
T18 |
3 |
|
T44 |
1 |
| others[1] |
94 |
1 |
|
T18 |
3 |
|
T200 |
1 |
|
T210 |
1 |
| others[2] |
88 |
1 |
|
T18 |
4 |
|
T210 |
1 |
|
T122 |
1 |
| others[3] |
166 |
1 |
|
T16 |
1 |
|
T18 |
2 |
|
T122 |
1 |
| false |
50 |
1 |
|
T18 |
2 |
|
T332 |
1 |
|
T253 |
1 |
| true |
6365 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T18 |
15 |
|
T21 |
1 |
|
T51 |
1 |
| others[1] |
234 |
1 |
|
T8 |
1 |
|
T56 |
1 |
|
T18 |
11 |
| others[2] |
247 |
1 |
|
T16 |
1 |
|
T18 |
11 |
|
T99 |
9 |
| others[3] |
376 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T18 |
16 |
| false |
97 |
1 |
|
T18 |
5 |
|
T99 |
9 |
|
T217 |
1 |
| true |
5677 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |