Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1059 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T6 |
14 |
| others[1] |
1060 |
1 |
|
T4 |
19 |
|
T6 |
10 |
|
T57 |
13 |
| others[2] |
1040 |
1 |
|
T1 |
1 |
|
T4 |
17 |
|
T6 |
13 |
| others[3] |
1807 |
1 |
|
T4 |
29 |
|
T16 |
1 |
|
T6 |
17 |
| false |
547 |
1 |
|
T4 |
5 |
|
T16 |
1 |
|
T6 |
3 |
| true |
1351 |
1 |
|
T5 |
1 |
|
T6 |
43 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T18 |
11 |
|
T193 |
1 |
|
T99 |
9 |
| others[1] |
216 |
1 |
|
T5 |
1 |
|
T56 |
1 |
|
T18 |
8 |
| others[2] |
226 |
1 |
|
T18 |
12 |
|
T210 |
2 |
|
T51 |
1 |
| others[3] |
390 |
1 |
|
T16 |
2 |
|
T8 |
1 |
|
T7 |
1 |
| false |
124 |
1 |
|
T18 |
7 |
|
T253 |
1 |
|
T99 |
5 |
| true |
5671 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T18 |
11 |
|
T33 |
1 |
|
T51 |
1 |
| others[1] |
218 |
1 |
|
T18 |
9 |
|
T44 |
1 |
|
T210 |
1 |
| others[2] |
202 |
1 |
|
T18 |
8 |
|
T127 |
1 |
|
T99 |
10 |
| others[3] |
353 |
1 |
|
T18 |
16 |
|
T253 |
1 |
|
T122 |
1 |
| false |
125 |
1 |
|
T18 |
5 |
|
T193 |
1 |
|
T99 |
4 |
| true |
5746 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T6 |
25 |
| others[1] |
1216 |
1 |
|
T4 |
21 |
|
T6 |
18 |
|
T57 |
12 |
| others[2] |
1245 |
1 |
|
T2 |
1 |
|
T4 |
16 |
|
T6 |
19 |
| others[3] |
2077 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T6 |
26 |
| false |
660 |
1 |
|
T4 |
12 |
|
T6 |
12 |
|
T57 |
10 |
| true |
448 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1272 |
1 |
|
T4 |
17 |
|
T6 |
31 |
|
T57 |
10 |
| others[1] |
1234 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T6 |
16 |
| others[2] |
1220 |
1 |
|
T2 |
1 |
|
T4 |
18 |
|
T6 |
17 |
| others[3] |
2039 |
1 |
|
T4 |
28 |
|
T16 |
1 |
|
T6 |
29 |
| false |
667 |
1 |
|
T4 |
3 |
|
T6 |
7 |
|
T57 |
9 |
| true |
432 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T18 |
2 |
|
T211 |
1 |
|
T122 |
1 |
| others[1] |
115 |
1 |
|
T18 |
3 |
|
T44 |
1 |
|
T210 |
1 |
| others[2] |
95 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T253 |
1 |
| others[3] |
156 |
1 |
|
T16 |
1 |
|
T18 |
2 |
|
T200 |
1 |
| false |
40 |
1 |
|
T18 |
2 |
|
T99 |
3 |
|
T61 |
1 |
| true |
6348 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T18 |
12 |
|
T253 |
1 |
|
T122 |
1 |
| others[1] |
240 |
1 |
|
T18 |
14 |
|
T23 |
1 |
|
T211 |
1 |
| others[2] |
241 |
1 |
|
T18 |
11 |
|
T332 |
1 |
|
T127 |
1 |
| others[3] |
388 |
1 |
|
T7 |
1 |
|
T56 |
1 |
|
T18 |
14 |
| false |
142 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T18 |
3 |
| true |
5627 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1056 |
1 |
|
T4 |
14 |
|
T16 |
1 |
|
T6 |
8 |
| others[1] |
1055 |
1 |
|
T4 |
18 |
|
T6 |
14 |
|
T8 |
1 |
| others[2] |
998 |
1 |
|
T4 |
15 |
|
T6 |
8 |
|
T7 |
1 |
| others[3] |
1840 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
32 |
| false |
558 |
1 |
|
T4 |
6 |
|
T16 |
1 |
|
T6 |
4 |
| true |
1357 |
1 |
|
T5 |
1 |
|
T6 |
50 |
|
T56 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T19 |
1 |
|
T18 |
11 |
|
T51 |
1 |
| others[1] |
211 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T18 |
7 |
| others[2] |
211 |
1 |
|
T18 |
14 |
|
T122 |
1 |
|
T99 |
13 |
| others[3] |
395 |
1 |
|
T18 |
24 |
|
T99 |
14 |
|
T60 |
1 |
| false |
128 |
1 |
|
T18 |
3 |
|
T33 |
1 |
|
T99 |
3 |
| true |
5690 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T18 |
9 |
|
T200 |
1 |
|
T210 |
1 |
| others[1] |
203 |
1 |
|
T16 |
1 |
|
T18 |
11 |
|
T122 |
1 |
| others[2] |
211 |
1 |
|
T18 |
10 |
|
T32 |
1 |
|
T44 |
1 |
| others[3] |
383 |
1 |
|
T18 |
21 |
|
T253 |
2 |
|
T125 |
1 |
| false |
123 |
1 |
|
T18 |
5 |
|
T51 |
1 |
|
T99 |
7 |
| true |
5726 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T2 |
1 |
|
T4 |
19 |
|
T6 |
16 |
| others[1] |
1270 |
1 |
|
T4 |
14 |
|
T16 |
1 |
|
T6 |
19 |
| others[2] |
1252 |
1 |
|
T4 |
20 |
|
T16 |
1 |
|
T6 |
15 |
| others[3] |
2014 |
1 |
|
T4 |
22 |
|
T6 |
37 |
|
T57 |
28 |
| false |
666 |
1 |
|
T4 |
10 |
|
T6 |
13 |
|
T57 |
8 |
| true |
436 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T4 |
21 |
|
T6 |
25 |
|
T57 |
19 |
| others[1] |
1291 |
1 |
|
T4 |
16 |
|
T16 |
1 |
|
T6 |
19 |
| others[2] |
1207 |
1 |
|
T4 |
13 |
|
T16 |
1 |
|
T6 |
24 |
| others[3] |
2048 |
1 |
|
T2 |
1 |
|
T4 |
29 |
|
T6 |
28 |
| false |
629 |
1 |
|
T4 |
6 |
|
T6 |
4 |
|
T57 |
6 |
| true |
433 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T18 |
5 |
|
T210 |
2 |
|
T253 |
1 |
| others[1] |
112 |
1 |
|
T18 |
6 |
|
T44 |
1 |
|
T211 |
1 |
| others[2] |
99 |
1 |
|
T18 |
6 |
|
T200 |
1 |
|
T211 |
1 |
| others[3] |
169 |
1 |
|
T16 |
1 |
|
T18 |
5 |
|
T32 |
1 |
| false |
61 |
1 |
|
T16 |
1 |
|
T18 |
4 |
|
T253 |
1 |
| true |
6313 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T7 |
1 |
|
T18 |
14 |
|
T99 |
9 |
| others[1] |
208 |
1 |
|
T16 |
1 |
|
T18 |
12 |
|
T239 |
1 |
| others[2] |
241 |
1 |
|
T18 |
4 |
|
T44 |
1 |
|
T33 |
1 |
| others[3] |
423 |
1 |
|
T18 |
13 |
|
T21 |
1 |
|
T210 |
1 |
| false |
119 |
1 |
|
T18 |
2 |
|
T332 |
1 |
|
T123 |
1 |
| true |
5619 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
993 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T6 |
18 |
| others[1] |
1015 |
1 |
|
T4 |
16 |
|
T6 |
9 |
|
T57 |
15 |
| others[2] |
1067 |
1 |
|
T4 |
20 |
|
T6 |
11 |
|
T8 |
1 |
| others[3] |
1847 |
1 |
|
T2 |
1 |
|
T4 |
21 |
|
T16 |
1 |
| false |
531 |
1 |
|
T4 |
9 |
|
T6 |
3 |
|
T59 |
1 |
| true |
1411 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
42 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T8 |
1 |
|
T18 |
7 |
|
T253 |
1 |
| others[1] |
220 |
1 |
|
T16 |
1 |
|
T18 |
5 |
|
T250 |
1 |
| others[2] |
220 |
1 |
|
T18 |
10 |
|
T32 |
1 |
|
T44 |
1 |
| others[3] |
382 |
1 |
|
T7 |
1 |
|
T18 |
22 |
|
T210 |
1 |
| false |
133 |
1 |
|
T18 |
6 |
|
T211 |
1 |
|
T99 |
7 |
| true |
5686 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T18 |
15 |
|
T32 |
1 |
|
T51 |
2 |
| others[1] |
224 |
1 |
|
T16 |
1 |
|
T18 |
12 |
|
T44 |
1 |
| others[2] |
237 |
1 |
|
T18 |
10 |
|
T210 |
1 |
|
T211 |
1 |
| others[3] |
384 |
1 |
|
T18 |
15 |
|
T51 |
1 |
|
T99 |
21 |
| false |
119 |
1 |
|
T16 |
1 |
|
T18 |
4 |
|
T99 |
2 |
| true |
5680 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1300 |
1 |
|
T4 |
13 |
|
T6 |
26 |
|
T59 |
1 |
| others[1] |
1217 |
1 |
|
T4 |
10 |
|
T6 |
13 |
|
T57 |
13 |
| others[2] |
1196 |
1 |
|
T2 |
1 |
|
T4 |
23 |
|
T16 |
1 |
| others[3] |
2075 |
1 |
|
T4 |
26 |
|
T16 |
1 |
|
T6 |
31 |
| false |
633 |
1 |
|
T4 |
13 |
|
T6 |
12 |
|
T57 |
6 |
| true |
443 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1172 |
1 |
|
T4 |
18 |
|
T6 |
22 |
|
T57 |
9 |
| others[1] |
1246 |
1 |
|
T2 |
1 |
|
T4 |
12 |
|
T6 |
20 |
| others[2] |
1292 |
1 |
|
T4 |
18 |
|
T6 |
9 |
|
T57 |
20 |
| others[3] |
2086 |
1 |
|
T4 |
28 |
|
T6 |
40 |
|
T8 |
1 |
| false |
654 |
1 |
|
T4 |
9 |
|
T16 |
2 |
|
T6 |
9 |
| true |
414 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T18 |
3 |
|
T44 |
1 |
|
T211 |
1 |
| others[1] |
101 |
1 |
|
T18 |
5 |
|
T200 |
1 |
|
T253 |
1 |
| others[2] |
91 |
1 |
|
T18 |
5 |
|
T211 |
1 |
|
T253 |
1 |
| others[3] |
168 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T210 |
2 |
| false |
61 |
1 |
|
T16 |
1 |
|
T18 |
2 |
|
T33 |
1 |
| true |
6340 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T7 |
1 |
|
T18 |
9 |
|
T24 |
1 |
| others[1] |
240 |
1 |
|
T16 |
1 |
|
T18 |
12 |
|
T22 |
1 |
| others[2] |
234 |
1 |
|
T18 |
11 |
|
T253 |
1 |
|
T99 |
7 |
| others[3] |
395 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T19 |
1 |
| false |
129 |
1 |
|
T18 |
6 |
|
T21 |
1 |
|
T33 |
1 |
| true |
5625 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1068 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T6 |
12 |
| others[1] |
1062 |
1 |
|
T4 |
18 |
|
T6 |
9 |
|
T57 |
13 |
| others[2] |
1049 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T6 |
8 |
| others[3] |
1785 |
1 |
|
T4 |
29 |
|
T5 |
1 |
|
T16 |
1 |
| false |
535 |
1 |
|
T4 |
3 |
|
T6 |
5 |
|
T57 |
4 |
| true |
1365 |
1 |
|
T1 |
1 |
|
T6 |
54 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T18 |
15 |
|
T23 |
1 |
|
T51 |
1 |
| others[1] |
228 |
1 |
|
T18 |
7 |
|
T33 |
1 |
|
T122 |
1 |
| others[2] |
220 |
1 |
|
T56 |
1 |
|
T18 |
8 |
|
T211 |
1 |
| others[3] |
361 |
1 |
|
T18 |
16 |
|
T210 |
1 |
|
T211 |
1 |
| false |
116 |
1 |
|
T5 |
1 |
|
T18 |
3 |
|
T210 |
1 |
| true |
5695 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T16 |
1 |
|
T18 |
11 |
|
T32 |
1 |
| others[1] |
229 |
1 |
|
T18 |
19 |
|
T332 |
1 |
|
T253 |
1 |
| others[2] |
233 |
1 |
|
T18 |
5 |
|
T99 |
9 |
|
T61 |
6 |
| others[3] |
353 |
1 |
|
T18 |
16 |
|
T210 |
1 |
|
T51 |
1 |
| false |
105 |
1 |
|
T18 |
5 |
|
T99 |
4 |
|
T61 |
4 |
| true |
5714 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T4 |
19 |
|
T6 |
18 |
|
T57 |
7 |
| others[1] |
1205 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T16 |
1 |
| others[2] |
1248 |
1 |
|
T4 |
16 |
|
T6 |
19 |
|
T57 |
18 |
| others[3] |
2051 |
1 |
|
T4 |
25 |
|
T6 |
33 |
|
T57 |
20 |
| false |
660 |
1 |
|
T4 |
10 |
|
T16 |
1 |
|
T6 |
10 |
| true |
441 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1282 |
1 |
|
T4 |
10 |
|
T6 |
16 |
|
T57 |
16 |
| others[1] |
1235 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T6 |
14 |
| others[2] |
1243 |
1 |
|
T4 |
23 |
|
T16 |
1 |
|
T6 |
27 |
| others[3] |
2018 |
1 |
|
T4 |
28 |
|
T16 |
1 |
|
T6 |
25 |
| false |
667 |
1 |
|
T4 |
9 |
|
T6 |
18 |
|
T57 |
6 |
| true |
419 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T18 |
3 |
|
T210 |
2 |
|
T99 |
2 |
| others[1] |
92 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T44 |
1 |
| others[2] |
96 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T211 |
2 |
| others[3] |
175 |
1 |
|
T18 |
8 |
|
T253 |
2 |
|
T122 |
2 |
| false |
50 |
1 |
|
T99 |
3 |
|
T61 |
2 |
|
T112 |
1 |
| true |
6351 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T19 |
1 |
| others[1] |
246 |
1 |
|
T8 |
1 |
|
T7 |
1 |
|
T18 |
7 |
| others[2] |
235 |
1 |
|
T18 |
7 |
|
T24 |
1 |
|
T211 |
1 |
| others[3] |
416 |
1 |
|
T18 |
14 |
|
T200 |
1 |
|
T253 |
1 |
| false |
130 |
1 |
|
T18 |
6 |
|
T239 |
1 |
|
T99 |
2 |
| true |
5617 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1042 |
1 |
|
T2 |
1 |
|
T4 |
18 |
|
T6 |
13 |
| others[1] |
1031 |
1 |
|
T4 |
15 |
|
T16 |
1 |
|
T6 |
10 |
| others[2] |
1082 |
1 |
|
T4 |
15 |
|
T16 |
1 |
|
T6 |
10 |
| others[3] |
1772 |
1 |
|
T4 |
29 |
|
T6 |
12 |
|
T56 |
1 |
| false |
574 |
1 |
|
T4 |
8 |
|
T6 |
7 |
|
T57 |
7 |
| true |
1363 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T8 |
1 |
|
T7 |
1 |
|
T18 |
11 |
| others[1] |
213 |
1 |
|
T18 |
8 |
|
T211 |
1 |
|
T99 |
9 |
| others[2] |
246 |
1 |
|
T19 |
1 |
|
T18 |
8 |
|
T239 |
1 |
| others[3] |
375 |
1 |
|
T5 |
1 |
|
T56 |
1 |
|
T18 |
16 |
| false |
124 |
1 |
|
T18 |
4 |
|
T99 |
2 |
|
T61 |
10 |
| true |
5678 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T18 |
8 |
|
T99 |
11 |
|
T61 |
6 |
| others[1] |
239 |
1 |
|
T18 |
13 |
|
T210 |
1 |
|
T125 |
1 |
| others[2] |
230 |
1 |
|
T16 |
1 |
|
T18 |
14 |
|
T332 |
1 |
| others[3] |
362 |
1 |
|
T16 |
1 |
|
T18 |
13 |
|
T200 |
1 |
| false |
116 |
1 |
|
T18 |
3 |
|
T33 |
1 |
|
T99 |
2 |
| true |
5691 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |