Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T4 |
13 |
|
T16 |
1 |
|
T6 |
20 |
| others[1] |
1309 |
1 |
|
T4 |
14 |
|
T6 |
23 |
|
T57 |
13 |
| others[2] |
1224 |
1 |
|
T4 |
15 |
|
T6 |
20 |
|
T57 |
7 |
| others[3] |
2018 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
30 |
| false |
643 |
1 |
|
T4 |
13 |
|
T6 |
10 |
|
T57 |
9 |
| true |
440 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T4 |
17 |
|
T16 |
1 |
|
T6 |
23 |
| others[1] |
1232 |
1 |
|
T4 |
14 |
|
T6 |
12 |
|
T57 |
14 |
| others[2] |
1256 |
1 |
|
T4 |
16 |
|
T16 |
1 |
|
T6 |
17 |
| others[3] |
2037 |
1 |
|
T2 |
1 |
|
T4 |
29 |
|
T6 |
35 |
| false |
660 |
1 |
|
T4 |
9 |
|
T6 |
13 |
|
T57 |
5 |
| true |
425 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T18 |
4 |
|
T122 |
1 |
|
T99 |
6 |
| others[1] |
120 |
1 |
|
T18 |
3 |
|
T210 |
1 |
|
T211 |
1 |
| others[2] |
112 |
1 |
|
T18 |
3 |
|
T200 |
1 |
|
T210 |
1 |
| others[3] |
150 |
1 |
|
T16 |
2 |
|
T18 |
7 |
|
T32 |
1 |
| false |
50 |
1 |
|
T18 |
4 |
|
T332 |
1 |
|
T99 |
1 |
| true |
6328 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T18 |
11 |
|
T32 |
1 |
|
T44 |
1 |
| others[1] |
212 |
1 |
|
T16 |
1 |
|
T18 |
7 |
|
T193 |
1 |
| others[2] |
231 |
1 |
|
T8 |
1 |
|
T18 |
9 |
|
T24 |
1 |
| others[3] |
375 |
1 |
|
T7 |
1 |
|
T18 |
14 |
|
T33 |
1 |
| false |
131 |
1 |
|
T18 |
7 |
|
T122 |
1 |
|
T125 |
1 |
| true |
5688 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1023 |
1 |
|
T4 |
15 |
|
T6 |
8 |
|
T57 |
11 |
| others[1] |
1087 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T6 |
11 |
| others[2] |
1062 |
1 |
|
T4 |
14 |
|
T6 |
9 |
|
T57 |
12 |
| others[3] |
1783 |
1 |
|
T2 |
1 |
|
T4 |
30 |
|
T16 |
1 |
| false |
534 |
1 |
|
T4 |
7 |
|
T6 |
7 |
|
T57 |
5 |
| true |
1375 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
53 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T19 |
1 |
|
T18 |
12 |
|
T122 |
1 |
| others[1] |
207 |
1 |
|
T16 |
1 |
|
T18 |
7 |
|
T99 |
5 |
| others[2] |
231 |
1 |
|
T8 |
1 |
|
T18 |
9 |
|
T211 |
1 |
| others[3] |
415 |
1 |
|
T7 |
1 |
|
T18 |
13 |
|
T239 |
1 |
| false |
111 |
1 |
|
T18 |
5 |
|
T32 |
1 |
|
T99 |
3 |
| true |
5667 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T16 |
1 |
|
T18 |
8 |
|
T99 |
5 |
| others[1] |
209 |
1 |
|
T18 |
12 |
|
T211 |
1 |
|
T253 |
1 |
| others[2] |
226 |
1 |
|
T18 |
8 |
|
T99 |
5 |
|
T61 |
15 |
| others[3] |
388 |
1 |
|
T18 |
19 |
|
T32 |
1 |
|
T211 |
1 |
| false |
103 |
1 |
|
T18 |
3 |
|
T210 |
2 |
|
T253 |
1 |
| true |
5714 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T4 |
23 |
|
T16 |
1 |
|
T6 |
20 |
| others[1] |
1251 |
1 |
|
T2 |
1 |
|
T4 |
12 |
|
T6 |
16 |
| others[2] |
1206 |
1 |
|
T1 |
1 |
|
T4 |
15 |
|
T6 |
15 |
| others[3] |
2071 |
1 |
|
T4 |
27 |
|
T16 |
1 |
|
T6 |
37 |
| false |
640 |
1 |
|
T4 |
8 |
|
T6 |
12 |
|
T57 |
10 |
| true |
461 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T2 |
1 |
|
T4 |
14 |
|
T16 |
1 |
| others[1] |
1266 |
1 |
|
T4 |
21 |
|
T6 |
22 |
|
T57 |
17 |
| others[2] |
1223 |
1 |
|
T4 |
15 |
|
T16 |
1 |
|
T6 |
16 |
| others[3] |
2110 |
1 |
|
T4 |
22 |
|
T6 |
33 |
|
T57 |
26 |
| false |
618 |
1 |
|
T4 |
13 |
|
T6 |
7 |
|
T57 |
6 |
| true |
429 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T18 |
2 |
|
T332 |
1 |
|
T99 |
6 |
| others[1] |
108 |
1 |
|
T18 |
4 |
|
T253 |
2 |
|
T122 |
1 |
| others[2] |
102 |
1 |
|
T18 |
6 |
|
T44 |
1 |
|
T99 |
7 |
| others[3] |
182 |
1 |
|
T16 |
1 |
|
T18 |
5 |
|
T200 |
1 |
| false |
56 |
1 |
|
T16 |
1 |
|
T18 |
5 |
|
T211 |
1 |
| true |
6324 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T18 |
7 |
|
T211 |
1 |
|
T332 |
1 |
| others[1] |
235 |
1 |
|
T5 |
1 |
|
T16 |
2 |
|
T7 |
1 |
| others[2] |
238 |
1 |
|
T8 |
1 |
|
T18 |
7 |
|
T253 |
1 |
| others[3] |
385 |
1 |
|
T18 |
14 |
|
T21 |
1 |
|
T200 |
1 |
| false |
125 |
1 |
|
T18 |
9 |
|
T123 |
1 |
|
T51 |
1 |
| true |
5626 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1085 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
17 |
| others[1] |
1065 |
1 |
|
T4 |
12 |
|
T6 |
10 |
|
T8 |
1 |
| others[2] |
1049 |
1 |
|
T4 |
18 |
|
T5 |
1 |
|
T6 |
7 |
| others[3] |
1741 |
1 |
|
T4 |
26 |
|
T16 |
1 |
|
T6 |
19 |
| false |
557 |
1 |
|
T4 |
12 |
|
T6 |
7 |
|
T57 |
5 |
| true |
1367 |
1 |
|
T6 |
49 |
|
T59 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T19 |
1 |
|
T18 |
10 |
|
T33 |
1 |
| others[1] |
220 |
1 |
|
T18 |
8 |
|
T200 |
1 |
|
T125 |
1 |
| others[2] |
258 |
1 |
|
T16 |
1 |
|
T8 |
1 |
|
T18 |
12 |
| others[3] |
342 |
1 |
|
T18 |
17 |
|
T210 |
1 |
|
T24 |
1 |
| false |
114 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T99 |
6 |
| true |
5694 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T16 |
1 |
|
T18 |
7 |
|
T51 |
2 |
| others[1] |
238 |
1 |
|
T18 |
9 |
|
T210 |
1 |
|
T211 |
1 |
| others[2] |
237 |
1 |
|
T18 |
14 |
|
T210 |
1 |
|
T51 |
1 |
| others[3] |
361 |
1 |
|
T16 |
1 |
|
T18 |
18 |
|
T33 |
1 |
| false |
100 |
1 |
|
T18 |
2 |
|
T211 |
1 |
|
T99 |
5 |
| true |
5683 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1175 |
1 |
|
T2 |
1 |
|
T4 |
14 |
|
T6 |
12 |
| others[1] |
1224 |
1 |
|
T4 |
11 |
|
T6 |
22 |
|
T57 |
14 |
| others[2] |
1264 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T6 |
30 |
| others[3] |
2131 |
1 |
|
T4 |
33 |
|
T6 |
24 |
|
T57 |
19 |
| false |
629 |
1 |
|
T4 |
9 |
|
T16 |
1 |
|
T6 |
12 |
| true |
441 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1198 |
1 |
|
T4 |
15 |
|
T6 |
26 |
|
T57 |
13 |
| others[1] |
1229 |
1 |
|
T4 |
15 |
|
T6 |
13 |
|
T57 |
10 |
| others[2] |
1314 |
1 |
|
T2 |
1 |
|
T4 |
14 |
|
T6 |
19 |
| others[3] |
2073 |
1 |
|
T4 |
26 |
|
T16 |
2 |
|
T6 |
38 |
| false |
628 |
1 |
|
T4 |
15 |
|
T6 |
4 |
|
T57 |
6 |
| true |
422 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T18 |
3 |
|
T332 |
1 |
|
T253 |
1 |
| others[1] |
111 |
1 |
|
T18 |
3 |
|
T253 |
1 |
|
T99 |
3 |
| others[2] |
111 |
1 |
|
T16 |
1 |
|
T18 |
4 |
|
T44 |
1 |
| others[3] |
162 |
1 |
|
T16 |
1 |
|
T18 |
3 |
|
T200 |
1 |
| false |
53 |
1 |
|
T18 |
1 |
|
T211 |
1 |
|
T99 |
2 |
| true |
6328 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T18 |
13 |
|
T200 |
1 |
|
T127 |
1 |
| others[1] |
263 |
1 |
|
T18 |
12 |
|
T22 |
1 |
|
T51 |
1 |
| others[2] |
235 |
1 |
|
T18 |
10 |
|
T210 |
1 |
|
T253 |
1 |
| others[3] |
388 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T7 |
1 |
| false |
105 |
1 |
|
T18 |
4 |
|
T99 |
3 |
|
T52 |
1 |
| true |
5650 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1011 |
1 |
|
T4 |
17 |
|
T6 |
8 |
|
T57 |
14 |
| others[1] |
1012 |
1 |
|
T4 |
14 |
|
T6 |
7 |
|
T59 |
1 |
| others[2] |
1070 |
1 |
|
T1 |
1 |
|
T4 |
21 |
|
T6 |
15 |
| others[3] |
1836 |
1 |
|
T2 |
1 |
|
T4 |
29 |
|
T16 |
2 |
| false |
563 |
1 |
|
T4 |
4 |
|
T6 |
5 |
|
T57 |
5 |
| true |
1372 |
1 |
|
T5 |
1 |
|
T6 |
51 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T18 |
7 |
|
T239 |
1 |
|
T210 |
1 |
| others[1] |
208 |
1 |
|
T18 |
11 |
|
T51 |
2 |
|
T99 |
7 |
| others[2] |
234 |
1 |
|
T18 |
8 |
|
T122 |
1 |
|
T125 |
1 |
| others[3] |
364 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T19 |
1 |
| false |
123 |
1 |
|
T18 |
4 |
|
T99 |
8 |
|
T217 |
1 |
| true |
5714 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T18 |
6 |
|
T200 |
1 |
|
T211 |
1 |
| others[1] |
212 |
1 |
|
T18 |
11 |
|
T99 |
7 |
|
T61 |
6 |
| others[2] |
209 |
1 |
|
T18 |
7 |
|
T33 |
1 |
|
T99 |
11 |
| others[3] |
380 |
1 |
|
T18 |
15 |
|
T210 |
1 |
|
T211 |
1 |
| false |
130 |
1 |
|
T18 |
5 |
|
T99 |
1 |
|
T61 |
5 |
| true |
5723 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T4 |
13 |
|
T6 |
22 |
|
T57 |
17 |
| others[1] |
1267 |
1 |
|
T2 |
1 |
|
T4 |
17 |
|
T6 |
16 |
| others[2] |
1239 |
1 |
|
T4 |
11 |
|
T6 |
24 |
|
T57 |
9 |
| others[3] |
2035 |
1 |
|
T4 |
34 |
|
T6 |
28 |
|
T57 |
20 |
| false |
625 |
1 |
|
T4 |
10 |
|
T16 |
2 |
|
T6 |
10 |
| true |
447 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T4 |
9 |
|
T6 |
15 |
|
T57 |
9 |
| others[1] |
1180 |
1 |
|
T4 |
23 |
|
T16 |
1 |
|
T6 |
22 |
| others[2] |
1280 |
1 |
|
T4 |
13 |
|
T6 |
19 |
|
T57 |
11 |
| others[3] |
2062 |
1 |
|
T4 |
32 |
|
T16 |
1 |
|
T6 |
37 |
| false |
683 |
1 |
|
T2 |
1 |
|
T4 |
8 |
|
T6 |
7 |
| true |
435 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T16 |
1 |
|
T18 |
4 |
|
T99 |
4 |
| others[1] |
112 |
1 |
|
T18 |
2 |
|
T211 |
1 |
|
T253 |
1 |
| others[2] |
94 |
1 |
|
T16 |
1 |
|
T18 |
5 |
|
T211 |
1 |
| others[3] |
161 |
1 |
|
T18 |
7 |
|
T200 |
1 |
|
T210 |
1 |
| false |
49 |
1 |
|
T18 |
2 |
|
T44 |
1 |
|
T210 |
1 |
| true |
6342 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T56 |
1 |
|
T18 |
4 |
|
T51 |
1 |
| others[1] |
231 |
1 |
|
T16 |
1 |
|
T18 |
11 |
|
T239 |
1 |
| others[2] |
221 |
1 |
|
T7 |
1 |
|
T18 |
6 |
|
T33 |
1 |
| others[3] |
390 |
1 |
|
T19 |
1 |
|
T18 |
12 |
|
T210 |
1 |
| false |
128 |
1 |
|
T18 |
5 |
|
T211 |
1 |
|
T250 |
1 |
| true |
5676 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T2 |
1 |
|
T4 |
19 |
|
T16 |
1 |
| others[1] |
1038 |
1 |
|
T1 |
1 |
|
T4 |
21 |
|
T6 |
10 |
| others[2] |
1054 |
1 |
|
T4 |
16 |
|
T6 |
11 |
|
T57 |
15 |
| others[3] |
1772 |
1 |
|
T4 |
20 |
|
T16 |
1 |
|
T6 |
8 |
| false |
530 |
1 |
|
T4 |
9 |
|
T6 |
6 |
|
T57 |
3 |
| true |
1407 |
1 |
|
T5 |
1 |
|
T6 |
54 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T18 |
9 |
|
T32 |
1 |
|
T24 |
1 |
| others[1] |
228 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T56 |
1 |
| others[2] |
226 |
1 |
|
T19 |
1 |
|
T18 |
8 |
|
T332 |
1 |
| others[3] |
379 |
1 |
|
T18 |
13 |
|
T44 |
1 |
|
T239 |
1 |
| false |
115 |
1 |
|
T18 |
7 |
|
T99 |
4 |
|
T61 |
7 |
| true |
5679 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T18 |
6 |
|
T332 |
1 |
|
T51 |
2 |
| others[1] |
231 |
1 |
|
T18 |
8 |
|
T51 |
1 |
|
T99 |
5 |
| others[2] |
235 |
1 |
|
T16 |
1 |
|
T18 |
9 |
|
T253 |
1 |
| others[3] |
337 |
1 |
|
T16 |
1 |
|
T18 |
13 |
|
T32 |
1 |
| false |
103 |
1 |
|
T18 |
3 |
|
T99 |
5 |
|
T61 |
4 |
| true |
5748 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1202 |
1 |
|
T2 |
1 |
|
T4 |
18 |
|
T6 |
19 |
| others[1] |
1281 |
1 |
|
T4 |
20 |
|
T6 |
16 |
|
T57 |
14 |
| others[2] |
1211 |
1 |
|
T4 |
13 |
|
T6 |
22 |
|
T57 |
7 |
| others[3] |
2081 |
1 |
|
T4 |
27 |
|
T16 |
1 |
|
T6 |
32 |
| false |
654 |
1 |
|
T4 |
7 |
|
T16 |
1 |
|
T6 |
11 |
| true |
435 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T246 |
1 |
|
T396 |
1 |
|
T397 |
1 |
| others[1] |
5 |
1 |
|
T398 |
1 |
|
T399 |
1 |
|
T400 |
1 |
| others[2] |
6 |
1 |
|
T80 |
1 |
|
T81 |
1 |
|
T401 |
1 |
| others[3] |
9 |
1 |
|
T180 |
1 |
|
T85 |
1 |
|
T402 |
1 |
| false |
7 |
1 |
|
T1 |
1 |
|
T59 |
1 |
|
T58 |
1 |
| true |
59 |
1 |
|
T3 |
1 |
|
T12 |
2 |
|
T153 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T387 |
1 |
|
T403 |
1 |
|
T404 |
1 |
| others[1] |
8 |
1 |
|
T254 |
1 |
|
T390 |
1 |
|
T405 |
1 |
| others[2] |
2 |
1 |
|
T28 |
1 |
|
T389 |
1 |
|
- |
- |
| others[3] |
5 |
1 |
|
T89 |
1 |
|
T388 |
1 |
|
T391 |
1 |
| false |
8 |
1 |
|
T29 |
1 |
|
T189 |
1 |
|
T406 |
1 |
| true |
19 |
1 |
|
T335 |
1 |
|
T407 |
1 |
|
T408 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |