Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10043 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
17 |
| others[1] |
801 |
1 |
|
T4 |
14 |
|
T16 |
1 |
|
T57 |
14 |
| others[2] |
741 |
1 |
|
T4 |
13 |
|
T16 |
1 |
|
T57 |
7 |
| others[3] |
1343 |
1 |
|
T4 |
31 |
|
T57 |
21 |
|
T18 |
34 |
| false |
401 |
1 |
|
T4 |
10 |
|
T57 |
7 |
|
T18 |
8 |
| true |
507 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2348 |
1 |
|
T4 |
19 |
|
T6 |
16 |
|
T57 |
12 |
| others[1] |
2400 |
1 |
|
T3 |
1 |
|
T4 |
21 |
|
T6 |
17 |
| others[2] |
2440 |
1 |
|
T3 |
1 |
|
T4 |
15 |
|
T6 |
18 |
| others[3] |
3848 |
1 |
|
T2 |
1 |
|
T4 |
25 |
|
T16 |
1 |
| false |
1251 |
1 |
|
T4 |
5 |
|
T16 |
1 |
|
T6 |
12 |
| true |
1549 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9450 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
292 |
1 |
|
T18 |
11 |
|
T20 |
1 |
|
T72 |
2 |
| others[2] |
261 |
1 |
|
T8 |
1 |
|
T18 |
13 |
|
T99 |
11 |
| others[3] |
461 |
1 |
|
T16 |
1 |
|
T18 |
12 |
|
T72 |
1 |
| false |
131 |
1 |
|
T18 |
6 |
|
T124 |
1 |
|
T99 |
1 |
| true |
3241 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9711 |
1 |
|
T3 |
2 |
|
T4 |
5 |
|
T16 |
2 |
| others[1] |
465 |
1 |
|
T4 |
9 |
|
T56 |
1 |
|
T57 |
7 |
| others[2] |
465 |
1 |
|
T4 |
9 |
|
T16 |
1 |
|
T59 |
1 |
| others[3] |
757 |
1 |
|
T4 |
11 |
|
T57 |
9 |
|
T18 |
18 |
| false |
241 |
1 |
|
T4 |
6 |
|
T57 |
3 |
|
T18 |
5 |
| true |
2197 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
45 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9460 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
269 |
1 |
|
T16 |
2 |
|
T8 |
1 |
|
T18 |
8 |
| others[2] |
248 |
1 |
|
T18 |
14 |
|
T211 |
1 |
|
T51 |
1 |
| others[3] |
423 |
1 |
|
T5 |
1 |
|
T18 |
11 |
|
T32 |
1 |
| false |
129 |
1 |
|
T18 |
8 |
|
T33 |
1 |
|
T24 |
1 |
| true |
3307 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9481 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
271 |
1 |
|
T16 |
1 |
|
T18 |
15 |
|
T20 |
1 |
| others[2] |
244 |
1 |
|
T18 |
8 |
|
T72 |
1 |
|
T211 |
2 |
| others[3] |
427 |
1 |
|
T18 |
15 |
|
T33 |
1 |
|
T253 |
1 |
| false |
133 |
1 |
|
T18 |
5 |
|
T210 |
1 |
|
T99 |
5 |
| true |
3280 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10021 |
1 |
|
T3 |
2 |
|
T4 |
14 |
|
T16 |
1 |
| others[1] |
826 |
1 |
|
T4 |
20 |
|
T57 |
12 |
|
T18 |
26 |
| others[2] |
770 |
1 |
|
T4 |
22 |
|
T57 |
13 |
|
T18 |
17 |
| others[3] |
1299 |
1 |
|
T2 |
1 |
|
T4 |
25 |
|
T16 |
1 |
| false |
418 |
1 |
|
T4 |
4 |
|
T57 |
6 |
|
T18 |
12 |
| true |
502 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9948 |
1 |
|
T3 |
2 |
|
T4 |
15 |
|
T16 |
1 |
| others[1] |
834 |
1 |
|
T4 |
18 |
|
T57 |
14 |
|
T18 |
15 |
| others[2] |
813 |
1 |
|
T2 |
1 |
|
T4 |
23 |
|
T57 |
17 |
| others[3] |
1251 |
1 |
|
T4 |
18 |
|
T16 |
1 |
|
T57 |
22 |
| false |
430 |
1 |
|
T4 |
11 |
|
T57 |
5 |
|
T18 |
9 |
| true |
528 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2332 |
1 |
|
T4 |
17 |
|
T6 |
16 |
|
T57 |
16 |
| others[1] |
2423 |
1 |
|
T4 |
16 |
|
T16 |
1 |
|
T6 |
18 |
| others[2] |
2347 |
1 |
|
T3 |
2 |
|
T4 |
12 |
|
T6 |
11 |
| others[3] |
3948 |
1 |
|
T2 |
1 |
|
T4 |
24 |
|
T16 |
1 |
| false |
1225 |
1 |
|
T4 |
16 |
|
T6 |
18 |
|
T57 |
8 |
| true |
1529 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9488 |
1 |
|
T3 |
2 |
|
T16 |
2 |
|
T6 |
100 |
| others[1] |
262 |
1 |
|
T18 |
11 |
|
T130 |
1 |
|
T124 |
1 |
| others[2] |
284 |
1 |
|
T56 |
1 |
|
T18 |
8 |
|
T32 |
1 |
| others[3] |
440 |
1 |
|
T19 |
1 |
|
T18 |
14 |
|
T211 |
1 |
| false |
151 |
1 |
|
T18 |
4 |
|
T239 |
1 |
|
T22 |
1 |
| true |
3179 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9663 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
10 |
| others[1] |
479 |
1 |
|
T4 |
8 |
|
T56 |
1 |
|
T57 |
7 |
| others[2] |
467 |
1 |
|
T4 |
7 |
|
T5 |
1 |
|
T16 |
1 |
| others[3] |
787 |
1 |
|
T4 |
17 |
|
T16 |
1 |
|
T57 |
16 |
| false |
252 |
1 |
|
T4 |
7 |
|
T57 |
2 |
|
T18 |
6 |
| true |
2156 |
1 |
|
T1 |
1 |
|
T4 |
36 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9471 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T6 |
100 |
| others[1] |
276 |
1 |
|
T16 |
1 |
|
T18 |
11 |
|
T33 |
1 |
| others[2] |
235 |
1 |
|
T8 |
1 |
|
T18 |
11 |
|
T32 |
1 |
| others[3] |
428 |
1 |
|
T5 |
1 |
|
T56 |
1 |
|
T18 |
14 |
| false |
145 |
1 |
|
T16 |
1 |
|
T18 |
4 |
|
T99 |
1 |
| true |
3249 |
1 |
|
T1 |
1 |
|
T4 |
85 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9435 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T6 |
100 |
| others[1] |
243 |
1 |
|
T18 |
11 |
|
T72 |
1 |
|
T191 |
1 |
| others[2] |
245 |
1 |
|
T16 |
1 |
|
T18 |
7 |
|
T72 |
1 |
| others[3] |
461 |
1 |
|
T16 |
1 |
|
T18 |
21 |
|
T20 |
1 |
| false |
139 |
1 |
|
T18 |
5 |
|
T44 |
1 |
|
T51 |
1 |
| true |
3281 |
1 |
|
T1 |
1 |
|
T4 |
85 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10001 |
1 |
|
T3 |
2 |
|
T4 |
18 |
|
T16 |
1 |
| others[1] |
817 |
1 |
|
T4 |
15 |
|
T16 |
1 |
|
T57 |
8 |
| others[2] |
801 |
1 |
|
T4 |
13 |
|
T57 |
10 |
|
T18 |
22 |
| others[3] |
1275 |
1 |
|
T2 |
1 |
|
T4 |
33 |
|
T57 |
31 |
| false |
407 |
1 |
|
T4 |
6 |
|
T57 |
13 |
|
T18 |
9 |
| true |
503 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9946 |
1 |
|
T3 |
2 |
|
T4 |
19 |
|
T16 |
1 |
| others[1] |
805 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T57 |
13 |
| others[2] |
797 |
1 |
|
T4 |
19 |
|
T57 |
19 |
|
T18 |
20 |
| others[3] |
1322 |
1 |
|
T4 |
29 |
|
T57 |
17 |
|
T18 |
36 |
| false |
407 |
1 |
|
T4 |
7 |
|
T57 |
8 |
|
T18 |
13 |
| true |
527 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2445 |
1 |
|
T2 |
1 |
|
T4 |
20 |
|
T16 |
1 |
| others[1] |
2306 |
1 |
|
T3 |
1 |
|
T4 |
16 |
|
T6 |
20 |
| others[2] |
2416 |
1 |
|
T4 |
13 |
|
T16 |
1 |
|
T6 |
16 |
| others[3] |
3894 |
1 |
|
T4 |
27 |
|
T6 |
32 |
|
T57 |
23 |
| false |
1214 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T6 |
9 |
| true |
1529 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9469 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
277 |
1 |
|
T7 |
1 |
|
T19 |
1 |
|
T18 |
7 |
| others[2] |
272 |
1 |
|
T16 |
1 |
|
T18 |
8 |
|
T44 |
1 |
| others[3] |
460 |
1 |
|
T16 |
1 |
|
T18 |
17 |
|
T72 |
2 |
| false |
137 |
1 |
|
T18 |
6 |
|
T21 |
1 |
|
T25 |
1 |
| true |
3189 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9652 |
1 |
|
T3 |
2 |
|
T4 |
7 |
|
T16 |
1 |
| others[1] |
458 |
1 |
|
T4 |
15 |
|
T57 |
3 |
|
T18 |
10 |
| others[2] |
459 |
1 |
|
T4 |
7 |
|
T5 |
1 |
|
T7 |
1 |
| others[3] |
748 |
1 |
|
T1 |
1 |
|
T4 |
14 |
|
T16 |
1 |
| false |
269 |
1 |
|
T4 |
3 |
|
T57 |
5 |
|
T18 |
5 |
| true |
2218 |
1 |
|
T2 |
1 |
|
T4 |
39 |
|
T57 |
42 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9457 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
254 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T56 |
1 |
| others[2] |
253 |
1 |
|
T18 |
14 |
|
T130 |
1 |
|
T200 |
1 |
| others[3] |
463 |
1 |
|
T2 |
1 |
|
T18 |
18 |
|
T32 |
1 |
| false |
133 |
1 |
|
T18 |
5 |
|
T25 |
1 |
|
T99 |
5 |
| true |
3244 |
1 |
|
T1 |
1 |
|
T4 |
85 |
|
T16 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9453 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
230 |
1 |
|
T18 |
16 |
|
T99 |
10 |
|
T409 |
1 |
| others[2] |
259 |
1 |
|
T18 |
6 |
|
T130 |
1 |
|
T210 |
1 |
| others[3] |
417 |
1 |
|
T18 |
19 |
|
T32 |
1 |
|
T191 |
1 |
| false |
129 |
1 |
|
T18 |
9 |
|
T72 |
1 |
|
T33 |
1 |
| true |
3316 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10026 |
1 |
|
T3 |
2 |
|
T4 |
20 |
|
T6 |
100 |
| others[1] |
792 |
1 |
|
T4 |
20 |
|
T57 |
12 |
|
T18 |
20 |
| others[2] |
771 |
1 |
|
T4 |
13 |
|
T57 |
12 |
|
T18 |
20 |
| others[3] |
1313 |
1 |
|
T2 |
1 |
|
T4 |
25 |
|
T57 |
32 |
| false |
394 |
1 |
|
T4 |
7 |
|
T8 |
1 |
|
T57 |
6 |
| true |
508 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10009 |
1 |
|
T3 |
2 |
|
T4 |
15 |
|
T16 |
1 |
| others[1] |
739 |
1 |
|
T4 |
21 |
|
T57 |
16 |
|
T18 |
20 |
| others[2] |
796 |
1 |
|
T4 |
13 |
|
T57 |
14 |
|
T18 |
18 |
| others[3] |
1336 |
1 |
|
T2 |
1 |
|
T4 |
29 |
|
T57 |
25 |
| false |
391 |
1 |
|
T4 |
7 |
|
T57 |
6 |
|
T18 |
6 |
| true |
533 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2363 |
1 |
|
T3 |
1 |
|
T4 |
13 |
|
T6 |
24 |
| others[1] |
2349 |
1 |
|
T3 |
1 |
|
T4 |
9 |
|
T6 |
24 |
| others[2] |
2351 |
1 |
|
T2 |
1 |
|
T4 |
16 |
|
T16 |
2 |
| others[3] |
3945 |
1 |
|
T4 |
34 |
|
T6 |
30 |
|
T57 |
29 |
| false |
1252 |
1 |
|
T4 |
13 |
|
T6 |
5 |
|
T57 |
8 |
| true |
1544 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9452 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
275 |
1 |
|
T18 |
13 |
|
T72 |
1 |
|
T239 |
1 |
| others[2] |
276 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T18 |
15 |
| others[3] |
457 |
1 |
|
T18 |
18 |
|
T24 |
1 |
|
T211 |
1 |
| false |
122 |
1 |
|
T18 |
8 |
|
T33 |
1 |
|
T200 |
1 |
| true |
3222 |
1 |
|
T1 |
1 |
|
T4 |
85 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9657 |
1 |
|
T3 |
2 |
|
T4 |
15 |
|
T16 |
1 |
| others[1] |
507 |
1 |
|
T4 |
7 |
|
T57 |
7 |
|
T18 |
9 |
| others[2] |
462 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T57 |
6 |
| others[3] |
776 |
1 |
|
T1 |
1 |
|
T4 |
15 |
|
T57 |
12 |
| false |
230 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T57 |
6 |
| true |
2172 |
1 |
|
T4 |
40 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9470 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T8 |
1 |
| others[1] |
259 |
1 |
|
T16 |
1 |
|
T18 |
9 |
|
T72 |
1 |
| others[2] |
251 |
1 |
|
T2 |
1 |
|
T18 |
9 |
|
T191 |
1 |
| others[3] |
441 |
1 |
|
T7 |
1 |
|
T56 |
1 |
|
T18 |
14 |
| false |
144 |
1 |
|
T18 |
3 |
|
T72 |
2 |
|
T138 |
1 |
| true |
3239 |
1 |
|
T1 |
1 |
|
T4 |
85 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9438 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
242 |
1 |
|
T18 |
9 |
|
T332 |
1 |
|
T193 |
1 |
| others[2] |
235 |
1 |
|
T18 |
6 |
|
T72 |
1 |
|
T51 |
1 |
| others[3] |
439 |
1 |
|
T16 |
1 |
|
T18 |
10 |
|
T32 |
1 |
| false |
144 |
1 |
|
T18 |
5 |
|
T191 |
1 |
|
T122 |
1 |
| true |
3306 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9995 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
15 |
| others[1] |
785 |
1 |
|
T4 |
16 |
|
T57 |
13 |
|
T18 |
16 |
| others[2] |
742 |
1 |
|
T4 |
14 |
|
T57 |
11 |
|
T18 |
20 |
| others[3] |
1358 |
1 |
|
T4 |
36 |
|
T8 |
1 |
|
T57 |
29 |
| false |
422 |
1 |
|
T4 |
4 |
|
T57 |
9 |
|
T18 |
15 |
| true |
502 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10059 |
1 |
|
T3 |
2 |
|
T4 |
24 |
|
T6 |
100 |
| others[1] |
756 |
1 |
|
T4 |
14 |
|
T57 |
16 |
|
T18 |
20 |
| others[2] |
756 |
1 |
|
T4 |
16 |
|
T57 |
16 |
|
T18 |
16 |
| others[3] |
1300 |
1 |
|
T2 |
1 |
|
T4 |
24 |
|
T57 |
22 |
| false |
424 |
1 |
|
T4 |
7 |
|
T57 |
4 |
|
T18 |
14 |
| true |
509 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2384 |
1 |
|
T4 |
13 |
|
T6 |
15 |
|
T57 |
14 |
| others[1] |
2418 |
1 |
|
T4 |
15 |
|
T6 |
20 |
|
T57 |
18 |
| others[2] |
2365 |
1 |
|
T3 |
1 |
|
T4 |
20 |
|
T16 |
1 |
| others[3] |
3912 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
23 |
| false |
1226 |
1 |
|
T4 |
14 |
|
T6 |
6 |
|
T57 |
7 |
| true |
1499 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9430 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T6 |
100 |
| others[1] |
291 |
1 |
|
T18 |
7 |
|
T138 |
1 |
|
T193 |
1 |
| others[2] |
277 |
1 |
|
T18 |
13 |
|
T33 |
1 |
|
T200 |
1 |
| others[3] |
477 |
1 |
|
T56 |
1 |
|
T18 |
16 |
|
T44 |
1 |
| false |
157 |
1 |
|
T18 |
3 |
|
T25 |
1 |
|
T332 |
1 |
| true |
3172 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |