Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9674 |
1 |
|
T3 |
2 |
|
T4 |
16 |
|
T16 |
2 |
| others[1] |
454 |
1 |
|
T4 |
11 |
|
T59 |
1 |
|
T57 |
3 |
| others[2] |
458 |
1 |
|
T4 |
5 |
|
T57 |
8 |
|
T18 |
13 |
| others[3] |
778 |
1 |
|
T4 |
14 |
|
T8 |
1 |
|
T57 |
15 |
| false |
231 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T57 |
3 |
| true |
2209 |
1 |
|
T1 |
1 |
|
T4 |
33 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9462 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T19 |
1 |
| others[1] |
236 |
1 |
|
T18 |
7 |
|
T72 |
1 |
|
T239 |
1 |
| others[2] |
252 |
1 |
|
T18 |
9 |
|
T23 |
1 |
|
T99 |
10 |
| others[3] |
448 |
1 |
|
T5 |
1 |
|
T18 |
24 |
|
T72 |
1 |
| false |
139 |
1 |
|
T18 |
2 |
|
T20 |
1 |
|
T51 |
1 |
| true |
3267 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9476 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
256 |
1 |
|
T18 |
8 |
|
T122 |
1 |
|
T99 |
7 |
| others[2] |
261 |
1 |
|
T18 |
13 |
|
T20 |
1 |
|
T122 |
1 |
| others[3] |
453 |
1 |
|
T16 |
1 |
|
T18 |
17 |
|
T32 |
1 |
| false |
134 |
1 |
|
T18 |
4 |
|
T200 |
1 |
|
T51 |
1 |
| true |
3224 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9977 |
1 |
|
T3 |
2 |
|
T4 |
15 |
|
T6 |
100 |
| others[1] |
774 |
1 |
|
T1 |
1 |
|
T4 |
19 |
|
T57 |
15 |
| others[2] |
807 |
1 |
|
T2 |
1 |
|
T4 |
18 |
|
T16 |
1 |
| others[3] |
1332 |
1 |
|
T4 |
26 |
|
T57 |
21 |
|
T18 |
32 |
| false |
424 |
1 |
|
T4 |
7 |
|
T57 |
11 |
|
T18 |
9 |
| true |
490 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9964 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
15 |
| others[1] |
770 |
1 |
|
T4 |
14 |
|
T57 |
15 |
|
T18 |
15 |
| others[2] |
834 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T57 |
9 |
| others[3] |
1321 |
1 |
|
T4 |
32 |
|
T16 |
1 |
|
T57 |
26 |
| false |
391 |
1 |
|
T4 |
5 |
|
T57 |
8 |
|
T18 |
14 |
| true |
524 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2278 |
1 |
|
T4 |
9 |
|
T6 |
19 |
|
T57 |
12 |
| others[1] |
2424 |
1 |
|
T4 |
22 |
|
T16 |
1 |
|
T6 |
18 |
| others[2] |
2375 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
14 |
| others[3] |
3976 |
1 |
|
T3 |
1 |
|
T4 |
26 |
|
T16 |
1 |
| false |
1187 |
1 |
|
T4 |
14 |
|
T6 |
9 |
|
T57 |
6 |
| true |
1564 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9455 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T8 |
1 |
| others[1] |
271 |
1 |
|
T16 |
2 |
|
T18 |
8 |
|
T72 |
1 |
| others[2] |
273 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T18 |
9 |
| others[3] |
462 |
1 |
|
T18 |
13 |
|
T20 |
1 |
|
T72 |
1 |
| false |
151 |
1 |
|
T7 |
1 |
|
T18 |
8 |
|
T72 |
1 |
| true |
3192 |
1 |
|
T1 |
1 |
|
T4 |
85 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9693 |
1 |
|
T3 |
2 |
|
T4 |
7 |
|
T16 |
1 |
| others[1] |
453 |
1 |
|
T4 |
11 |
|
T8 |
1 |
|
T57 |
4 |
| others[2] |
469 |
1 |
|
T1 |
1 |
|
T4 |
5 |
|
T57 |
4 |
| others[3] |
762 |
1 |
|
T4 |
9 |
|
T5 |
1 |
|
T57 |
16 |
| false |
248 |
1 |
|
T4 |
6 |
|
T16 |
1 |
|
T57 |
2 |
| true |
2179 |
1 |
|
T2 |
1 |
|
T4 |
47 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9419 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T6 |
100 |
| others[1] |
255 |
1 |
|
T18 |
12 |
|
T72 |
1 |
|
T122 |
1 |
| others[2] |
250 |
1 |
|
T16 |
1 |
|
T18 |
6 |
|
T193 |
1 |
| others[3] |
460 |
1 |
|
T18 |
17 |
|
T44 |
1 |
|
T211 |
1 |
| false |
122 |
1 |
|
T56 |
1 |
|
T18 |
1 |
|
T72 |
1 |
| true |
3298 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9439 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
220 |
1 |
|
T18 |
7 |
|
T20 |
1 |
|
T211 |
1 |
| others[2] |
278 |
1 |
|
T18 |
14 |
|
T32 |
1 |
|
T72 |
1 |
| others[3] |
420 |
1 |
|
T18 |
21 |
|
T72 |
1 |
|
T33 |
1 |
| false |
130 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T18 |
5 |
| true |
3317 |
1 |
|
T1 |
1 |
|
T4 |
85 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9978 |
1 |
|
T3 |
2 |
|
T4 |
21 |
|
T6 |
100 |
| others[1] |
792 |
1 |
|
T4 |
15 |
|
T57 |
13 |
|
T18 |
20 |
| others[2] |
767 |
1 |
|
T4 |
14 |
|
T57 |
16 |
|
T18 |
18 |
| others[3] |
1346 |
1 |
|
T4 |
25 |
|
T57 |
23 |
|
T18 |
41 |
| false |
416 |
1 |
|
T2 |
1 |
|
T4 |
10 |
|
T57 |
7 |
| true |
505 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9988 |
1 |
|
T3 |
2 |
|
T4 |
13 |
|
T6 |
100 |
| others[1] |
782 |
1 |
|
T4 |
25 |
|
T57 |
12 |
|
T18 |
22 |
| others[2] |
797 |
1 |
|
T4 |
10 |
|
T16 |
1 |
|
T57 |
14 |
| others[3] |
1312 |
1 |
|
T2 |
1 |
|
T4 |
25 |
|
T57 |
31 |
| false |
390 |
1 |
|
T4 |
12 |
|
T57 |
7 |
|
T18 |
13 |
| true |
535 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2366 |
1 |
|
T3 |
1 |
|
T4 |
17 |
|
T6 |
22 |
| others[1] |
2304 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T6 |
19 |
| others[2] |
2409 |
1 |
|
T4 |
19 |
|
T16 |
1 |
|
T6 |
21 |
| others[3] |
3947 |
1 |
|
T3 |
1 |
|
T4 |
29 |
|
T16 |
1 |
| false |
1240 |
1 |
|
T4 |
5 |
|
T6 |
12 |
|
T57 |
5 |
| true |
1538 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9483 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T6 |
100 |
| others[1] |
261 |
1 |
|
T18 |
8 |
|
T130 |
1 |
|
T253 |
1 |
| others[2] |
250 |
1 |
|
T16 |
1 |
|
T18 |
10 |
|
T191 |
1 |
| others[3] |
483 |
1 |
|
T18 |
17 |
|
T44 |
1 |
|
T20 |
1 |
| false |
125 |
1 |
|
T8 |
1 |
|
T18 |
5 |
|
T76 |
1 |
| true |
3202 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9644 |
1 |
|
T3 |
2 |
|
T4 |
8 |
|
T6 |
100 |
| others[1] |
481 |
1 |
|
T4 |
9 |
|
T57 |
10 |
|
T19 |
1 |
| others[2] |
447 |
1 |
|
T1 |
1 |
|
T4 |
12 |
|
T16 |
1 |
| others[3] |
769 |
1 |
|
T4 |
9 |
|
T5 |
1 |
|
T16 |
1 |
| false |
239 |
1 |
|
T4 |
7 |
|
T57 |
4 |
|
T18 |
7 |
| true |
2224 |
1 |
|
T2 |
1 |
|
T4 |
40 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9469 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T7 |
1 |
| others[1] |
251 |
1 |
|
T18 |
9 |
|
T210 |
1 |
|
T127 |
1 |
| others[2] |
257 |
1 |
|
T18 |
5 |
|
T24 |
1 |
|
T332 |
1 |
| others[3] |
442 |
1 |
|
T56 |
1 |
|
T18 |
12 |
|
T130 |
1 |
| false |
121 |
1 |
|
T19 |
1 |
|
T18 |
5 |
|
T193 |
1 |
| true |
3264 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9463 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T16 |
1 |
| others[1] |
241 |
1 |
|
T18 |
9 |
|
T72 |
2 |
|
T130 |
1 |
| others[2] |
258 |
1 |
|
T16 |
1 |
|
T18 |
7 |
|
T44 |
1 |
| others[3] |
432 |
1 |
|
T18 |
18 |
|
T32 |
1 |
|
T211 |
1 |
| false |
141 |
1 |
|
T18 |
8 |
|
T210 |
1 |
|
T253 |
1 |
| true |
3269 |
1 |
|
T1 |
1 |
|
T4 |
85 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9985 |
1 |
|
T3 |
2 |
|
T4 |
12 |
|
T6 |
100 |
| others[1] |
772 |
1 |
|
T4 |
14 |
|
T57 |
13 |
|
T18 |
18 |
| others[2] |
772 |
1 |
|
T4 |
30 |
|
T57 |
18 |
|
T18 |
17 |
| others[3] |
1360 |
1 |
|
T2 |
1 |
|
T4 |
21 |
|
T16 |
1 |
| false |
424 |
1 |
|
T1 |
1 |
|
T4 |
8 |
|
T57 |
4 |
| true |
491 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9947 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
11 |
| others[1] |
749 |
1 |
|
T4 |
16 |
|
T57 |
16 |
|
T18 |
25 |
| others[2] |
800 |
1 |
|
T4 |
19 |
|
T57 |
12 |
|
T18 |
16 |
| others[3] |
1385 |
1 |
|
T4 |
32 |
|
T16 |
1 |
|
T57 |
18 |
| false |
393 |
1 |
|
T4 |
7 |
|
T57 |
13 |
|
T18 |
5 |
| true |
530 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2363 |
1 |
|
T4 |
22 |
|
T16 |
1 |
|
T6 |
19 |
| others[1] |
2291 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T16 |
1 |
| others[2] |
2391 |
1 |
|
T4 |
23 |
|
T6 |
13 |
|
T57 |
11 |
| others[3] |
3943 |
1 |
|
T3 |
2 |
|
T4 |
25 |
|
T6 |
43 |
| false |
1251 |
1 |
|
T4 |
4 |
|
T6 |
7 |
|
T57 |
13 |
| true |
1565 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9469 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T6 |
100 |
| others[1] |
279 |
1 |
|
T19 |
1 |
|
T18 |
11 |
|
T332 |
1 |
| others[2] |
255 |
1 |
|
T18 |
13 |
|
T72 |
1 |
|
T99 |
9 |
| others[3] |
410 |
1 |
|
T18 |
12 |
|
T130 |
1 |
|
T239 |
1 |
| false |
150 |
1 |
|
T16 |
1 |
|
T18 |
7 |
|
T72 |
1 |
| true |
3241 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9676 |
1 |
|
T3 |
2 |
|
T4 |
9 |
|
T16 |
1 |
| others[1] |
440 |
1 |
|
T4 |
11 |
|
T57 |
4 |
|
T18 |
7 |
| others[2] |
453 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T7 |
1 |
| others[3] |
731 |
1 |
|
T4 |
10 |
|
T56 |
1 |
|
T59 |
1 |
| false |
287 |
1 |
|
T4 |
11 |
|
T16 |
1 |
|
T57 |
5 |
| true |
2217 |
1 |
|
T1 |
1 |
|
T4 |
39 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9460 |
1 |
|
T3 |
2 |
|
T6 |
100 |
|
T39 |
62 |
| others[1] |
279 |
1 |
|
T5 |
1 |
|
T18 |
9 |
|
T44 |
1 |
| others[2] |
270 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T56 |
1 |
| others[3] |
437 |
1 |
|
T18 |
8 |
|
T72 |
1 |
|
T191 |
1 |
| false |
131 |
1 |
|
T18 |
4 |
|
T122 |
1 |
|
T127 |
1 |
| true |
3227 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
85 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9425 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T6 |
100 |
| others[1] |
244 |
1 |
|
T18 |
9 |
|
T72 |
2 |
|
T332 |
1 |
| others[2] |
261 |
1 |
|
T18 |
15 |
|
T32 |
1 |
|
T72 |
1 |
| others[3] |
413 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T18 |
17 |
| false |
140 |
1 |
|
T18 |
3 |
|
T210 |
1 |
|
T122 |
1 |
| true |
3321 |
1 |
|
T1 |
1 |
|
T4 |
85 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9975 |
1 |
|
T3 |
2 |
|
T4 |
16 |
|
T6 |
100 |
| others[1] |
777 |
1 |
|
T4 |
21 |
|
T16 |
1 |
|
T57 |
12 |
| others[2] |
808 |
1 |
|
T4 |
16 |
|
T57 |
18 |
|
T18 |
19 |
| others[3] |
1315 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
22 |
| false |
439 |
1 |
|
T4 |
10 |
|
T57 |
7 |
|
T18 |
6 |
| true |
490 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T8 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |