Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	225710	1		T3	1		T4	44		T5	482
auto[FlashEraseBank]	184913	1		T1	2		T4	41		T5	611

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	230502	1		T1	1		T3	1		T5	1093
auto[FlashOpProgram]	160811	1		T1	1		T4	85		T16	2
auto[FlashOpErase]	15310	1		T16	1		T6	100		T59	2
auto[FlashOpInvalid]	4000	1		T6	200		T87	200		T88	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	230502	1		T1	1		T3	1		T5	1093
op[FlashOpProgram]	160811	1		T1	1		T4	85		T16	2
op[FlashOpErase]	15310	1		T16	1		T6	100		T59	2
read_erase_read	804	1		T18	6		T72	1		T28	3
read_prog_read	1096	1		T18	4		T32	13		T20	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	274495	1		T3	1		T4	85		T5	834
auto[FlashPartInfo]	133053	1		T1	1		T5	259		T8	265
auto[FlashPartInfo1]	653	1		T32	5		T20	4		T72	7
auto[FlashPartInfo2]	2422	1		T1	1		T59	1		T32	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	168842	1		T3	1		T5	834		T16	2
auto[FlashPartData]	auto[FlashOpProgram]	98099	1		T4	85		T16	2		T6	100
auto[FlashPartData]	auto[FlashOpErase]	3648	1		T16	1		T6	100		T59	1
auto[FlashPartData]	auto[FlashOpInvalid]	3906	1		T6	200		T87	196		T88	192
auto[FlashPartInfo]	auto[FlashOpRead]	59515	1		T1	1		T5	259		T8	265
auto[FlashPartInfo]	auto[FlashOpProgram]	61838	1		T18	640		T32	319		T20	308
auto[FlashPartInfo]	auto[FlashOpErase]	11624	1		T18	18		T72	1		T28	11
auto[FlashPartInfo]	auto[FlashOpInvalid]	76	1		T87	2		T88	6		T91	4
auto[FlashPartInfo1]	auto[FlashOpRead]	602	1		T32	5		T20	4		T72	7
auto[FlashPartInfo1]	auto[FlashOpProgram]	37	1		T87	1		T91	1		T411	1
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T87	1		T91	1		T181	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T87	2		T91	2		T411	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1543	1		T32	3		T20	5		T72	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	837	1		T1	1		T32	1		T20	9
auto[FlashPartInfo2]	auto[FlashOpErase]	32	1		T59	1		T88	1		T99	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T88	2		T412	2		T413	2