Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29458	1		T6	400		T39	1		T18	20
auto[1]	123	1		T34	1		T98	2		T217	1
auto[2]	107	1		T140	4		T101	10		T141	8
auto[3]	213	1		T21	1		T124	1		T229	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7491	1		T6	100		T18	5		T40	1
evic_idx[1]	7497	1		T6	100		T39	1		T18	5
evic_idx[2]	7468	1		T6	100		T18	5		T40	1
evic_idx[3]	7445	1		T6	100		T18	5		T40	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28826	1		T6	400		T39	1		T40	4
evic_op[2]	461	1		T18	4		T21	1		T34	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7140	1		T6	100		T40	1		T90	37
evic_idx[0]	evic_op[1]	auto[1]	32	1		T414	21		T415	11		-	-
evic_idx[0]	evic_op[1]	auto[2]	1	1		T141	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	53	1		T416	12		T417	21		T415	5
evic_idx[0]	evic_op[2]	auto[0]	78	1		T18	1		T123	5		T189	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T34	1		T418	1		T419	1
evic_idx[0]	evic_op[2]	auto[2]	18	1		T101	3		T420	2		T421	1
evic_idx[0]	evic_op[2]	auto[3]	11	1		T21	1		T212	1		T231	1
evic_idx[1]	evic_op[1]	auto[0]	7142	1		T6	100		T39	1		T40	1
evic_idx[1]	evic_op[1]	auto[1]	26	1		T414	12		T415	14		-	-
evic_idx[1]	evic_op[1]	auto[2]	1	1		T141	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	49	1		T416	15		T417	17		T415	1
evic_idx[1]	evic_op[2]	auto[0]	82	1		T18	1		T123	7		T189	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T418	1		T419	1		T422	1
evic_idx[1]	evic_op[2]	auto[2]	27	1		T101	1		T421	2		T423	2
evic_idx[1]	evic_op[2]	auto[3]	13	1		T124	1		T229	1		T212	1
evic_idx[2]	evic_op[1]	auto[0]	7137	1		T6	100		T40	1		T90	37
evic_idx[2]	evic_op[1]	auto[1]	22	1		T414	7		T415	15		-	-
evic_idx[2]	evic_op[1]	auto[2]	1	1		T141	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	35	1		T416	14		T417	9		T415	3
evic_idx[2]	evic_op[2]	auto[0]	78	1		T18	1		T123	6		T189	1
evic_idx[2]	evic_op[2]	auto[1]	8	1		T98	1		T114	1		T418	1
evic_idx[2]	evic_op[2]	auto[2]	21	1		T101	3		T423	2		T424	7
evic_idx[2]	evic_op[2]	auto[3]	13	1		T118	1		T302	1		T425	1
evic_idx[3]	evic_op[1]	auto[0]	7136	1		T6	100		T40	1		T90	37
evic_idx[3]	evic_op[1]	auto[1]	22	1		T414	12		T415	10		-	-
evic_idx[3]	evic_op[1]	auto[2]	1	1		T141	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	28	1		T416	10		T417	6		T415	5
evic_idx[3]	evic_op[2]	auto[0]	71	1		T18	1		T123	5		T189	1
evic_idx[3]	evic_op[2]	auto[1]	6	1		T98	1		T217	1		T296	1
evic_idx[3]	evic_op[2]	auto[2]	17	1		T101	3		T420	1		T424	4
evic_idx[3]	evic_op[2]	auto[3]	11	1		T35	1		T53	1		T302	1