Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
4682 | 
1 | 
 | 
T48 | 
98 | 
 | 
T49 | 
88 | 
 | 
T50 | 
95 | 
| instr_types[0] | 
5794 | 
1 | 
 | 
T48 | 
188 | 
 | 
T49 | 
212 | 
 | 
T50 | 
189 | 
| instr_types[1] | 
4041481 | 
1 | 
 | 
T5 | 
16801 | 
 | 
T16 | 
10 | 
 | 
T8 | 
16676 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4050225 | 
1 | 
 | 
T5 | 
16801 | 
 | 
T16 | 
10 | 
 | 
T8 | 
16676 | 
| auto[1] | 
1732 | 
1 | 
 | 
T48 | 
132 | 
 | 
T49 | 
126 | 
 | 
T50 | 
143 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4370 | 
1 | 
 | 
T48 | 
49 | 
 | 
T49 | 
63 | 
 | 
T50 | 
85 | 
| auto[0] | 
instr_types[0] | 
5103 | 
1 | 
 | 
T48 | 
162 | 
 | 
T49 | 
175 | 
 | 
T50 | 
122 | 
| auto[0] | 
instr_types[1] | 
4040752 | 
1 | 
 | 
T5 | 
16801 | 
 | 
T16 | 
10 | 
 | 
T8 | 
16676 | 
| auto[1] | 
others | 
312 | 
1 | 
 | 
T48 | 
49 | 
 | 
T49 | 
25 | 
 | 
T50 | 
10 | 
| auto[1] | 
instr_types[0] | 
691 | 
1 | 
 | 
T48 | 
26 | 
 | 
T49 | 
37 | 
 | 
T50 | 
67 | 
| auto[1] | 
instr_types[1] | 
729 | 
1 | 
 | 
T48 | 
57 | 
 | 
T49 | 
64 | 
 | 
T50 | 
66 |