Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	8157	1		T250	2795		T358	2669		T359	2693
rd_lvl[2]	18500	1		T250	1846		T234	1835		T360	6346
rd_lvl[3]	18986	1		T56	1424		T130	2711		T250	760
rd_lvl[4]	38732	1		T56	3552		T130	1484		T239	2170
rd_lvl[5]	21223	1		T8	863		T56	374		T239	1253
rd_lvl[6]	14156	1		T8	1932		T56	30		T19	1321
rd_lvl[7]	11995	1		T8	792		T7	1256		T19	487
rd_lvl[8]	12657	1		T8	67		T7	890		T56	1
rd_lvl[9]	9850	1		T7	19		T19	21		T250	1223
rd_lvl[10]	8369	1		T7	19		T56	1		T19	21
rd_lvl[11]	8988	1		T5	604		T8	67		T250	123
rd_lvl[12]	8149	1		T5	474		T239	1		T250	1
rd_lvl[13]	5691	1		T56	30		T250	1		T30	31
rd_lvl[14]	4187	1		T5	15		T250	13		T31	699
rd_lvl[15]	2433	1		T361	414		T362	1		T363	392