Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	280339	1		T1	2		T3	1		T4	2
all_pins[1]	280339	1		T1	2		T3	1		T4	2
all_pins[2]	280339	1		T1	2		T3	1		T4	2
all_pins[3]	280339	1		T1	2		T3	1		T4	2
all_pins[4]	280339	1		T1	2		T3	1		T4	2
all_pins[5]	280339	1		T1	2		T3	1		T4	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1385422	1		T1	12		T3	6		T4	12
values[0x1]	296612	1		T5	2186		T8	5112		T7	3276
transitions[0x0=>0x1]	271312	1		T5	2186		T8	4230		T7	3257
transitions[0x1=>0x0]	271298	1		T5	2186		T8	4230		T7	3257

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280166	1		T1	2		T3	1		T4	2
all_pins[0]	values[0x1]	173	1		T280	4		T281	5		T351	2
all_pins[0]	transitions[0x0=>0x1]	92	1		T280	3		T351	1		T353	3
all_pins[0]	transitions[0x1=>0x0]	75	1		T353	1		T352	3		T357	6
all_pins[1]	values[0x0]	280183	1		T1	2		T3	1		T4	2
all_pins[1]	values[0x1]	156	1		T280	1		T281	5		T351	1
all_pins[1]	transitions[0x0=>0x1]	126	1		T280	1		T281	4		T351	1
all_pins[1]	transitions[0x1=>0x0]	465	1		T361	87		T363	26		T366	37
all_pins[2]	values[0x0]	279844	1		T1	2		T3	1		T4	2
all_pins[2]	values[0x1]	495	1		T361	87		T363	26		T366	37
all_pins[2]	transitions[0x0=>0x1]	41	1		T281	1		T351	2		T353	1
all_pins[2]	transitions[0x1=>0x0]	192220	1		T5	1093		T8	3721		T7	2184
all_pins[3]	values[0x0]	87665	1		T1	2		T3	1		T4	2
all_pins[3]	values[0x1]	192674	1		T5	1093		T8	3721		T7	2184
all_pins[3]	transitions[0x0=>0x1]	167997	1		T5	1093		T8	2839		T7	2165
all_pins[3]	transitions[0x1=>0x0]	78372	1		T5	1093		T8	509		T7	1073
all_pins[4]	values[0x0]	177290	1		T1	2		T3	1		T4	2
all_pins[4]	values[0x1]	103049	1		T5	1093		T8	1391		T7	1092
all_pins[4]	transitions[0x0=>0x1]	103035	1		T5	1093		T8	1391		T7	1092
all_pins[4]	transitions[0x1=>0x0]	51	1		T351	1		T353	1		T354	2
all_pins[5]	values[0x0]	280274	1		T1	2		T3	1		T4	2
all_pins[5]	values[0x1]	65	1		T281	1		T351	1		T353	2
all_pins[5]	transitions[0x0=>0x1]	21	1		T354	1		T357	2		T355	1
all_pins[5]	transitions[0x1=>0x0]	115	1		T280	3		T281	3		T351	2