| T1081 |
/workspace/coverage/default/13.flash_ctrl_re_evict.4269717313 |
|
|
Mar 05 01:54:07 PM PST 24 |
Mar 05 01:54:46 PM PST 24 |
233178400 ps |
| T1082 |
/workspace/coverage/default/12.flash_ctrl_alert_test.1023521973 |
|
|
Mar 05 01:54:02 PM PST 24 |
Mar 05 01:54:16 PM PST 24 |
53535300 ps |
| T1083 |
/workspace/coverage/default/21.flash_ctrl_disable.3793785099 |
|
|
Mar 05 01:55:27 PM PST 24 |
Mar 05 01:55:49 PM PST 24 |
12648200 ps |
| T1084 |
/workspace/coverage/default/15.flash_ctrl_connect.2893763001 |
|
|
Mar 05 01:54:27 PM PST 24 |
Mar 05 01:54:43 PM PST 24 |
117071900 ps |
| T1085 |
/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1874789448 |
|
|
Mar 05 01:53:48 PM PST 24 |
Mar 05 01:54:02 PM PST 24 |
132830200 ps |
| T1086 |
/workspace/coverage/default/33.flash_ctrl_connect.146466562 |
|
|
Mar 05 01:56:20 PM PST 24 |
Mar 05 01:56:34 PM PST 24 |
50416600 ps |
| T1087 |
/workspace/coverage/default/11.flash_ctrl_alert_test.896057575 |
|
|
Mar 05 01:53:55 PM PST 24 |
Mar 05 01:54:08 PM PST 24 |
197796900 ps |
| T1088 |
/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.2622750679 |
|
|
Mar 05 01:56:22 PM PST 24 |
Mar 05 01:56:53 PM PST 24 |
77565900 ps |
| T1089 |
/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2926827851 |
|
|
Mar 05 01:57:13 PM PST 24 |
Mar 05 01:59:07 PM PST 24 |
13379496500 ps |
| T1090 |
/workspace/coverage/default/35.flash_ctrl_otp_reset.1076374865 |
|
|
Mar 05 01:56:25 PM PST 24 |
Mar 05 01:58:18 PM PST 24 |
73418600 ps |
| T1091 |
/workspace/coverage/default/2.flash_ctrl_hw_rma.2374031657 |
|
|
Mar 05 01:52:17 PM PST 24 |
Mar 05 02:23:32 PM PST 24 |
271931115100 ps |
| T1092 |
/workspace/coverage/default/14.flash_ctrl_phy_arb.3144584157 |
|
|
Mar 05 01:54:17 PM PST 24 |
Mar 05 01:56:53 PM PST 24 |
140841000 ps |
| T1093 |
/workspace/coverage/default/17.flash_ctrl_mp_regions.2879429684 |
|
|
Mar 05 01:54:50 PM PST 24 |
Mar 05 02:00:50 PM PST 24 |
5102506500 ps |
| T1094 |
/workspace/coverage/default/36.flash_ctrl_smoke.2874292615 |
|
|
Mar 05 01:56:29 PM PST 24 |
Mar 05 01:58:10 PM PST 24 |
204757000 ps |
| T1095 |
/workspace/coverage/default/39.flash_ctrl_rw_evict.2889057188 |
|
|
Mar 05 01:56:41 PM PST 24 |
Mar 05 01:57:12 PM PST 24 |
50743300 ps |
| T1096 |
/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3005649336 |
|
|
Mar 05 01:52:13 PM PST 24 |
Mar 05 01:55:29 PM PST 24 |
26054960000 ps |
| T1097 |
/workspace/coverage/default/31.flash_ctrl_connect.3644393168 |
|
|
Mar 05 01:56:14 PM PST 24 |
Mar 05 01:56:30 PM PST 24 |
13623400 ps |
| T1098 |
/workspace/coverage/default/2.flash_ctrl_wo.2321472102 |
|
|
Mar 05 01:52:20 PM PST 24 |
Mar 05 01:55:18 PM PST 24 |
4105988800 ps |
| T1099 |
/workspace/coverage/default/11.flash_ctrl_connect.3684392966 |
|
|
Mar 05 01:54:06 PM PST 24 |
Mar 05 01:54:20 PM PST 24 |
18979300 ps |
| T1100 |
/workspace/coverage/default/8.flash_ctrl_error_mp.1626706322 |
|
|
Mar 05 01:53:23 PM PST 24 |
Mar 05 02:31:28 PM PST 24 |
90599747100 ps |
| T1101 |
/workspace/coverage/default/57.flash_ctrl_connect.4200688749 |
|
|
Mar 05 01:57:16 PM PST 24 |
Mar 05 01:57:30 PM PST 24 |
24160100 ps |
| T209 |
/workspace/coverage/default/2.flash_ctrl_sec_cm.3381620757 |
|
|
Mar 05 01:52:27 PM PST 24 |
Mar 05 03:10:45 PM PST 24 |
4126139100 ps |
| T1102 |
/workspace/coverage/default/10.flash_ctrl_invalid_op.223130418 |
|
|
Mar 05 01:53:42 PM PST 24 |
Mar 05 01:54:53 PM PST 24 |
7089449500 ps |
| T163 |
/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.615243472 |
|
|
Mar 05 01:52:06 PM PST 24 |
Mar 05 02:04:31 PM PST 24 |
120155175500 ps |
| T1103 |
/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3940478581 |
|
|
Mar 05 01:53:54 PM PST 24 |
Mar 05 01:54:08 PM PST 24 |
57167000 ps |
| T1104 |
/workspace/coverage/default/49.flash_ctrl_disable.2219036704 |
|
|
Mar 05 01:57:12 PM PST 24 |
Mar 05 01:57:35 PM PST 24 |
12083300 ps |
| T1105 |
/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1765604174 |
|
|
Mar 05 01:55:05 PM PST 24 |
Mar 05 01:55:52 PM PST 24 |
10059091900 ps |
| T1106 |
/workspace/coverage/default/26.flash_ctrl_alert_test.2168677972 |
|
|
Mar 05 01:55:50 PM PST 24 |
Mar 05 01:56:03 PM PST 24 |
226663900 ps |
| T1107 |
/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1428172870 |
|
|
Mar 05 01:53:40 PM PST 24 |
Mar 05 01:53:53 PM PST 24 |
25101100 ps |
| T1108 |
/workspace/coverage/default/9.flash_ctrl_rw.2440190442 |
|
|
Mar 05 01:53:31 PM PST 24 |
Mar 05 02:00:50 PM PST 24 |
13618512500 ps |
| T1109 |
/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3344237820 |
|
|
Mar 05 01:55:57 PM PST 24 |
Mar 05 02:00:05 PM PST 24 |
11801125900 ps |
| T1110 |
/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.663751749 |
|
|
Mar 05 01:53:31 PM PST 24 |
Mar 05 01:56:38 PM PST 24 |
9214131200 ps |
| T1111 |
/workspace/coverage/default/13.flash_ctrl_mp_regions.334761122 |
|
|
Mar 05 01:54:08 PM PST 24 |
Mar 05 02:13:53 PM PST 24 |
27834297700 ps |
| T1112 |
/workspace/coverage/default/44.flash_ctrl_alert_test.1061620677 |
|
|
Mar 05 01:56:59 PM PST 24 |
Mar 05 01:57:14 PM PST 24 |
230334800 ps |
| T1113 |
/workspace/coverage/default/2.flash_ctrl_phy_arb.443801315 |
|
|
Mar 05 01:52:13 PM PST 24 |
Mar 05 01:54:05 PM PST 24 |
127715000 ps |
| T1114 |
/workspace/coverage/default/0.flash_ctrl_stress_all.1114685211 |
|
|
Mar 05 01:52:08 PM PST 24 |
Mar 05 02:14:51 PM PST 24 |
1957174600 ps |
| T1115 |
/workspace/coverage/default/60.flash_ctrl_connect.990562827 |
|
|
Mar 05 01:57:20 PM PST 24 |
Mar 05 01:57:35 PM PST 24 |
27828400 ps |
| T1116 |
/workspace/coverage/default/22.flash_ctrl_connect.1968283064 |
|
|
Mar 05 01:55:35 PM PST 24 |
Mar 05 01:55:51 PM PST 24 |
20366100 ps |
| T1117 |
/workspace/coverage/default/17.flash_ctrl_sec_info_access.1033368063 |
|
|
Mar 05 01:54:50 PM PST 24 |
Mar 05 01:55:48 PM PST 24 |
534109100 ps |
| T1118 |
/workspace/coverage/default/12.flash_ctrl_rw_evict.3814384422 |
|
|
Mar 05 01:54:01 PM PST 24 |
Mar 05 01:54:33 PM PST 24 |
170733400 ps |
| T1119 |
/workspace/coverage/default/12.flash_ctrl_mp_regions.2046701667 |
|
|
Mar 05 01:54:01 PM PST 24 |
Mar 05 01:58:13 PM PST 24 |
41451996600 ps |
| T1120 |
/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4092411998 |
|
|
Mar 05 01:52:31 PM PST 24 |
Mar 05 01:56:23 PM PST 24 |
35648870400 ps |
| T1121 |
/workspace/coverage/default/3.flash_ctrl_full_mem_access.2553185782 |
|
|
Mar 05 01:52:28 PM PST 24 |
Mar 05 02:33:34 PM PST 24 |
86431101200 ps |
| T1122 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.3155949758 |
|
|
Mar 05 01:52:07 PM PST 24 |
Mar 05 01:53:37 PM PST 24 |
4093665000 ps |
| T1123 |
/workspace/coverage/default/10.flash_ctrl_ro.184159719 |
|
|
Mar 05 01:53:48 PM PST 24 |
Mar 05 01:55:15 PM PST 24 |
315302000 ps |
| T1124 |
/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3062882466 |
|
|
Mar 05 01:56:18 PM PST 24 |
Mar 05 01:56:49 PM PST 24 |
46914400 ps |
| T1125 |
/workspace/coverage/default/5.flash_ctrl_intr_wr.397605304 |
|
|
Mar 05 01:52:50 PM PST 24 |
Mar 05 01:54:33 PM PST 24 |
4609871700 ps |
| T1126 |
/workspace/coverage/default/5.flash_ctrl_error_mp.3253185125 |
|
|
Mar 05 01:52:50 PM PST 24 |
Mar 05 02:31:36 PM PST 24 |
6161266200 ps |
| T1127 |
/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1124740290 |
|
|
Mar 05 01:52:50 PM PST 24 |
Mar 05 01:57:51 PM PST 24 |
42908737200 ps |
| T1128 |
/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3973174866 |
|
|
Mar 05 01:53:55 PM PST 24 |
Mar 05 01:54:08 PM PST 24 |
63934600 ps |
| T1129 |
/workspace/coverage/default/42.flash_ctrl_alert_test.417571752 |
|
|
Mar 05 01:56:55 PM PST 24 |
Mar 05 01:57:09 PM PST 24 |
68777800 ps |
| T1130 |
/workspace/coverage/default/16.flash_ctrl_rw_evict.2514783644 |
|
|
Mar 05 01:54:43 PM PST 24 |
Mar 05 01:55:14 PM PST 24 |
32601200 ps |
| T1131 |
/workspace/coverage/default/8.flash_ctrl_rand_ops.185191036 |
|
|
Mar 05 01:53:16 PM PST 24 |
Mar 05 02:13:41 PM PST 24 |
1512468200 ps |
| T1132 |
/workspace/coverage/default/57.flash_ctrl_otp_reset.2669327061 |
|
|
Mar 05 01:57:19 PM PST 24 |
Mar 05 01:59:30 PM PST 24 |
271133100 ps |
| T1133 |
/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.2042218814 |
|
|
Mar 05 01:54:15 PM PST 24 |
Mar 05 01:57:44 PM PST 24 |
76191912400 ps |
| T1134 |
/workspace/coverage/default/17.flash_ctrl_intr_rd.2546280876 |
|
|
Mar 05 01:54:49 PM PST 24 |
Mar 05 01:58:05 PM PST 24 |
4874428600 ps |
| T1135 |
/workspace/coverage/default/42.flash_ctrl_disable.3470199983 |
|
|
Mar 05 01:56:55 PM PST 24 |
Mar 05 01:57:17 PM PST 24 |
14679100 ps |
| T1136 |
/workspace/coverage/default/9.flash_ctrl_rand_ops.3417024094 |
|
|
Mar 05 01:53:31 PM PST 24 |
Mar 05 02:15:05 PM PST 24 |
1630729800 ps |
| T36 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3836202775 |
|
|
Mar 05 01:08:36 PM PST 24 |
Mar 05 01:08:51 PM PST 24 |
28606100 ps |
| T280 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1156411326 |
|
|
Mar 05 01:08:50 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
30711300 ps |
| T37 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1444884122 |
|
|
Mar 05 01:08:37 PM PST 24 |
Mar 05 01:08:55 PM PST 24 |
121752600 ps |
| T38 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.123452174 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:52 PM PST 24 |
840415500 ps |
| T203 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4264133194 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:04 PM PST 24 |
84517800 ps |
| T245 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2195843537 |
|
|
Mar 05 01:08:30 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
42280400 ps |
| T281 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1915759905 |
|
|
Mar 05 01:08:52 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
50152800 ps |
| T201 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3938824674 |
|
|
Mar 05 01:08:48 PM PST 24 |
Mar 05 01:09:05 PM PST 24 |
112812900 ps |
| T240 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3932357835 |
|
|
Mar 05 01:08:29 PM PST 24 |
Mar 05 01:08:45 PM PST 24 |
126920100 ps |
| T1137 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2740501007 |
|
|
Mar 05 01:08:31 PM PST 24 |
Mar 05 01:08:45 PM PST 24 |
41690800 ps |
| T351 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3895278444 |
|
|
Mar 05 01:08:56 PM PST 24 |
Mar 05 01:09:10 PM PST 24 |
22085000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.185797619 |
|
|
Mar 05 01:08:31 PM PST 24 |
Mar 05 01:08:46 PM PST 24 |
21347600 ps |
| T202 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3585977517 |
|
|
Mar 05 01:08:41 PM PST 24 |
Mar 05 01:08:58 PM PST 24 |
45443000 ps |
| T353 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2548317162 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:00 PM PST 24 |
28933200 ps |
| T264 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1646469939 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:51 PM PST 24 |
140895200 ps |
| T1139 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.78685337 |
|
|
Mar 05 01:08:32 PM PST 24 |
Mar 05 01:08:46 PM PST 24 |
35572800 ps |
| T352 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4099410670 |
|
|
Mar 05 01:08:53 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
79889900 ps |
| T241 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.274795195 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
135050200 ps |
| T271 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1495462672 |
|
|
Mar 05 01:08:16 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
119135100 ps |
| T270 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2789621315 |
|
|
Mar 05 01:08:23 PM PST 24 |
Mar 05 01:08:55 PM PST 24 |
48865500 ps |
| T269 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1324395934 |
|
|
Mar 05 01:08:44 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
882201100 ps |
| T272 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.460838962 |
|
|
Mar 05 01:08:37 PM PST 24 |
Mar 05 01:08:54 PM PST 24 |
209622800 ps |
| T354 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3654622523 |
|
|
Mar 05 01:08:47 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
33458800 ps |
| T357 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1664685611 |
|
|
Mar 05 01:08:38 PM PST 24 |
Mar 05 01:08:53 PM PST 24 |
93111100 ps |
| T355 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3185637733 |
|
|
Mar 05 01:08:48 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
32344600 ps |
| T1140 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1188283104 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
24754700 ps |
| T242 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.16832256 |
|
|
Mar 05 01:08:18 PM PST 24 |
Mar 05 01:08:34 PM PST 24 |
117926300 ps |
| T243 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1949513873 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:52 PM PST 24 |
45128400 ps |
| T1141 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2453734390 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
12715100 ps |
| T244 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1897540819 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:23:46 PM PST 24 |
1770986200 ps |
| T326 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3091188970 |
|
|
Mar 05 01:08:24 PM PST 24 |
Mar 05 01:09:19 PM PST 24 |
747688800 ps |
| T316 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1699596964 |
|
|
Mar 05 01:08:40 PM PST 24 |
Mar 05 01:08:55 PM PST 24 |
257135300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1894594504 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:09:00 PM PST 24 |
35878700 ps |
| T317 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.713705091 |
|
|
Mar 05 01:08:38 PM PST 24 |
Mar 05 01:08:58 PM PST 24 |
199381500 ps |
| T356 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.251804212 |
|
|
Mar 05 01:08:55 PM PST 24 |
Mar 05 01:09:10 PM PST 24 |
27761500 ps |
| T1143 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2218062829 |
|
|
Mar 05 01:08:48 PM PST 24 |
Mar 05 01:09:24 PM PST 24 |
61824000 ps |
| T379 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1011549906 |
|
|
Mar 05 01:08:31 PM PST 24 |
Mar 05 01:09:34 PM PST 24 |
1296343400 ps |
| T318 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3981461874 |
|
|
Mar 05 01:08:27 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
2495253100 ps |
| T1144 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.558280841 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:08:59 PM PST 24 |
43123000 ps |
| T1145 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4227919940 |
|
|
Mar 05 01:08:31 PM PST 24 |
Mar 05 01:08:45 PM PST 24 |
86984300 ps |
| T1146 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3573874998 |
|
|
Mar 05 01:08:56 PM PST 24 |
Mar 05 01:09:10 PM PST 24 |
59516400 ps |
| T1147 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.343383370 |
|
|
Mar 05 01:08:44 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
235015200 ps |
| T252 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.903580555 |
|
|
Mar 05 01:08:42 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
307656900 ps |
| T1148 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.4072647518 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:49 PM PST 24 |
34966200 ps |
| T286 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2353674446 |
|
|
Mar 05 01:08:17 PM PST 24 |
Mar 05 01:08:39 PM PST 24 |
47082600 ps |
| T1149 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2327924731 |
|
|
Mar 05 01:08:55 PM PST 24 |
Mar 05 01:09:09 PM PST 24 |
52475800 ps |
| T319 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.882436953 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
749028700 ps |
| T1150 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3687724146 |
|
|
Mar 05 01:08:18 PM PST 24 |
Mar 05 01:08:37 PM PST 24 |
83071800 ps |
| T1151 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2206466904 |
|
|
Mar 05 01:08:52 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
15877900 ps |
| T1152 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2115043033 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
146670200 ps |
| T278 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3800935575 |
|
|
Mar 05 01:08:29 PM PST 24 |
Mar 05 01:08:47 PM PST 24 |
316337400 ps |
| T279 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2825379477 |
|
|
Mar 05 01:08:44 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
27625600 ps |
| T265 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2369762533 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:21:12 PM PST 24 |
1032308900 ps |
| T1153 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.654130924 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:50 PM PST 24 |
70616900 ps |
| T1154 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.455048288 |
|
|
Mar 05 01:08:40 PM PST 24 |
Mar 05 01:08:53 PM PST 24 |
43709900 ps |
| T1155 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1703840641 |
|
|
Mar 05 01:08:51 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
12058600 ps |
| T1156 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3209577302 |
|
|
Mar 05 01:08:47 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
14102100 ps |
| T1157 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2360831550 |
|
|
Mar 05 01:08:28 PM PST 24 |
Mar 05 01:08:42 PM PST 24 |
61135900 ps |
| T320 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1193747547 |
|
|
Mar 05 01:08:29 PM PST 24 |
Mar 05 01:08:50 PM PST 24 |
279177800 ps |
| T321 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1734305319 |
|
|
Mar 05 01:08:44 PM PST 24 |
Mar 05 01:09:00 PM PST 24 |
65211200 ps |
| T266 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.942941155 |
|
|
Mar 05 01:08:44 PM PST 24 |
Mar 05 01:16:20 PM PST 24 |
3764304800 ps |
| T1158 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3210887289 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
93700000 ps |
| T322 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1696306629 |
|
|
Mar 05 01:08:50 PM PST 24 |
Mar 05 01:09:09 PM PST 24 |
449744800 ps |
| T1159 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2254808389 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:00 PM PST 24 |
18407200 ps |
| T1160 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2773469147 |
|
|
Mar 05 01:08:26 PM PST 24 |
Mar 05 01:09:28 PM PST 24 |
2601873600 ps |
| T323 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3601551499 |
|
|
Mar 05 01:08:32 PM PST 24 |
Mar 05 01:09:29 PM PST 24 |
1447946400 ps |
| T1161 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2923549677 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:47 PM PST 24 |
16545900 ps |
| T275 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.236922524 |
|
|
Mar 05 01:08:47 PM PST 24 |
Mar 05 01:09:05 PM PST 24 |
335797500 ps |
| T276 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.219178438 |
|
|
Mar 05 01:08:41 PM PST 24 |
Mar 05 01:08:58 PM PST 24 |
362871500 ps |
| T1162 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1425079235 |
|
|
Mar 05 01:08:42 PM PST 24 |
Mar 05 01:08:58 PM PST 24 |
153824500 ps |
| T1163 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1231004274 |
|
|
Mar 05 01:08:37 PM PST 24 |
Mar 05 01:08:53 PM PST 24 |
12676400 ps |
| T1164 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3567842720 |
|
|
Mar 05 01:08:20 PM PST 24 |
Mar 05 01:08:36 PM PST 24 |
18475800 ps |
| T1165 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3398608655 |
|
|
Mar 05 01:08:32 PM PST 24 |
Mar 05 01:08:50 PM PST 24 |
86476100 ps |
| T1166 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.321826803 |
|
|
Mar 05 01:08:42 PM PST 24 |
Mar 05 01:08:59 PM PST 24 |
20618700 ps |
| T1167 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.961276693 |
|
|
Mar 05 01:08:30 PM PST 24 |
Mar 05 01:08:46 PM PST 24 |
133524700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.145050815 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:08:59 PM PST 24 |
18569400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2527870633 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:52 PM PST 24 |
136085100 ps |
| T277 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.902672629 |
|
|
Mar 05 01:08:25 PM PST 24 |
Mar 05 01:08:41 PM PST 24 |
235023700 ps |
| T1170 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.536363649 |
|
|
Mar 05 01:08:38 PM PST 24 |
Mar 05 01:08:55 PM PST 24 |
207466500 ps |
| T1171 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.12686528 |
|
|
Mar 05 01:09:17 PM PST 24 |
Mar 05 01:09:31 PM PST 24 |
36042600 ps |
| T1172 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3010597154 |
|
|
Mar 05 01:08:48 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
24482300 ps |
| T1173 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2230326223 |
|
|
Mar 05 01:08:49 PM PST 24 |
Mar 05 01:09:07 PM PST 24 |
204588500 ps |
| T1174 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4020384637 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:08:59 PM PST 24 |
21006300 ps |
| T1175 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3772170548 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:09:04 PM PST 24 |
152295800 ps |
| T1176 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3524019518 |
|
|
Mar 05 01:08:34 PM PST 24 |
Mar 05 01:08:55 PM PST 24 |
645710300 ps |
| T1177 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1056235522 |
|
|
Mar 05 01:08:53 PM PST 24 |
Mar 05 01:09:07 PM PST 24 |
121918000 ps |
| T1178 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4271089938 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:09:18 PM PST 24 |
169932900 ps |
| T375 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1149332599 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:16:18 PM PST 24 |
345005500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3452023950 |
|
|
Mar 05 01:08:47 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
14318700 ps |
| T1180 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2448250472 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:04 PM PST 24 |
27940500 ps |
| T1181 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1241198749 |
|
|
Mar 05 01:08:57 PM PST 24 |
Mar 05 01:09:11 PM PST 24 |
17621000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2175384494 |
|
|
Mar 05 01:08:53 PM PST 24 |
Mar 05 01:09:07 PM PST 24 |
24343800 ps |
| T368 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3153147717 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:23:46 PM PST 24 |
1355161600 ps |
| T255 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2430714142 |
|
|
Mar 05 01:08:26 PM PST 24 |
Mar 05 01:08:40 PM PST 24 |
17476400 ps |
| T1183 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3810480816 |
|
|
Mar 05 01:08:21 PM PST 24 |
Mar 05 01:08:36 PM PST 24 |
28146700 ps |
| T1184 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2878627748 |
|
|
Mar 05 01:08:34 PM PST 24 |
Mar 05 01:08:48 PM PST 24 |
54180700 ps |
| T1185 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3688808405 |
|
|
Mar 05 01:08:51 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
23828900 ps |
| T1186 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1788893096 |
|
|
Mar 05 01:08:41 PM PST 24 |
Mar 05 01:08:59 PM PST 24 |
61991200 ps |
| T256 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1861294742 |
|
|
Mar 05 01:08:32 PM PST 24 |
Mar 05 01:08:45 PM PST 24 |
106565600 ps |
| T373 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2522240607 |
|
|
Mar 05 01:08:28 PM PST 24 |
Mar 05 01:23:30 PM PST 24 |
2627951900 ps |
| T1187 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1143781372 |
|
|
Mar 05 01:08:32 PM PST 24 |
Mar 05 01:09:19 PM PST 24 |
29144600 ps |
| T1188 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.4047003683 |
|
|
Mar 05 01:08:55 PM PST 24 |
Mar 05 01:09:10 PM PST 24 |
28047200 ps |
| T294 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1427548790 |
|
|
Mar 05 01:08:42 PM PST 24 |
Mar 05 01:23:40 PM PST 24 |
3865929200 ps |
| T1189 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2668265868 |
|
|
Mar 05 01:08:52 PM PST 24 |
Mar 05 01:09:11 PM PST 24 |
83119700 ps |
| T1190 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.4105891243 |
|
|
Mar 05 01:08:36 PM PST 24 |
Mar 05 01:08:50 PM PST 24 |
164184700 ps |
| T1191 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3108493338 |
|
|
Mar 05 01:08:34 PM PST 24 |
Mar 05 01:08:47 PM PST 24 |
21166800 ps |
| T1192 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2566252449 |
|
|
Mar 05 01:08:51 PM PST 24 |
Mar 05 01:09:05 PM PST 24 |
30886800 ps |
| T1193 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.386598096 |
|
|
Mar 05 01:08:30 PM PST 24 |
Mar 05 01:08:46 PM PST 24 |
45394000 ps |
| T287 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3930621519 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:21:17 PM PST 24 |
1470695400 ps |
| T376 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1404186311 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:15:13 PM PST 24 |
190849600 ps |
| T288 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2249142251 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
81945600 ps |
| T1194 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1503598287 |
|
|
Mar 05 01:08:52 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
24714800 ps |
| T1195 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1646763426 |
|
|
Mar 05 01:08:47 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
11852700 ps |
| T1196 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3336364405 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
13874200 ps |
| T292 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1010767640 |
|
|
Mar 05 01:08:48 PM PST 24 |
Mar 05 01:09:07 PM PST 24 |
50026200 ps |
| T291 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2508192478 |
|
|
Mar 05 01:08:21 PM PST 24 |
Mar 05 01:23:27 PM PST 24 |
2012366100 ps |
| T1197 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4170248391 |
|
|
Mar 05 01:08:39 PM PST 24 |
Mar 05 01:08:55 PM PST 24 |
12354900 ps |
| T1198 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1156378421 |
|
|
Mar 05 01:08:29 PM PST 24 |
Mar 05 01:09:15 PM PST 24 |
46038500 ps |
| T1199 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3692248135 |
|
|
Mar 05 01:08:52 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
14678900 ps |
| T369 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1786408054 |
|
|
Mar 05 01:08:20 PM PST 24 |
Mar 05 01:23:18 PM PST 24 |
3248408800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2562952620 |
|
|
Mar 05 01:08:42 PM PST 24 |
Mar 05 01:08:58 PM PST 24 |
31848900 ps |
| T1201 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.4169804502 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
39279000 ps |
| T284 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.948794195 |
|
|
Mar 05 01:08:34 PM PST 24 |
Mar 05 01:08:50 PM PST 24 |
35326400 ps |
| T324 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1827681105 |
|
|
Mar 05 01:08:44 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
372960900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.471482561 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:51 PM PST 24 |
42664100 ps |
| T1203 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2829964581 |
|
|
Mar 05 01:08:50 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
50223400 ps |
| T1204 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4256840792 |
|
|
Mar 05 01:08:38 PM PST 24 |
Mar 05 01:08:56 PM PST 24 |
48592900 ps |
| T1205 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.4171299844 |
|
|
Mar 05 01:08:19 PM PST 24 |
Mar 05 01:08:33 PM PST 24 |
48582100 ps |
| T257 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1357477345 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:48 PM PST 24 |
20124500 ps |
| T258 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3723648280 |
|
|
Mar 05 01:08:38 PM PST 24 |
Mar 05 01:08:53 PM PST 24 |
18669400 ps |
| T1206 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.349548313 |
|
|
Mar 05 01:08:48 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
22868600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.919165645 |
|
|
Mar 05 01:08:31 PM PST 24 |
Mar 05 01:08:45 PM PST 24 |
45330800 ps |
| T1208 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1793901367 |
|
|
Mar 05 01:08:47 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
12437600 ps |
| T282 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1667608264 |
|
|
Mar 05 01:08:37 PM PST 24 |
Mar 05 01:08:53 PM PST 24 |
102315900 ps |
| T1209 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.732522088 |
|
|
Mar 05 01:08:52 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
17068300 ps |
| T1210 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2800216867 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
67051500 ps |
| T1211 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2741268473 |
|
|
Mar 05 01:08:18 PM PST 24 |
Mar 05 01:08:35 PM PST 24 |
14107900 ps |
| T325 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3984078996 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
359863200 ps |
| T1212 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.15299200 |
|
|
Mar 05 01:08:51 PM PST 24 |
Mar 05 01:09:09 PM PST 24 |
55451300 ps |
| T1213 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.732772422 |
|
|
Mar 05 01:08:38 PM PST 24 |
Mar 05 01:08:51 PM PST 24 |
20969700 ps |
| T1214 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2249111475 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:55 PM PST 24 |
84898300 ps |
| T1215 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1643562216 |
|
|
Mar 05 01:08:20 PM PST 24 |
Mar 05 01:08:36 PM PST 24 |
47270600 ps |
| T259 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.562205396 |
|
|
Mar 05 01:08:21 PM PST 24 |
Mar 05 01:08:36 PM PST 24 |
15847500 ps |
| T1216 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1329750116 |
|
|
Mar 05 01:08:51 PM PST 24 |
Mar 05 01:09:05 PM PST 24 |
17019100 ps |
| T285 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1192101878 |
|
|
Mar 05 01:08:47 PM PST 24 |
Mar 05 01:09:04 PM PST 24 |
92613200 ps |
| T1217 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2512494916 |
|
|
Mar 05 01:08:42 PM PST 24 |
Mar 05 01:08:55 PM PST 24 |
12855900 ps |
| T283 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1054093352 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:54 PM PST 24 |
159516300 ps |
| T1218 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3832578932 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:00 PM PST 24 |
17157300 ps |
| T1219 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.18139747 |
|
|
Mar 05 01:08:30 PM PST 24 |
Mar 05 01:09:16 PM PST 24 |
4976122400 ps |
| T1220 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1446118482 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:00 PM PST 24 |
50314500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2343597647 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:08:57 PM PST 24 |
15145200 ps |
| T1222 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.754802132 |
|
|
Mar 05 01:08:31 PM PST 24 |
Mar 05 01:10:04 PM PST 24 |
10216556600 ps |
| T1223 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3282313941 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
142194700 ps |
| T273 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2343892566 |
|
|
Mar 05 01:08:34 PM PST 24 |
Mar 05 01:08:50 PM PST 24 |
58473700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3724948380 |
|
|
Mar 05 01:08:34 PM PST 24 |
Mar 05 01:08:50 PM PST 24 |
333134000 ps |
| T1225 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.89102288 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:09:02 PM PST 24 |
32157100 ps |
| T370 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2909169769 |
|
|
Mar 05 01:08:41 PM PST 24 |
Mar 05 01:21:14 PM PST 24 |
1376183700 ps |
| T1226 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3854056629 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:09:00 PM PST 24 |
37485300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1462904460 |
|
|
Mar 05 01:08:26 PM PST 24 |
Mar 05 01:09:08 PM PST 24 |
339399000 ps |
| T290 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2994614633 |
|
|
Mar 05 01:08:42 PM PST 24 |
Mar 05 01:08:59 PM PST 24 |
37500500 ps |
| T374 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.321851015 |
|
|
Mar 05 01:08:44 PM PST 24 |
Mar 05 01:16:20 PM PST 24 |
1088701500 ps |
| T1228 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1110671103 |
|
|
Mar 05 01:08:34 PM PST 24 |
Mar 05 01:09:22 PM PST 24 |
1718564400 ps |
| T1229 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.407615507 |
|
|
Mar 05 01:08:47 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
91992300 ps |
| T377 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1623853403 |
|
|
Mar 05 01:08:34 PM PST 24 |
Mar 05 01:14:54 PM PST 24 |
1129083200 ps |
| T1230 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.607886600 |
|
|
Mar 05 01:08:30 PM PST 24 |
Mar 05 01:08:46 PM PST 24 |
45112300 ps |
| T1231 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3228397684 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
191806100 ps |
| T1232 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.992834355 |
|
|
Mar 05 01:08:30 PM PST 24 |
Mar 05 01:08:49 PM PST 24 |
173773600 ps |
| T1233 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2978213284 |
|
|
Mar 05 01:08:53 PM PST 24 |
Mar 05 01:09:08 PM PST 24 |
14950500 ps |
| T274 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2854072406 |
|
|
Mar 05 01:08:38 PM PST 24 |
Mar 05 01:08:55 PM PST 24 |
519378400 ps |
| T1234 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.938543601 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
13042900 ps |
| T1235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3303853723 |
|
|
Mar 05 01:08:28 PM PST 24 |
Mar 05 01:08:47 PM PST 24 |
160597400 ps |
| T1236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3093556560 |
|
|
Mar 05 01:08:31 PM PST 24 |
Mar 05 01:08:45 PM PST 24 |
16193700 ps |
| T1237 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1858044204 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:08:59 PM PST 24 |
44581300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1294797745 |
|
|
Mar 05 01:08:30 PM PST 24 |
Mar 05 01:08:53 PM PST 24 |
3296058800 ps |
| T1239 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3555973837 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:53 PM PST 24 |
624839200 ps |
| T1240 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1196127334 |
|
|
Mar 05 01:08:45 PM PST 24 |
Mar 05 01:08:59 PM PST 24 |
18226200 ps |
| T1241 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2159739174 |
|
|
Mar 05 01:08:37 PM PST 24 |
Mar 05 01:08:51 PM PST 24 |
43217600 ps |
| T289 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1977199567 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:05 PM PST 24 |
399345400 ps |
| T1242 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.4068949713 |
|
|
Mar 05 01:08:33 PM PST 24 |
Mar 05 01:08:47 PM PST 24 |
27471900 ps |
| T1243 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4103624043 |
|
|
Mar 05 01:08:22 PM PST 24 |
Mar 05 01:08:40 PM PST 24 |
27826900 ps |
| T1244 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2648909691 |
|
|
Mar 05 01:08:43 PM PST 24 |
Mar 05 01:09:00 PM PST 24 |
13469500 ps |
| T1245 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3948409825 |
|
|
Mar 05 01:08:46 PM PST 24 |
Mar 05 01:09:03 PM PST 24 |
17109300 ps |
| T1246 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1377089737 |
|
|
Mar 05 01:08:29 PM PST 24 |
Mar 05 01:08:45 PM PST 24 |
15140900 ps |
| T1247 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.43638444 |
|
|
Mar 05 01:08:41 PM PST 24 |
Mar 05 01:08:57 PM PST 24 |
30788800 ps |
| T1248 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2036647323 |
|
|
Mar 05 01:08:42 PM PST 24 |
Mar 05 01:09:01 PM PST 24 |
198189100 ps |
| T1249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4072625954 |
|
|
Mar 05 01:08:24 PM PST 24 |
Mar 05 01:08:38 PM PST 24 |
121847100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2191498523 |
|
|
Mar 05 01:08:37 PM PST 24 |
Mar 05 01:08:53 PM PST 24 |
20700600 ps |
| T1251 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.989237174 |
|
|
Mar 05 01:08:31 PM PST 24 |
Mar 05 01:09:41 PM PST 24 |
4469183300 ps |
| T1252 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.303184269 |
|
|
Mar 05 01:08:32 PM PST 24 |
Mar 05 01:15:00 PM PST 24 |
5669968300 ps |
| T1253 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2817854780 |
|
|
Mar 05 01:08:30 PM PST 24 |
Mar 05 01:09:35 PM PST 24 |
6571663900 ps |
| T1254 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1760914364 |
|
|
Mar 05 01:08:31 PM PST 24 |
Mar 05 01:08:47 PM PST 24 |
132051000 ps |
| T1255 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1161049572 |
|
|
Mar 05 01:08:51 PM PST 24 |
Mar 05 01:09:06 PM PST 24 |
15867500 ps |