Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	315375	1		T1	2		T2	1		T3	2
all_values[1]	315375	1		T1	2		T2	1		T3	2
all_values[2]	315375	1		T1	2		T2	1		T3	2
all_values[3]	315375	1		T1	2		T2	1		T3	2
all_values[4]	315375	1		T1	2		T2	1		T3	2
all_values[5]	315375	1		T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	637150	1		T1	12		T2	6		T3	12
auto[1]	1255100	1		T5	15600		T17	23348		T19	5056

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	923383	1		T1	7		T2	4		T3	7
auto[1]	968867	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	315230	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	145	1		T264	5		T327	1		T328	7
all_values[1]	auto[0]	auto[1]	315228	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	147	1		T264	4		T327	5		T328	6
all_values[2]	auto[0]	auto[0]	1606	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	46	1		T328	1		T329	1		T336	2
all_values[2]	auto[1]	auto[0]	313666	1		T5	3900		T17	5837		T19	1264
all_values[2]	auto[1]	auto[1]	57	1		T264	2		T328	3		T330	1
all_values[3]	auto[0]	auto[0]	1610	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	64	1		T264	1		T327	1		T328	3
all_values[3]	auto[1]	auto[0]	74113	1		T17	78		T19	632		T18	1032
all_values[3]	auto[1]	auto[1]	239588	1		T5	3900		T17	5759		T19	632
all_values[4]	auto[0]	auto[0]	1146	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	518	1		T1	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	216059	1		T5	2925		T17	4961		T19	632
all_values[4]	auto[1]	auto[1]	97652	1		T5	975		T17	876		T19	632
all_values[5]	auto[0]	auto[0]	1558	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	144	1		T27	1		T28	1		T29	1
all_values[5]	auto[1]	auto[0]	313625	1		T5	3900		T17	5837		T19	1264
all_values[5]	auto[1]	auto[1]	48	1		T264	3		T328	3		T330	1