Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T55 |
6 |
|
T226 |
1 |
|
T123 |
2 |
| others[1] |
108 |
1 |
|
T3 |
1 |
|
T55 |
1 |
|
T48 |
1 |
| others[2] |
92 |
1 |
|
T55 |
1 |
|
T123 |
2 |
|
T87 |
1 |
| others[3] |
171 |
1 |
|
T47 |
1 |
|
T55 |
6 |
|
T234 |
1 |
| false |
54 |
1 |
|
T55 |
3 |
|
T123 |
2 |
|
T85 |
1 |
| true |
6302 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
268 |
1 |
|
T47 |
1 |
|
T55 |
11 |
|
T96 |
1 |
| others[1] |
243 |
1 |
|
T3 |
1 |
|
T50 |
1 |
|
T207 |
1 |
| others[2] |
221 |
1 |
|
T16 |
1 |
|
T55 |
13 |
|
T93 |
1 |
| others[3] |
367 |
1 |
|
T30 |
1 |
|
T55 |
12 |
|
T48 |
1 |
| false |
129 |
1 |
|
T55 |
5 |
|
T123 |
1 |
|
T59 |
1 |
| true |
5612 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1076 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T39 |
14 |
| others[1] |
1008 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T7 |
1 |
| others[2] |
1050 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T5 |
1 |
| others[3] |
1741 |
1 |
|
T1 |
30 |
|
T4 |
8 |
|
T19 |
1 |
| false |
578 |
1 |
|
T1 |
8 |
|
T27 |
1 |
|
T18 |
1 |
| true |
1387 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T118 |
1 |
|
T55 |
11 |
|
T48 |
1 |
| others[1] |
236 |
1 |
|
T20 |
1 |
|
T101 |
1 |
|
T55 |
7 |
| others[2] |
251 |
1 |
|
T50 |
1 |
|
T47 |
1 |
|
T55 |
9 |
| others[3] |
373 |
1 |
|
T17 |
1 |
|
T55 |
20 |
|
T123 |
2 |
| false |
137 |
1 |
|
T55 |
8 |
|
T123 |
1 |
|
T86 |
1 |
| true |
5623 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T50 |
1 |
|
T55 |
11 |
|
T48 |
1 |
| others[1] |
208 |
1 |
|
T47 |
1 |
|
T55 |
7 |
|
T48 |
1 |
| others[2] |
212 |
1 |
|
T28 |
1 |
|
T55 |
10 |
|
T8 |
1 |
| others[3] |
354 |
1 |
|
T27 |
1 |
|
T104 |
1 |
|
T55 |
20 |
| false |
119 |
1 |
|
T3 |
1 |
|
T55 |
8 |
|
T123 |
1 |
| true |
5736 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T39 |
13 |
| others[1] |
1223 |
1 |
|
T1 |
12 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1256 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T18 |
1 |
| others[3] |
2041 |
1 |
|
T1 |
26 |
|
T4 |
7 |
|
T6 |
1 |
| false |
677 |
1 |
|
T1 |
11 |
|
T19 |
1 |
|
T39 |
11 |
| true |
439 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T1 |
12 |
|
T4 |
3 |
|
T39 |
10 |
| others[1] |
1205 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
1285 |
1 |
|
T1 |
21 |
|
T4 |
5 |
|
T19 |
1 |
| others[3] |
2043 |
1 |
|
T1 |
28 |
|
T4 |
3 |
|
T7 |
1 |
| false |
628 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T39 |
4 |
| true |
434 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T55 |
6 |
|
T234 |
1 |
|
T123 |
1 |
| others[1] |
106 |
1 |
|
T104 |
1 |
|
T55 |
4 |
|
T123 |
5 |
| others[2] |
99 |
1 |
|
T55 |
3 |
|
T123 |
1 |
|
T203 |
1 |
| others[3] |
165 |
1 |
|
T55 |
4 |
|
T123 |
2 |
|
T87 |
1 |
| false |
57 |
1 |
|
T55 |
1 |
|
T87 |
1 |
|
T356 |
2 |
| true |
6306 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T17 |
1 |
|
T30 |
1 |
|
T118 |
1 |
| others[1] |
218 |
1 |
|
T27 |
1 |
|
T47 |
1 |
|
T55 |
8 |
| others[2] |
247 |
1 |
|
T55 |
13 |
|
T85 |
1 |
|
T87 |
1 |
| others[3] |
407 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| false |
109 |
1 |
|
T28 |
1 |
|
T55 |
3 |
|
T48 |
1 |
| true |
5642 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1112 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T27 |
1 |
| others[1] |
1045 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
1094 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T17 |
1 |
| others[3] |
1691 |
1 |
|
T1 |
23 |
|
T4 |
6 |
|
T66 |
1 |
| false |
555 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T39 |
5 |
| true |
1343 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T55 |
12 |
|
T123 |
2 |
|
T97 |
1 |
| others[1] |
220 |
1 |
|
T17 |
1 |
|
T28 |
1 |
|
T207 |
1 |
| others[2] |
254 |
1 |
|
T55 |
12 |
|
T48 |
1 |
|
T123 |
1 |
| others[3] |
389 |
1 |
|
T18 |
1 |
|
T104 |
1 |
|
T55 |
17 |
| false |
110 |
1 |
|
T27 |
1 |
|
T101 |
1 |
|
T55 |
4 |
| true |
5636 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T28 |
1 |
|
T55 |
9 |
|
T48 |
1 |
| others[1] |
241 |
1 |
|
T55 |
10 |
|
T123 |
3 |
|
T59 |
1 |
| others[2] |
208 |
1 |
|
T55 |
8 |
|
T87 |
1 |
|
T62 |
1 |
| others[3] |
376 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T55 |
13 |
| false |
104 |
1 |
|
T55 |
4 |
|
T48 |
1 |
|
T203 |
1 |
| true |
5690 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T19 |
1 |
| others[1] |
1205 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T17 |
1 |
| others[2] |
1217 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T39 |
22 |
| others[3] |
2069 |
1 |
|
T1 |
23 |
|
T4 |
5 |
|
T7 |
1 |
| false |
662 |
1 |
|
T1 |
11 |
|
T4 |
3 |
|
T5 |
1 |
| true |
442 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1212 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T39 |
12 |
| others[1] |
1237 |
1 |
|
T1 |
13 |
|
T4 |
5 |
|
T39 |
17 |
| others[2] |
1237 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
2063 |
1 |
|
T1 |
21 |
|
T4 |
5 |
|
T7 |
1 |
| false |
660 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T19 |
1 |
| true |
431 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T55 |
4 |
|
T234 |
1 |
|
T123 |
3 |
| others[1] |
125 |
1 |
|
T55 |
4 |
|
T123 |
2 |
|
T357 |
1 |
| others[2] |
104 |
1 |
|
T55 |
5 |
|
T123 |
4 |
|
T85 |
1 |
| others[3] |
177 |
1 |
|
T55 |
6 |
|
T48 |
1 |
|
T226 |
1 |
| false |
72 |
1 |
|
T55 |
2 |
|
T76 |
1 |
|
T100 |
2 |
| true |
6265 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T181 |
1 |
|
T55 |
12 |
|
T115 |
1 |
| others[1] |
232 |
1 |
|
T55 |
8 |
|
T123 |
1 |
|
T99 |
1 |
| others[2] |
231 |
1 |
|
T27 |
1 |
|
T47 |
1 |
|
T55 |
12 |
| others[3] |
366 |
1 |
|
T16 |
1 |
|
T28 |
1 |
|
T20 |
1 |
| false |
148 |
1 |
|
T30 |
1 |
|
T55 |
5 |
|
T8 |
1 |
| true |
5630 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
994 |
1 |
|
T1 |
13 |
|
T4 |
1 |
|
T7 |
1 |
| others[1] |
1067 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T12 |
1 |
| others[2] |
1080 |
1 |
|
T1 |
13 |
|
T4 |
6 |
|
T5 |
1 |
| others[3] |
1781 |
1 |
|
T1 |
30 |
|
T3 |
1 |
|
T4 |
5 |
| false |
530 |
1 |
|
T1 |
7 |
|
T19 |
1 |
|
T39 |
4 |
| true |
1388 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T118 |
1 |
|
T207 |
1 |
|
T55 |
12 |
| others[1] |
206 |
1 |
|
T47 |
1 |
|
T55 |
10 |
|
T123 |
3 |
| others[2] |
246 |
1 |
|
T18 |
1 |
|
T101 |
1 |
|
T55 |
12 |
| others[3] |
403 |
1 |
|
T17 |
1 |
|
T28 |
1 |
|
T181 |
1 |
| false |
124 |
1 |
|
T55 |
7 |
|
T208 |
1 |
|
T324 |
1 |
| true |
5620 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T55 |
11 |
|
T123 |
1 |
|
T75 |
1 |
| others[1] |
216 |
1 |
|
T104 |
1 |
|
T55 |
11 |
|
T85 |
1 |
| others[2] |
220 |
1 |
|
T55 |
7 |
|
T123 |
1 |
|
T86 |
1 |
| others[3] |
365 |
1 |
|
T55 |
21 |
|
T48 |
1 |
|
T123 |
2 |
| false |
107 |
1 |
|
T55 |
1 |
|
T226 |
1 |
|
T8 |
1 |
| true |
5722 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T39 |
14 |
| others[1] |
1203 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T19 |
1 |
| others[2] |
1217 |
1 |
|
T1 |
15 |
|
T7 |
1 |
|
T66 |
1 |
| others[3] |
2060 |
1 |
|
T1 |
25 |
|
T4 |
5 |
|
T39 |
31 |
| false |
658 |
1 |
|
T1 |
7 |
|
T4 |
3 |
|
T5 |
1 |
| true |
454 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T1 |
17 |
|
T4 |
2 |
|
T5 |
1 |
| others[1] |
1168 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T66 |
1 |
| others[2] |
1261 |
1 |
|
T1 |
13 |
|
T4 |
3 |
|
T39 |
16 |
| others[3] |
2050 |
1 |
|
T1 |
27 |
|
T4 |
3 |
|
T39 |
33 |
| false |
681 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T6 |
1 |
| true |
421 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T55 |
1 |
|
T48 |
1 |
|
T123 |
2 |
| others[1] |
97 |
1 |
|
T55 |
1 |
|
T123 |
2 |
|
T75 |
1 |
| others[2] |
112 |
1 |
|
T55 |
4 |
|
T48 |
2 |
|
T123 |
2 |
| others[3] |
174 |
1 |
|
T55 |
7 |
|
T123 |
2 |
|
T85 |
1 |
| false |
41 |
1 |
|
T234 |
1 |
|
T123 |
1 |
|
T76 |
2 |
| true |
6305 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T47 |
1 |
|
T55 |
8 |
|
T48 |
1 |
| others[1] |
230 |
1 |
|
T55 |
10 |
|
T123 |
1 |
|
T87 |
1 |
| others[2] |
213 |
1 |
|
T3 |
1 |
|
T55 |
7 |
|
T48 |
1 |
| others[3] |
389 |
1 |
|
T181 |
1 |
|
T204 |
1 |
|
T55 |
15 |
| false |
145 |
1 |
|
T29 |
1 |
|
T55 |
9 |
|
T96 |
1 |
| true |
5649 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1016 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T7 |
1 |
| others[1] |
1051 |
1 |
|
T1 |
19 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
1046 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T66 |
1 |
| others[3] |
1804 |
1 |
|
T1 |
32 |
|
T4 |
9 |
|
T39 |
15 |
| false |
554 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T19 |
1 |
| true |
1369 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T181 |
1 |
|
T55 |
16 |
|
T48 |
1 |
| others[1] |
229 |
1 |
|
T50 |
1 |
|
T18 |
1 |
|
T55 |
5 |
| others[2] |
221 |
1 |
|
T55 |
6 |
|
T123 |
1 |
|
T76 |
12 |
| others[3] |
407 |
1 |
|
T55 |
16 |
|
T48 |
2 |
|
T123 |
2 |
| false |
124 |
1 |
|
T55 |
4 |
|
T48 |
1 |
|
T226 |
1 |
| true |
5636 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T55 |
6 |
|
T87 |
1 |
|
T8 |
1 |
| others[1] |
241 |
1 |
|
T47 |
1 |
|
T55 |
12 |
|
T226 |
1 |
| others[2] |
230 |
1 |
|
T55 |
7 |
|
T48 |
1 |
|
T123 |
2 |
| others[3] |
361 |
1 |
|
T55 |
17 |
|
T123 |
1 |
|
T85 |
1 |
| false |
119 |
1 |
|
T28 |
1 |
|
T55 |
7 |
|
T356 |
1 |
| true |
5646 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T5 |
1 |
| others[1] |
1234 |
1 |
|
T1 |
16 |
|
T3 |
1 |
|
T4 |
5 |
| others[2] |
1260 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T39 |
20 |
| others[3] |
2009 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T19 |
1 |
| false |
643 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T7 |
1 |
| true |
431 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1290 |
1 |
|
T1 |
21 |
|
T4 |
1 |
|
T66 |
1 |
| others[1] |
1228 |
1 |
|
T1 |
21 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
1270 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T39 |
20 |
| others[3] |
2015 |
1 |
|
T1 |
16 |
|
T4 |
6 |
|
T7 |
1 |
| false |
609 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T39 |
6 |
| true |
428 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T55 |
6 |
|
T123 |
1 |
|
T357 |
1 |
| others[1] |
108 |
1 |
|
T29 |
1 |
|
T104 |
1 |
|
T55 |
6 |
| others[2] |
113 |
1 |
|
T3 |
1 |
|
T55 |
3 |
|
T123 |
2 |
| others[3] |
164 |
1 |
|
T55 |
5 |
|
T123 |
1 |
|
T85 |
1 |
| false |
54 |
1 |
|
T55 |
4 |
|
T123 |
4 |
|
T62 |
1 |
| true |
6291 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T17 |
1 |
|
T207 |
1 |
|
T55 |
10 |
| others[1] |
227 |
1 |
|
T28 |
1 |
|
T101 |
1 |
|
T55 |
6 |
| others[2] |
235 |
1 |
|
T29 |
1 |
|
T181 |
1 |
|
T30 |
1 |
| others[3] |
377 |
1 |
|
T20 |
1 |
|
T47 |
1 |
|
T118 |
1 |
| false |
141 |
1 |
|
T55 |
5 |
|
T360 |
1 |
|
T8 |
1 |
| true |
5610 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1090 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
1020 |
1 |
|
T1 |
21 |
|
T4 |
3 |
|
T39 |
9 |
| others[2] |
1067 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T7 |
1 |
| others[3] |
1787 |
1 |
|
T1 |
20 |
|
T4 |
4 |
|
T66 |
1 |
| false |
518 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T39 |
5 |
| true |
1358 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |