Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T27 |
1 |
|
T50 |
1 |
|
T207 |
1 |
| others[1] |
211 |
1 |
|
T28 |
1 |
|
T55 |
11 |
|
T48 |
2 |
| others[2] |
233 |
1 |
|
T20 |
1 |
|
T118 |
1 |
|
T55 |
9 |
| others[3] |
406 |
1 |
|
T3 |
1 |
|
T55 |
16 |
|
T48 |
2 |
| false |
102 |
1 |
|
T29 |
1 |
|
T55 |
5 |
|
T123 |
1 |
| true |
5655 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T27 |
1 |
|
T55 |
10 |
|
T48 |
1 |
| others[1] |
219 |
1 |
|
T29 |
1 |
|
T55 |
12 |
|
T123 |
1 |
| others[2] |
252 |
1 |
|
T50 |
1 |
|
T55 |
11 |
|
T123 |
2 |
| others[3] |
359 |
1 |
|
T28 |
1 |
|
T55 |
21 |
|
T48 |
1 |
| false |
127 |
1 |
|
T47 |
1 |
|
T55 |
5 |
|
T76 |
8 |
| true |
5653 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1202 |
1 |
|
T1 |
18 |
|
T4 |
3 |
|
T5 |
1 |
| others[1] |
1286 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T7 |
1 |
| others[2] |
1217 |
1 |
|
T1 |
11 |
|
T4 |
5 |
|
T39 |
23 |
| others[3] |
2034 |
1 |
|
T1 |
24 |
|
T4 |
3 |
|
T19 |
1 |
| false |
673 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T39 |
12 |
| true |
428 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1225 |
1 |
|
T1 |
14 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
1188 |
1 |
|
T1 |
15 |
|
T4 |
6 |
|
T7 |
1 |
| others[2] |
1266 |
1 |
|
T1 |
19 |
|
T4 |
1 |
|
T39 |
12 |
| others[3] |
2081 |
1 |
|
T1 |
21 |
|
T4 |
3 |
|
T19 |
1 |
| false |
660 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T39 |
9 |
| true |
420 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T3 |
1 |
|
T55 |
10 |
|
T123 |
2 |
| others[1] |
99 |
1 |
|
T55 |
4 |
|
T48 |
1 |
|
T123 |
1 |
| others[2] |
90 |
1 |
|
T55 |
2 |
|
T123 |
3 |
|
T87 |
1 |
| others[3] |
174 |
1 |
|
T50 |
1 |
|
T55 |
5 |
|
T123 |
3 |
| false |
50 |
1 |
|
T55 |
2 |
|
T234 |
1 |
|
T85 |
1 |
| true |
6310 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T28 |
1 |
|
T55 |
11 |
|
T48 |
2 |
| others[1] |
221 |
1 |
|
T17 |
1 |
|
T101 |
1 |
|
T104 |
1 |
| others[2] |
246 |
1 |
|
T207 |
1 |
|
T55 |
12 |
|
T115 |
1 |
| others[3] |
379 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T30 |
1 |
| false |
115 |
1 |
|
T55 |
4 |
|
T48 |
1 |
|
T96 |
1 |
| true |
5627 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1080 |
1 |
|
T1 |
22 |
|
T4 |
4 |
|
T28 |
1 |
| others[1] |
1056 |
1 |
|
T1 |
12 |
|
T4 |
4 |
|
T5 |
1 |
| others[2] |
1052 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T27 |
1 |
| others[3] |
1737 |
1 |
|
T1 |
28 |
|
T4 |
3 |
|
T66 |
1 |
| false |
534 |
1 |
|
T1 |
5 |
|
T39 |
3 |
|
T95 |
2 |
| true |
1381 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T55 |
10 |
|
T48 |
1 |
|
T87 |
1 |
| others[1] |
230 |
1 |
|
T104 |
1 |
|
T207 |
1 |
|
T55 |
6 |
| others[2] |
217 |
1 |
|
T17 |
1 |
|
T55 |
9 |
|
T48 |
1 |
| others[3] |
395 |
1 |
|
T28 |
1 |
|
T20 |
1 |
|
T101 |
1 |
| false |
122 |
1 |
|
T55 |
5 |
|
T76 |
5 |
|
T100 |
3 |
| true |
5633 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T55 |
8 |
|
T226 |
1 |
|
T359 |
1 |
| others[1] |
240 |
1 |
|
T28 |
1 |
|
T47 |
1 |
|
T55 |
10 |
| others[2] |
216 |
1 |
|
T55 |
11 |
|
T48 |
1 |
|
T123 |
2 |
| others[3] |
391 |
1 |
|
T29 |
1 |
|
T55 |
11 |
|
T234 |
1 |
| false |
125 |
1 |
|
T55 |
5 |
|
T123 |
2 |
|
T87 |
1 |
| true |
5658 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T1 |
12 |
|
T4 |
2 |
|
T12 |
1 |
| others[1] |
1174 |
1 |
|
T1 |
19 |
|
T4 |
5 |
|
T66 |
1 |
| others[2] |
1313 |
1 |
|
T1 |
22 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
2065 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T28 |
1 |
| false |
626 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T39 |
13 |
| true |
435 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T1 |
14 |
|
T4 |
5 |
|
T19 |
1 |
| others[1] |
1255 |
1 |
|
T1 |
10 |
|
T4 |
4 |
|
T5 |
1 |
| others[2] |
1250 |
1 |
|
T1 |
24 |
|
T4 |
2 |
|
T39 |
20 |
| others[3] |
2075 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T7 |
1 |
| false |
637 |
1 |
|
T1 |
8 |
|
T66 |
1 |
|
T39 |
7 |
| true |
420 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T55 |
3 |
|
T123 |
1 |
|
T357 |
1 |
| others[1] |
110 |
1 |
|
T55 |
4 |
|
T123 |
1 |
|
T85 |
1 |
| others[2] |
97 |
1 |
|
T55 |
4 |
|
T48 |
1 |
|
T76 |
2 |
| others[3] |
156 |
1 |
|
T28 |
1 |
|
T55 |
4 |
|
T123 |
6 |
| false |
61 |
1 |
|
T55 |
6 |
|
T234 |
1 |
|
T123 |
1 |
| true |
6317 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T55 |
10 |
|
T85 |
1 |
|
T87 |
1 |
| others[1] |
253 |
1 |
|
T47 |
1 |
|
T55 |
6 |
|
T123 |
2 |
| others[2] |
251 |
1 |
|
T101 |
1 |
|
T104 |
1 |
|
T118 |
1 |
| others[3] |
390 |
1 |
|
T50 |
1 |
|
T20 |
1 |
|
T181 |
1 |
| false |
99 |
1 |
|
T6 |
1 |
|
T55 |
5 |
|
T59 |
1 |
| true |
5594 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1054 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
1069 |
1 |
|
T1 |
14 |
|
T66 |
1 |
|
T39 |
10 |
| others[2] |
1016 |
1 |
|
T1 |
13 |
|
T4 |
6 |
|
T7 |
1 |
| others[3] |
1741 |
1 |
|
T1 |
29 |
|
T4 |
5 |
|
T6 |
1 |
| false |
554 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T39 |
4 |
| true |
1406 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T55 |
6 |
|
T287 |
1 |
|
T358 |
1 |
| others[1] |
215 |
1 |
|
T29 |
1 |
|
T47 |
1 |
|
T104 |
1 |
| others[2] |
231 |
1 |
|
T55 |
9 |
|
T75 |
1 |
|
T26 |
1 |
| others[3] |
389 |
1 |
|
T17 |
1 |
|
T27 |
1 |
|
T50 |
1 |
| false |
118 |
1 |
|
T55 |
6 |
|
T123 |
1 |
|
T76 |
6 |
| true |
5657 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T55 |
15 |
|
T226 |
1 |
|
T63 |
1 |
| others[1] |
227 |
1 |
|
T55 |
11 |
|
T48 |
1 |
|
T123 |
1 |
| others[2] |
223 |
1 |
|
T55 |
7 |
|
T48 |
1 |
|
T234 |
1 |
| others[3] |
365 |
1 |
|
T27 |
1 |
|
T104 |
1 |
|
T55 |
20 |
| false |
134 |
1 |
|
T47 |
1 |
|
T55 |
7 |
|
T8 |
1 |
| true |
5678 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T1 |
24 |
|
T4 |
3 |
|
T39 |
13 |
| others[1] |
1201 |
1 |
|
T1 |
14 |
|
T4 |
1 |
|
T7 |
1 |
| others[2] |
1179 |
1 |
|
T1 |
9 |
|
T4 |
3 |
|
T27 |
1 |
| others[3] |
2142 |
1 |
|
T1 |
24 |
|
T4 |
5 |
|
T5 |
1 |
| false |
670 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T19 |
1 |
| true |
424 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T39 |
25 |
| others[1] |
1223 |
1 |
|
T1 |
15 |
|
T4 |
5 |
|
T7 |
1 |
| others[2] |
1211 |
1 |
|
T1 |
14 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
2079 |
1 |
|
T1 |
24 |
|
T4 |
6 |
|
T6 |
1 |
| false |
666 |
1 |
|
T1 |
9 |
|
T39 |
18 |
|
T95 |
8 |
| true |
426 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T55 |
5 |
|
T123 |
3 |
|
T361 |
1 |
| others[1] |
101 |
1 |
|
T47 |
1 |
|
T104 |
1 |
|
T55 |
3 |
| others[2] |
108 |
1 |
|
T55 |
1 |
|
T75 |
1 |
|
T87 |
1 |
| others[3] |
178 |
1 |
|
T55 |
9 |
|
T234 |
1 |
|
T123 |
3 |
| false |
51 |
1 |
|
T55 |
1 |
|
T123 |
2 |
|
T76 |
1 |
| true |
6307 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T16 |
1 |
|
T27 |
1 |
|
T101 |
1 |
| others[1] |
248 |
1 |
|
T55 |
5 |
|
T48 |
1 |
|
T123 |
1 |
| others[2] |
233 |
1 |
|
T20 |
1 |
|
T55 |
9 |
|
T48 |
1 |
| others[3] |
398 |
1 |
|
T3 |
1 |
|
T47 |
1 |
|
T104 |
1 |
| false |
121 |
1 |
|
T28 |
1 |
|
T55 |
8 |
|
T123 |
1 |
| true |
5597 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T1 |
14 |
|
T4 |
1 |
|
T39 |
13 |
| others[1] |
1020 |
1 |
|
T1 |
18 |
|
T4 |
3 |
|
T66 |
1 |
| others[2] |
1037 |
1 |
|
T1 |
20 |
|
T4 |
3 |
|
T19 |
1 |
| others[3] |
1777 |
1 |
|
T1 |
18 |
|
T3 |
1 |
|
T4 |
6 |
| false |
567 |
1 |
|
T1 |
8 |
|
T16 |
1 |
|
T17 |
1 |
| true |
1376 |
1 |
|
T6 |
1 |
|
T28 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T55 |
10 |
|
T48 |
3 |
|
T123 |
2 |
| others[1] |
233 |
1 |
|
T29 |
1 |
|
T101 |
1 |
|
T55 |
15 |
| others[2] |
246 |
1 |
|
T20 |
1 |
|
T104 |
1 |
|
T55 |
12 |
| others[3] |
395 |
1 |
|
T18 |
1 |
|
T47 |
1 |
|
T55 |
15 |
| false |
106 |
1 |
|
T181 |
1 |
|
T207 |
1 |
|
T55 |
7 |
| true |
5612 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T104 |
1 |
|
T55 |
11 |
|
T48 |
1 |
| others[1] |
221 |
1 |
|
T28 |
1 |
|
T55 |
9 |
|
T48 |
1 |
| others[2] |
214 |
1 |
|
T50 |
1 |
|
T29 |
1 |
|
T55 |
12 |
| others[3] |
372 |
1 |
|
T27 |
1 |
|
T55 |
15 |
|
T123 |
2 |
| false |
122 |
1 |
|
T55 |
2 |
|
T87 |
2 |
|
T59 |
1 |
| true |
5671 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T6 |
1 |
| others[1] |
1269 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
1243 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T66 |
1 |
| others[3] |
2040 |
1 |
|
T1 |
20 |
|
T4 |
7 |
|
T7 |
1 |
| false |
603 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T19 |
1 |
| true |
426 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1257 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T39 |
18 |
| others[1] |
1231 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T7 |
1 |
| others[2] |
1191 |
1 |
|
T1 |
22 |
|
T4 |
3 |
|
T39 |
19 |
| others[3] |
2081 |
1 |
|
T1 |
25 |
|
T4 |
6 |
|
T5 |
1 |
| false |
656 |
1 |
|
T1 |
8 |
|
T50 |
1 |
|
T66 |
1 |
| true |
424 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T55 |
6 |
|
T48 |
1 |
|
T123 |
4 |
| others[1] |
110 |
1 |
|
T27 |
1 |
|
T55 |
4 |
|
T48 |
1 |
| others[2] |
100 |
1 |
|
T47 |
1 |
|
T55 |
4 |
|
T234 |
1 |
| others[3] |
172 |
1 |
|
T55 |
7 |
|
T48 |
1 |
|
T123 |
2 |
| false |
63 |
1 |
|
T29 |
1 |
|
T55 |
3 |
|
T76 |
3 |
| true |
6292 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T18 |
1 |
|
T55 |
7 |
|
T48 |
1 |
| others[1] |
233 |
1 |
|
T30 |
1 |
|
T55 |
7 |
|
T226 |
1 |
| others[2] |
258 |
1 |
|
T17 |
1 |
|
T28 |
1 |
|
T47 |
1 |
| others[3] |
354 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T204 |
1 |
| false |
134 |
1 |
|
T6 |
1 |
|
T29 |
1 |
|
T20 |
1 |
| true |
5627 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1034 |
1 |
|
T1 |
13 |
|
T4 |
3 |
|
T16 |
1 |
| others[1] |
1055 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T39 |
12 |
| others[2] |
1056 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T5 |
1 |
| others[3] |
1758 |
1 |
|
T1 |
24 |
|
T4 |
7 |
|
T7 |
1 |
| false |
550 |
1 |
|
T1 |
7 |
|
T39 |
3 |
|
T69 |
1 |
| true |
1387 |
1 |
|
T3 |
1 |
|
T28 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T55 |
5 |
|
T85 |
1 |
|
T87 |
1 |
| others[1] |
229 |
1 |
|
T3 |
1 |
|
T104 |
1 |
|
T118 |
1 |
| others[2] |
238 |
1 |
|
T181 |
1 |
|
T55 |
11 |
|
T123 |
1 |
| others[3] |
350 |
1 |
|
T55 |
18 |
|
T48 |
2 |
|
T123 |
1 |
| false |
127 |
1 |
|
T18 |
1 |
|
T29 |
1 |
|
T55 |
2 |
| true |
5672 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T27 |
1 |
|
T55 |
11 |
|
T48 |
1 |
| others[1] |
204 |
1 |
|
T29 |
1 |
|
T55 |
6 |
|
T123 |
1 |
| others[2] |
237 |
1 |
|
T28 |
1 |
|
T50 |
1 |
|
T55 |
12 |
| others[3] |
345 |
1 |
|
T55 |
19 |
|
T48 |
1 |
|
T123 |
2 |
| false |
114 |
1 |
|
T55 |
4 |
|
T86 |
1 |
|
T87 |
1 |
| true |
5711 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T39 |
14 |
| others[1] |
1190 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T7 |
1 |
| others[2] |
1279 |
1 |
|
T1 |
13 |
|
T4 |
3 |
|
T66 |
1 |
| others[3] |
2071 |
1 |
|
T1 |
23 |
|
T4 |
4 |
|
T5 |
1 |
| false |
627 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T39 |
9 |
| true |
440 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |