Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T7 |
1 |
| others[1] |
1224 |
1 |
|
T1 |
19 |
|
T4 |
3 |
|
T18 |
1 |
| others[2] |
1253 |
1 |
|
T1 |
13 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
2055 |
1 |
|
T1 |
24 |
|
T4 |
3 |
|
T39 |
31 |
| false |
657 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T39 |
4 |
| true |
422 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T55 |
4 |
|
T48 |
1 |
|
T226 |
1 |
| others[1] |
115 |
1 |
|
T55 |
3 |
|
T48 |
1 |
|
T123 |
1 |
| others[2] |
118 |
1 |
|
T55 |
6 |
|
T234 |
1 |
|
T123 |
1 |
| others[3] |
173 |
1 |
|
T55 |
8 |
|
T48 |
2 |
|
T123 |
3 |
| false |
45 |
1 |
|
T123 |
2 |
|
T361 |
1 |
|
T76 |
1 |
| true |
6285 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T30 |
1 |
|
T101 |
1 |
|
T55 |
12 |
| others[1] |
227 |
1 |
|
T17 |
1 |
|
T55 |
8 |
|
T123 |
1 |
| others[2] |
216 |
1 |
|
T27 |
1 |
|
T55 |
9 |
|
T226 |
1 |
| others[3] |
397 |
1 |
|
T3 |
1 |
|
T55 |
9 |
|
T115 |
1 |
| false |
141 |
1 |
|
T29 |
1 |
|
T181 |
1 |
|
T55 |
2 |
| true |
5631 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T1 |
14 |
|
T4 |
4 |
|
T39 |
11 |
| others[1] |
1068 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
1065 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T17 |
1 |
| others[3] |
1748 |
1 |
|
T1 |
26 |
|
T3 |
1 |
|
T4 |
4 |
| false |
547 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T39 |
2 |
| true |
1347 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T47 |
1 |
|
T118 |
1 |
|
T55 |
7 |
| others[1] |
222 |
1 |
|
T3 |
1 |
|
T27 |
1 |
|
T55 |
13 |
| others[2] |
237 |
1 |
|
T55 |
12 |
|
T48 |
1 |
|
T234 |
1 |
| others[3] |
385 |
1 |
|
T28 |
1 |
|
T104 |
1 |
|
T55 |
9 |
| false |
112 |
1 |
|
T20 |
1 |
|
T181 |
1 |
|
T55 |
5 |
| true |
5666 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T55 |
15 |
|
T8 |
1 |
|
T362 |
1 |
| others[1] |
221 |
1 |
|
T104 |
1 |
|
T55 |
7 |
|
T123 |
1 |
| others[2] |
223 |
1 |
|
T55 |
6 |
|
T123 |
1 |
|
T85 |
1 |
| others[3] |
374 |
1 |
|
T3 |
1 |
|
T27 |
1 |
|
T28 |
1 |
| false |
123 |
1 |
|
T55 |
3 |
|
T123 |
1 |
|
T62 |
1 |
| true |
5660 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1214 |
1 |
|
T1 |
14 |
|
T4 |
1 |
|
T39 |
15 |
| others[1] |
1253 |
1 |
|
T1 |
9 |
|
T4 |
5 |
|
T39 |
19 |
| others[2] |
1173 |
1 |
|
T1 |
20 |
|
T4 |
2 |
|
T7 |
1 |
| others[3] |
2106 |
1 |
|
T1 |
25 |
|
T4 |
4 |
|
T5 |
1 |
| false |
634 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T39 |
11 |
| true |
460 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1285 |
1 |
|
T1 |
23 |
|
T4 |
3 |
|
T39 |
17 |
| others[1] |
1196 |
1 |
|
T1 |
8 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
1229 |
1 |
|
T1 |
16 |
|
T19 |
1 |
|
T39 |
20 |
| others[3] |
2037 |
1 |
|
T1 |
25 |
|
T4 |
7 |
|
T18 |
1 |
| false |
662 |
1 |
|
T1 |
6 |
|
T66 |
1 |
|
T39 |
8 |
| true |
431 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T55 |
3 |
|
T48 |
1 |
|
T85 |
1 |
| others[1] |
84 |
1 |
|
T55 |
3 |
|
T123 |
1 |
|
T356 |
2 |
| others[2] |
119 |
1 |
|
T55 |
3 |
|
T123 |
4 |
|
T76 |
5 |
| others[3] |
181 |
1 |
|
T3 |
1 |
|
T55 |
8 |
|
T234 |
1 |
| false |
54 |
1 |
|
T55 |
1 |
|
T123 |
1 |
|
T87 |
1 |
| true |
6309 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T55 |
5 |
|
T48 |
1 |
|
T75 |
1 |
| others[1] |
253 |
1 |
|
T50 |
1 |
|
T118 |
1 |
|
T55 |
9 |
| others[2] |
241 |
1 |
|
T55 |
18 |
|
T123 |
1 |
|
T97 |
1 |
| others[3] |
380 |
1 |
|
T29 |
1 |
|
T55 |
19 |
|
T48 |
1 |
| false |
118 |
1 |
|
T18 |
1 |
|
T55 |
3 |
|
T48 |
1 |
| true |
5623 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1040 |
1 |
|
T1 |
17 |
|
T4 |
5 |
|
T39 |
18 |
| others[1] |
1095 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1043 |
1 |
|
T1 |
17 |
|
T4 |
2 |
|
T7 |
1 |
| others[3] |
1774 |
1 |
|
T1 |
24 |
|
T4 |
4 |
|
T17 |
1 |
| false |
538 |
1 |
|
T1 |
6 |
|
T39 |
7 |
|
T21 |
1 |
| true |
1350 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T118 |
1 |
|
T55 |
14 |
|
T48 |
1 |
| others[1] |
229 |
1 |
|
T17 |
1 |
|
T29 |
1 |
|
T207 |
1 |
| others[2] |
231 |
1 |
|
T28 |
1 |
|
T18 |
1 |
|
T20 |
1 |
| others[3] |
402 |
1 |
|
T181 |
1 |
|
T55 |
19 |
|
T48 |
2 |
| false |
121 |
1 |
|
T3 |
1 |
|
T55 |
3 |
|
T93 |
1 |
| true |
5616 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T50 |
1 |
|
T55 |
7 |
|
T123 |
2 |
| others[1] |
205 |
1 |
|
T29 |
1 |
|
T55 |
10 |
|
T48 |
1 |
| others[2] |
220 |
1 |
|
T104 |
1 |
|
T55 |
10 |
|
T123 |
1 |
| others[3] |
381 |
1 |
|
T55 |
15 |
|
T226 |
1 |
|
T123 |
1 |
| false |
111 |
1 |
|
T3 |
1 |
|
T55 |
7 |
|
T76 |
9 |
| true |
5689 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T66 |
1 |
| others[1] |
1266 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T39 |
18 |
| others[2] |
1184 |
1 |
|
T1 |
11 |
|
T4 |
4 |
|
T39 |
24 |
| others[3] |
2052 |
1 |
|
T1 |
32 |
|
T4 |
6 |
|
T7 |
1 |
| false |
633 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T5 |
1 |
| true |
451 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1208 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T39 |
23 |
| others[1] |
1213 |
1 |
|
T1 |
12 |
|
T4 |
5 |
|
T66 |
1 |
| others[2] |
1258 |
1 |
|
T1 |
27 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
2070 |
1 |
|
T1 |
23 |
|
T4 |
4 |
|
T19 |
1 |
| false |
663 |
1 |
|
T1 |
6 |
|
T39 |
9 |
|
T95 |
6 |
| true |
428 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
86 |
1 |
|
T29 |
1 |
|
T55 |
4 |
|
T123 |
1 |
| others[1] |
119 |
1 |
|
T55 |
3 |
|
T226 |
1 |
|
T123 |
5 |
| others[2] |
86 |
1 |
|
T55 |
1 |
|
T48 |
2 |
|
T85 |
1 |
| others[3] |
170 |
1 |
|
T55 |
9 |
|
T48 |
1 |
|
T234 |
1 |
| false |
46 |
1 |
|
T55 |
1 |
|
T100 |
4 |
|
T213 |
1 |
| true |
6333 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
256 |
1 |
|
T207 |
1 |
|
T55 |
12 |
|
T48 |
2 |
| others[1] |
244 |
1 |
|
T55 |
13 |
|
T96 |
1 |
|
T123 |
1 |
| others[2] |
206 |
1 |
|
T16 |
1 |
|
T55 |
6 |
|
T93 |
1 |
| others[3] |
378 |
1 |
|
T28 |
1 |
|
T50 |
1 |
|
T118 |
1 |
| false |
121 |
1 |
|
T47 |
1 |
|
T104 |
1 |
|
T55 |
4 |
| true |
5635 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1103 |
1 |
|
T1 |
20 |
|
T4 |
4 |
|
T7 |
1 |
| others[1] |
1034 |
1 |
|
T1 |
14 |
|
T66 |
1 |
|
T39 |
7 |
| others[2] |
1074 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T16 |
1 |
| others[3] |
1749 |
1 |
|
T1 |
23 |
|
T4 |
6 |
|
T5 |
1 |
| false |
528 |
1 |
|
T1 |
6 |
|
T19 |
1 |
|
T39 |
5 |
| true |
1352 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T27 |
1 |
|
T55 |
9 |
|
T48 |
1 |
| others[1] |
213 |
1 |
|
T3 |
1 |
|
T101 |
1 |
|
T55 |
9 |
| others[2] |
222 |
1 |
|
T29 |
1 |
|
T55 |
11 |
|
T287 |
1 |
| others[3] |
386 |
1 |
|
T28 |
1 |
|
T20 |
1 |
|
T55 |
15 |
| false |
112 |
1 |
|
T55 |
3 |
|
T123 |
1 |
|
T76 |
7 |
| true |
5690 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T55 |
7 |
|
T48 |
1 |
|
T123 |
1 |
| others[1] |
201 |
1 |
|
T55 |
10 |
|
T86 |
1 |
|
T8 |
1 |
| others[2] |
225 |
1 |
|
T3 |
1 |
|
T47 |
1 |
|
T55 |
9 |
| others[3] |
383 |
1 |
|
T55 |
19 |
|
T123 |
1 |
|
T203 |
1 |
| false |
135 |
1 |
|
T104 |
1 |
|
T55 |
6 |
|
T234 |
1 |
| true |
5677 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T1 |
18 |
|
T4 |
4 |
|
T39 |
21 |
| others[1] |
1195 |
1 |
|
T1 |
12 |
|
T4 |
4 |
|
T39 |
19 |
| others[2] |
1225 |
1 |
|
T1 |
20 |
|
T7 |
1 |
|
T66 |
1 |
| others[3] |
2114 |
1 |
|
T1 |
21 |
|
T4 |
3 |
|
T5 |
1 |
| false |
627 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T39 |
9 |
| true |
445 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T1 |
15 |
|
T4 |
4 |
|
T5 |
1 |
| others[1] |
1275 |
1 |
|
T1 |
20 |
|
T4 |
2 |
|
T19 |
1 |
| others[2] |
1202 |
1 |
|
T1 |
16 |
|
T6 |
1 |
|
T18 |
1 |
| others[3] |
2076 |
1 |
|
T1 |
21 |
|
T4 |
4 |
|
T66 |
1 |
| false |
635 |
1 |
|
T1 |
6 |
|
T4 |
3 |
|
T39 |
11 |
| true |
425 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T55 |
4 |
|
T123 |
1 |
|
T203 |
1 |
| others[1] |
110 |
1 |
|
T55 |
3 |
|
T123 |
1 |
|
T361 |
1 |
| others[2] |
94 |
1 |
|
T55 |
3 |
|
T123 |
1 |
|
T76 |
3 |
| others[3] |
177 |
1 |
|
T55 |
2 |
|
T234 |
1 |
|
T123 |
6 |
| false |
50 |
1 |
|
T55 |
3 |
|
T357 |
1 |
|
T356 |
1 |
| true |
6307 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T6 |
1 |
|
T55 |
6 |
|
T123 |
1 |
| others[1] |
263 |
1 |
|
T16 |
1 |
|
T55 |
11 |
|
T96 |
1 |
| others[2] |
233 |
1 |
|
T181 |
1 |
|
T101 |
1 |
|
T104 |
1 |
| others[3] |
369 |
1 |
|
T3 |
1 |
|
T204 |
1 |
|
T55 |
15 |
| false |
111 |
1 |
|
T30 |
1 |
|
T55 |
4 |
|
T123 |
1 |
| true |
5633 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1047 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T18 |
1 |
| others[1] |
1073 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T19 |
1 |
| others[2] |
1048 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T16 |
1 |
| others[3] |
1778 |
1 |
|
T1 |
26 |
|
T3 |
1 |
|
T4 |
6 |
| false |
530 |
1 |
|
T1 |
8 |
|
T39 |
8 |
|
T95 |
5 |
| true |
1364 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T118 |
1 |
|
T55 |
11 |
|
T234 |
1 |
| others[1] |
211 |
1 |
|
T28 |
1 |
|
T29 |
1 |
|
T55 |
9 |
| others[2] |
232 |
1 |
|
T55 |
12 |
|
T93 |
1 |
|
T123 |
1 |
| others[3] |
440 |
1 |
|
T50 |
1 |
|
T47 |
1 |
|
T55 |
19 |
| false |
126 |
1 |
|
T207 |
1 |
|
T55 |
6 |
|
T76 |
5 |
| true |
5605 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T55 |
7 |
|
T123 |
1 |
|
T357 |
1 |
| others[1] |
229 |
1 |
|
T3 |
1 |
|
T27 |
1 |
|
T55 |
8 |
| others[2] |
194 |
1 |
|
T55 |
9 |
|
T123 |
2 |
|
T87 |
1 |
| others[3] |
384 |
1 |
|
T50 |
1 |
|
T55 |
14 |
|
T48 |
1 |
| false |
122 |
1 |
|
T28 |
1 |
|
T55 |
4 |
|
T8 |
1 |
| true |
5696 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1206 |
1 |
|
T1 |
8 |
|
T4 |
4 |
|
T28 |
1 |
| others[1] |
1207 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T5 |
1 |
| others[2] |
1260 |
1 |
|
T1 |
15 |
|
T4 |
4 |
|
T39 |
19 |
| others[3] |
2101 |
1 |
|
T1 |
30 |
|
T4 |
3 |
|
T7 |
1 |
| false |
626 |
1 |
|
T1 |
12 |
|
T39 |
6 |
|
T32 |
1 |
| true |
440 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T14 |
1 |
|
T35 |
1 |
|
T169 |
1 |
| others[1] |
8 |
1 |
|
T36 |
1 |
|
T363 |
1 |
|
T364 |
1 |
| others[2] |
10 |
1 |
|
T160 |
1 |
|
T166 |
1 |
|
T163 |
1 |
| others[3] |
11 |
1 |
|
T171 |
1 |
|
T150 |
1 |
|
T365 |
1 |
| false |
3 |
1 |
|
T366 |
1 |
|
T367 |
1 |
|
T368 |
1 |
| true |
51 |
1 |
|
T103 |
1 |
|
T73 |
1 |
|
T160 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T24 |
1 |
|
T369 |
1 |
|
T370 |
1 |
| others[1] |
2 |
1 |
|
T371 |
1 |
|
T372 |
1 |
|
- |
- |
| others[2] |
2 |
1 |
|
T373 |
1 |
|
T374 |
1 |
|
- |
- |
| others[3] |
2 |
1 |
|
T375 |
1 |
|
T376 |
1 |
|
- |
- |
| false |
14 |
1 |
|
T180 |
1 |
|
T350 |
1 |
|
T377 |
1 |
| true |
23 |
1 |
|
T25 |
1 |
|
T179 |
1 |
|
T378 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T379 |
1 |
|
T380 |
1 |
|
T381 |
1 |
| others[1] |
3 |
1 |
|
T382 |
1 |
|
T383 |
1 |
|
T384 |
1 |
| others[2] |
6 |
1 |
|
T385 |
1 |
|
T386 |
1 |
|
T387 |
1 |
| others[3] |
3 |
1 |
|
T376 |
1 |
|
T372 |
1 |
|
T388 |
1 |
| false |
9 |
1 |
|
T24 |
1 |
|
T179 |
1 |
|
T373 |
1 |
| true |
22 |
1 |
|
T25 |
1 |
|
T180 |
1 |
|
T378 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |